CN103094068B - High density embedded capacitor and preparation method thereof - Google Patents
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- 238000000034 method Methods 0.000 claims abstract description 60
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- 239000010703 silicon Substances 0.000 claims description 31
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- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 239000004411 aluminium Substances 0.000 claims description 7
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- 238000001704 evaporation Methods 0.000 claims description 4
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- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
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Abstract
The embodiment of the invention discloses a kind of high density embedded capacitor and preparation method thereof, the method comprises: provide the substrate with body layer and etching barrier layer; Multiple perpendicularity is formed good and there is the groove of high-aspect-ratio in body layer surface; Bulk layer mate-rial between the bottom of groove, sidewall and adjacent trenches is adulterated, obtains the doped region of this capacitor, to form three-dimensional PN junction in body layer and doped region contact area; Form the first electrode and second electrode of this capacitor, the polarity of described first electrode and the second electrode is contrary, and electrical insulation therebetween, the first electrode is positioned at both sides, doped region or surrounding, and the second electrode is positioned at doped region on the surface.The embodiment of the present invention adopts 3 D stereo groove to make the dielectric layer of capacitor, the effective area of dielectric layer is made to be far longer than the effective area of the dielectric layer of conventional capacitor, improve the capacitance density of capacitor, enable this capacitor meet the requirement of low frequency decoupling and high frequency decoupling simultaneously.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly, relate to a kind of high density embedded capacitor and preparation method thereof.
Background technology
Rapid raising along with various functional circuit integrated level and the needs to functional module and components and parts miniaturization, integrating passive technology becomes a kind of discrete passive component that replaces to reach the solution of device miniaturization.In various typical circuit, the assembly of 80% is passive device, and they have accounted for the area of nearly 50% on printed circuit board (PCB).At system in package (System-in-Package, be called for short SiP, or System-on-Package, be called for short SOP) in technology, can adopt integrating passive technology that different passive devices or passive module are imbedded or are integrated on substrate, greatly can reduce the area of substrate, become and realize one of integrated method of effective system.And capacitor as the most common on substrate be also the maximum components and parts of distribution, make the integrated technology of capacitor become the key technology of integrating passive technology.
Along with the development of System-in-Package technology, the operating frequency of electronic system is more and more higher, a large amount of SMD (surfacemounteddevices) electric capacity has not only had a strong impact on the miniaturization of electronic system, and more and more can not meet the requirement of High frequency filter decoupling of electronic system, therefore development place embedded capacitance technology gradually.Embedded capacitor is because of without the need to being drawn by circuit, and more traditional SMD capacitor has less dead resistance and inductance, can be applied to widely in the highly dense electronic system of high frequency.
In actual applications, the stray inductance intrinsic due to capacitor and resistance, any one capacitor is all difficult to the full frequency band decoupling of accomplishing from low to high.In general, the capacitance of capacitor is larger, and decoupling effect is better, but volume also can be larger, and the good resistance of stray inductance of generation is also larger, poorer to the decoupling effect of high frequency; Otherwise capacitor capacitance is less, and volume is less, stray inductance and resistance less, therefore can be used for high frequency, but due to capacitance little, decoupling effect is just poor.Therefore, to make the decoupling effect of couple capacitors low frequency and high frequency all better, a kind of volume will be made little, but the capacitor that capacitance is larger, this just requires that the capacitance density of capacitor wants large.
The mode that three-dimensional capacitor of the prior art increases capacitance density is mainly based on the MIMIMI...M structure of metal-insulator-metal (MIM) structure and multiple-level stack, especially be applied to silica-based on Embedded capacitance, but the capacitance density representative value of this capacitor is 0.7 ~ 0.9nF/cm
2, be the ideal chose of low value application, but due to its capacitance density this limitation little, be difficult to meet the requirement of decoupling 1nF ~ 100nF capacitance under radio frequency, be namely difficult to the requirement meeting high frequency decoupling.Therefore, be badly in need of working out the large capacitor of a kind of capacitance density, the requirement of low frequency decoupling and high frequency decoupling can be met simultaneously.
Summary of the invention
Embodiments provide a kind of high density embedded capacitor and preparation method thereof, improve the capacitance density of capacitor, make the effect of this couple capacitors high frequency decoupling and low frequency decoupling all good, the requirement of low frequency decoupling and high frequency decoupling can be met simultaneously.
For achieving the above object, following technical scheme is embodiments provided:
A kind of high density embedded capacitor manufacture method, comprising:
There is provided substrate, described substrate comprises body layer and is positioned at the etching barrier layer on described body layer surface;
Multiple groove figure is formed in described etching barrier layer surface;
To have the etching barrier layer of described groove figure for mask, in described body layer surface, form multiple groove, described groove vertical degree is good and have high-aspect-ratio;
Remove the etching barrier layer materials between adjacent trenches, to form the doped region figure of this capacitor on the surface at described etching barrier layer;
There is the etching barrier layer of described doped region figure for mask, bulk layer mate-rial between the bottom of described groove, sidewall and adjacent trenches is adulterated, obtain the doped region of this capacitor, to form three-dimensional PN junction in described body layer and described doped region contact area;
Retain the partial etching barrier material at next-door neighbour edge, described doped region, remove the partial etching barrier material of both sides, described doped region or surrounding, expose part body layer material, as the first region of this capacitor;
The first metal layer is formed on the surface in described body layer, described the first metal layer and described doped region material and all form ohmic contact between described the first metal layer and described bulk layer mate-rial, described the first metal layer covers the doped region material between the bottom of described the first region and described groove, sidewall and adjacent trenches;
Remove part the first metal layer material, form the first electrode and second electrode of this capacitor, the polarity of described first electrode and the second electrode is contrary, and electrical insulation therebetween, described first electrode is positioned at both sides or the surrounding of described doped region, described second electrode is positioned at described doped region on the surface, and wherein, the part the first metal layer material of removal is located close on the partial etching barrier layer surface at edge, described doped region.
Preferably, also comprise after forming the first electrode and the second electrode, described first electrode and the second electrode surface form the second metal level, to draw described first electrode and the second electrode.
Preferably, the depth-to-width ratio of described groove is between 1: 1-10: 1.
Preferably, the degree of depth of described groove is between 2 μm-100 μm.
Preferably, the thickness of the bulk layer mate-rial between described adjacent trenches is greater than 2 times of the thickness of described doped region, and is less than 20 μm.
Preferably, the thickness of described doped region is between 0.1 μm-3 μm.
Preferably, the method forming described doped region is, high-temperature diffusion process is adopted to form described doped region, this process is specially, and under the high temperature within 1000 DEG C-1200 DEG C, carries out the prediffusion of 1min-10min, with make the concentration stabilize of diffuse source remain on preset concentration under, keep described high temperature and preset concentration afterwards, spread continuously, comprise the overall time of the described High temperature diffusion of described prediffusion time within 10min-90min.
Preferably, described bulk layer mate-rial is P-type silicon substrate, and described doped region is N-type doping, and the diffuse source of described doped region is POCl3, and described preset concentration is 8 × 1020cm-3, and the overall time of described High temperature diffusion is 80min.
Preferably, the resistivity of described P-type silicon substrate is between 0.01 Ω cm-0.5 Ω cm.
Preferably, described multiple groove is that array is distributed in described body layer surface.
Preferably, the shape of cross section of described groove is regular hexagon, circle or square.
Preferably, described the first metal layer material is aluminium, and described second metal layer material is gold.
The embodiment of the invention also discloses a kind of high density embedded capacitor adopting said method to make, comprising:
Body layer, in described body layer surface, there is multiple groove, bulk layer mate-rial between the bottom of described groove, sidewall and adjacent trenches has the doped region of certain doping content and doping thickness, described body layer and described doped region contact area are three-dimensional PN junction region;
Be positioned at the first electrode on the body layer surface of both sides, described doped region or surrounding, be positioned at described doped region on the surface and cover the second electrode of the bulk layer mate-rial between the bottom of described groove, sidewall and adjacent trenches, the polarity of described first electrode and the second electrode is contrary, and electrical insulation therebetween, described first electrode and the second electrode are all formed in the first metal layer surface, and the two is formed in same photoetching and etch step;
Be close to the etching barrier layer on the body layer surface at edge, described doped region, described etching barrier layer by described first electrode and the second electrode isolation, to make electrical insulation between described first electrode and the second electrode.
Preferably, described bulk layer mate-rial is P-type silicon substrate, and described doped region is N-type doping, and the resistivity of described P-type silicon substrate is at 0.01 Ω cm-0.5 Ω cm, and the thickness of described doped region is between 0.1 μm-3 μm.
Compared with prior art, technique scheme has the following advantages:
High density embedded capacitor that the embodiment of the present invention provides and preparation method thereof, break away from the constraint of MIMIMI...M multilayer " sandwich " structure of conventional three-dimensional capacitor, overturn the structure of traditional capacitor plane formula, 3 D stereo groove is adopted to make two interelectrode dielectric layers of capacitor, namely the first electrode in the present embodiment and the second electrode are equivalent to two opposite polarity pole plates of capacitor, the PN junction that body layer and doped region contact area are formed is equivalent to the dielectric layer between capacitor two pole plates, because groove structure is 3-D solid structure, therefore the effective area of dielectric layer is far longer than the effective area of the dielectric layer of mim structure capacitor, thus improve the capacitance density of capacitor.
Further, the quantity of the groove of the capacitor in the present embodiment, depth-to-width ratio, distribution mode and distribution density can change accordingly according to the requirement of different capacitors, thus meet the requirement of different capacitors to capacitance density.And in theory, the capacitance density of the capacitor in the present embodiment can up to 10nF/mm
2-15nF/mm
2, the requirement of low frequency decoupling and high frequency decoupling can be met simultaneously.
Accompanying drawing explanation
Shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawing indicates identical part.Deliberately do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on purport of the present invention is shown.
The profile of Fig. 1-10 high density embedded capacitor manufacture method disclosed in the embodiment of the present invention;
The vertical view of Figure 11 high density embedded capacitor disclosed in the embodiment of the present invention.
Embodiment
As described in background, the capacitor of the MIMIMI...M structure of prior art is subject to the restriction of planar configuration, and capacitance density is little, is difficult to the requirement meeting high frequency decoupling.In other words, the capacitance density of capacitor of the prior art is little, under being difficult to be applied to the environment for use of high and low frequency, is namely difficult to the requirement simultaneously meeting low frequency decoupling and high frequency decoupling simultaneously.
Based on above reason, inventor considers, to the requirement enabling a kind of capacitor meet low frequency decoupling and high frequency decoupling simultaneously, the capacitance density of capacitor must be improved, reach this purpose, can consider from three-dimension packaging angle, 3-D solid structure is introduced in capacitor arrangement, 3-D solid structure is changed into by planar configuration by capacitor, owing to spatially having expanded a dimension, the capacitance density of the capacitor of 3-D solid structure will inevitably obtain and greatly improve, thus can meet the requirement of low frequency decoupling and high frequency decoupling simultaneously.
It is more than the core concept of the application, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Embodiments provide a kind of high density embedded capacitor manufacture method, the profile of its each step is as shown in Fig. 1-Figure 10, and the method comprises:
Step 1: as shown in Figure 1, provides substrate, the etching barrier layer 102 that described substrate comprises body layer 101 and is positioned on described body layer surface;
In packaging technology, often use intermediate layer or the substrate carrier as the protection to packed element, electrical connection, mechanical support and heat management, the welding spot reliability that traditional organic material substrate often causes because thermal coefficient of expansion is different declines, high power consumption element can not efficiently radiates heat.
Use silicon substrate as passive device substrate and intermediate layer or substrate in the present embodiment, its major advantage is, on the one hand can make integrated of the high-quality of passive component by the relatively low silicon technology of use cost, on the other hand because passive device is identical with the base material of active device, when the two connects, the internal mutual line of fine pith can be adopted to interconnect, and the mismatch caused because of thermal expansion like this will very little or almost not have, thus makes the performance of device reach optimum.
Therefore, the attention of scientist has more and more been obtained using silicon as capacitive substrate, all passive components can be integrated on one piece of silicon substrate as NXP just represents existing, by face-down bonding technique (Flip-Chip), active chip is connected with this silicon substrate, realizes GSM RF front-end module function.The three-dimensional capacitance technology that NXP company utilizes DRIEtching technology to realize, it achieves large capacitance electric capacity on a silicon substrate embedding.But the manufacturing process of this electric capacity is very complicated, bring certain difficulty to concrete manufacture.Therefore, a kind of method of simple making three-dimensional silicon-based capacitor is embodiments provided.
It should be noted that, substrate in the present embodiment can comprise semiconductor element, the silicon of such as monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe), also the semiconductor structure of mixing can be comprised, such as carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination; Also can be silicon-on-insulator (SOI).In addition, semiconductor base can also comprise other material, the sandwich construction of such as epitaxial loayer or oxygen buried layer.Although there is described herein several examples of the material that can form substrate, all the spirit and scope of the present invention can be fallen into as any material of semiconductor base.
Body layer 101 in the present embodiment is preferably silicon substrate, preferred, and the silicon substrate in the present embodiment is P type or the N-type silicon substrate of low-resistance, and described low-resistance refers to that resistivity is between 0.01 Ω cm-0.5 Ω cm.Capacitor in the present embodiment makes based on the barrier capacitance theory based on PN junction, mainly between body layer and doped region, form PN junction, it will be appreciated by those skilled in the art that, body layer 101 can be P type also can be N-type, only for P-type silicon substrate in the present embodiment and following examples, the structure of this capacitor and manufacture method are described in detail.
The effect of etching barrier layer 102 described in the present embodiment is as mask in the manufacturing process of capacitor; and physical protection and electrical insulation are carried out to device; described etching barrier layer 102 is preferably silicon oxide layer; the mode of at high temperature carrying out thermal oxidation specifically can be adopted to be formed, and the thickness of this etching barrier layer 102 is preferably
Step 2: as shown in Figure 2, forms multiple groove figure 104 in described etching barrier layer 102 surface;
This process is specially, and first at etching barrier layer 102 spin coating photoresist layer 103 on the surface, in order to ensure exposure accuracy, also can form anti-reflecting layer (not shown) between photoresist layer and etching barrier layer 102, to reduce unnecessary reflection; The mask plate with multiple groove figure is adopted to expose photoresist layer 103, develop afterwards, multiple groove figure is formed on the surface at described photoresist layer, afterwards there is the photoresist layer 103 of multiple groove figure for mask, adopt wet etching or dry etch process, remove not by the etching barrier layer materials that photoresist layer 103 covers, thus form multiple groove figure 104 in etching barrier layer 102 surface.
The adopted positive photoresist of this photoetching process also can adopt negative photoresist, as AZ5214 reversion glue, AZ5214 is positive photoresist, but also can be used as negative photoresist in some cases, as long as adopt photoresist to do mask in the present embodiment, specifically how to operate, be not specifically limited, as long as multiple channel patterns can be obtained on the surface at photoresist layer.
In addition, in the present embodiment, do not limit the mode removing etching barrier layer materials yet, remove etching barrier layer materials (SiO according to wet corrosion technique
2), solution used can be NH
4the mixed solution of F (solution concentration is 40%) and HF (solution concentration is 40%), NH
4f solution and HF solution by volume 3: 1 mix after, corrode etching barrier layer 102, etching time is about 5min, for avoiding etching barrier layer materials not clean up, also can carry out the over etching of about 1min.
Step 3: as shown in Figure 3, to have the etching barrier layer 102 of described groove figure 104 for mask, forms multiple groove 105 in described body layer 101 surface, and described groove 105 perpendicularity well and have high-aspect-ratio;
Preferably, the depth-to-width ratio of described groove is between 1: 1-10: 1, preferred, the depth-to-width ratio of described groove is 5: 1, on this basis, preferably, the degree of depth of described groove is between 2um-100um, preferred, and the degree of depth of described groove is between 30um-80um.
Concrete, the photoresist layer 103 with multiple groove figure and etching barrier layer 102 can be adopted to be mask, adopt dry etching or wet corrosion technique, remove not by the bulk layer mate-rial that photoresist layer 103 and etching barrier layer 102 cover, in described body layer 101 surface, form multiple groove 105.
Preferably adopt dry etch process to remove not by the bulk layer mate-rial that photoresist layer 103 and etching barrier layer 102 cover in the present embodiment, etching apparatus is sense coupling (ICP) equipment, and the plasma gas of employing is SF
6and C
2h
4mist, etching process and polymer deposition process can be adopted to carry out respectively and the mode switched fast etches, i.e. " Boach " technique, thus obtain high-aspect-ratio and the good groove structure of perpendicularity.
It should be noted that, the shape of cross section of the plurality of groove 105 and the degree of depth can be determined according to the requirement of couple capacitors capacitance density, and its shape of cross section can have any shape, and are preferably regular shape in the present embodiment, as regular hexagon, circle or square etc., be more preferably regular hexagon.Further, the arrangement mode of multiple groove is also arbitrary, and arrange more intensive, capacitance density is larger, and being preferably multiple groove in the present embodiment is that array is distributed in described body layer surface, as shown in figure 11.
Step 4: see Fig. 3 and Fig. 4, removes the etching barrier layer materials (as shown in the label 106 in Fig. 3) between adjacent trenches 105, to form the doped region figure of this capacitor on the surface at described etching barrier layer;
Concrete, see Fig. 3, chemical cleaning technology is first adopted to remove photoresist layer 103, afterwards there is the etching barrier layer 102 spin coating photoresist (not shown) on the surface of multiple groove figure, the mask plate with doped region figure is adopted to expose photoresist layer afterwards, development, doped region figure is formed on the surface at described photoresist layer, afterwards there is the photoresist layer of doped region figure for mask, wet etching is adopted to remove not by etching barrier layer materials that photoresist layer covers, namely the etching barrier layer materials 106 between adjacent trenches 105 is removed, to form the doped region figure of this capacitor on the surface at described etching barrier layer, namely in body layer surface, doped region is formed, namely effective PN junction region of capacitor, the thickness of doped region i.e. the junction depth of PN junction, afterwards, chemical cleaning technology is adopted to remove photoresist layer, specifically acetone can be adopted, the solution etc. that removes photoresist removes photoresist layer.
Wet corrosion technique in this process can be identical with above step with the corrosive liquid of employing, also can be different, as long as ensure in corrosion process as far as possible little to the injury of body layer.
Step 5: as shown in Figure 4, there is the etching barrier layer of described doped region figure for mask, bulk layer mate-rial between the bottom of described groove, sidewall and adjacent trenches is adulterated, obtain the doped region 107 of this capacitor, to form three-dimensional PN junction in described body layer and described doped region contact area;
Concrete, high-temperature diffusion process can be adopted in the present embodiment to form described doped region 107, this process is specially, under high temperature within 1000 DEG C-1200 DEG C, carry out the prediffusion of 1min-10min, with make the concentration stabilize of diffuse source remain on preset concentration under, keep described high temperature and preset concentration afterwards, spread continuously, comprise the overall time of the described High temperature diffusion of described prediffusion time within 10min-90min.
It will be understood by those skilled in the art that described body layer is different with the dopant type of described doped region, can form PN junction, be P type low-resistance silicon substrate with bulk layer mate-rial in the present embodiment, doped region is that N-type is doped to example, and the diffuse source of described doped region is POCl
3, described preset concentration is 8 × 10
20cm
-3, the overall time of described High temperature diffusion is preferably 80min.
After above-mentioned high-temperature diffusion process, obtain the doped region 107 of this capacitor.It should be noted that, the capacitance of capacitor and capacitance density are directly related with the thickness of described doped region, the thickness of doped region is less, capacitance density is larger, thickness is larger, capacitance density is less, but the thickness of doped region is less, breakdown risk is also larger, therefore, in the present embodiment, the thickness of this doped region 107 is selected between 0.1 μm-3 μm, be preferably between 0.5 μm-1.5 μm, the thickness of doped region is more preferably 1 μm, but specifically why be worth, can determine according to the requirement of capacitance density, in the present embodiment, too much restriction is not done to this.
It will be appreciated by those skilled in the art that, doping particle in order to avoid adjacent trenches sidewall contacts with each other and short circuit phenomenon between the adjacent trenches caused, the thickness of the bulk layer mate-rial between described adjacent trenches must be greater than 2 times of the thickness of described doped region, the thickness of the bulk layer mate-rial in the present embodiment between adjacent trenches is less than 20 μm, if the thickness of described doped region is 1 μm, the thickness of the bulk layer mate-rial then between adjacent trenches is just greater than 2 μm, and is less than 20 μm.
Step 6: as shown in Figure 5, retains the partial etching barrier material at next-door neighbour edge, described doped region, removes the partial etching barrier material of both sides, described doped region or surrounding, expose part body layer material, as the first region 110 of this capacitor;
This process is specially, photoetching process is adopted to form the photoresist layer 108 with the first region figure on the surface at described etching barrier layer 102 and doped region 107, this photoresist layer 108 covers the partial etching barrier material (as shown in label in Fig. 5 109 region) at next-door neighbour edge, described doped region, wet corrosion technique is adopted to remove not by etching barrier layer materials that photoresist layer 108 covers afterwards, expose part body layer material, obtain the first region 110 of this capacitor, remove photoresist layer 108 afterwards.The first region 110 only can be positioned at the both sides of doped region, also can be positioned at the surrounding of doped region.The photoresist that this photoetching process adopts can be AZ5214 photoresist, and also can be S9920 photoresist, wet etching mode and corrosive liquid also can be identical with the wet etching course in above step.
Step 7: see Fig. 6, the first metal layer 111 is formed on the surface in described body layer, described the first metal layer 111 all forms ohmic contact with body layer 101 storeroom described in described doped region 107 material and described the first metal layer and 111, and described the first metal layer 111 covers the doped region material between the bottom of described the first region 110 and described groove 105, sidewall and adjacent trenches;
The effect of the first metal layer in the present embodiment forms ohmic contact with doped region and the first region, as long as the therefore metal material of conduction, in the present embodiment, the first metal layer material is preferably aluminium, the mode such as magnetron sputtering or evaporation can be adopted to form the first metal layer 111, and its thickness is about 1 μm.Because the depth-to-width ratio of groove is comparatively large, therefore, trenched side-wall and the subregional metallic aluminum of base portion thinner, but must ensure that the ohmic contact in each region is good.
Step 8: as shown in Figure 7, remove part the first metal layer material, form the first electrode 112 and the second electrode 113 of this capacitor, the polarity of described first electrode 112 and the second electrode 113 is contrary, and electrical insulation therebetween, described first electrode 112 is positioned at both sides, described doped region or surrounding, and described second electrode 113 is positioned at described doped region on the surface, wherein, the part the first metal layer material of removal is located close on the partial etching barrier layer surface at edge, described doped region.
This process is specially, photoetching process is adopted to form insulation layer figure (not shown) on the surface at described the first metal layer 111, wet corrosion technique is adopted to remove not by part the first metal layer material that photoresist layer covers afterwards, obtain insulation layer 114, thus form the first electrode 112 and the second electrode 113, kept apart by insulation layer 114 between first electrode 112 and the second electrode 113, thus the electrical insulation both realizing.
The present embodiment photoetching process can adopt positive photoresist S9920 photoresist, because the first metal layer 111 is aluminium lamination, therefore can adopt H
3pO
4(solution concentration 85%), HNO
3(solution concentration 65%), CH
3cOOH (solution concentration 100%), H
2o and NH
4the mixed solution of F (solution concentration 40%), etches aluminium lamination at normal temperatures, and in this mixed solution, each solution to mix by volume according to said sequence at 76: 3: 15: 5: 0.01, and the wet etching time is about 10min-15min.
In addition, as Figure 8-Figure 10, after formation first electrode 112 and the second electrode 113, the method also comprises, and described first electrode and the second electrode surface are formed the second metal level 116, to draw described first electrode and the second electrode.
This process is specially:
As shown in Figure 8, mask plate used in Fig. 7 is utilized to carry out secondary photoetching, the photoresist layer 115 with the first electrode and the second electrode pattern is formed on the surface at etching barrier layer, namely this photoresist layer 115 only covers above-mentioned insulation layer 114, with a upper photoetching unlike, this time photoetching adopts negative photoresist, is preferably AZ5214 reversion glue in the present embodiment.Afterwards the silicon chip with photoresist layer 115 is put into annealing furnace and carry out annealing process, make to form good ohmic contact between the first electrode 112 and bulk layer mate-rial, between the second electrode 113 and doped region material, this time annealing temperature is about 400 DEG C, time is about 40min, can carry out in a nitrogen environment.
Afterwards, as shown in Figure 9, can adopt sputtering or evaporation process, the silicon chip surface with photoresist layer 115 is formed the second metal level 116, the material of this second metal level 116 is preferably gold, and thickness is preferably
As shown in Figure 10, the stripping technology that removes photoresist can be adopted, silicon chip is removed photoresist in solution as acetone soln or other and soaks, until photoresist layer 115 comes off, to remove second metal layer material in electrical insulation region, form metal electrode 117 and 118, the first electrode and the second electrode can be drawn, can ultrasonic cleaning be carried out afterwards, dry and wait incessantly, keep the clean and dry of silicon chip.
In Figure 10, the thickness of metal electrode 117 and 118 is only the half of aluminium lamination first electrode and the second thickness of electrode, in order to the position of clear signal metal electrode 117 and 118 in figure, is increased by the thickness of metal electrode 117 and 118.
It should be noted that, in the present embodiment, concrete restriction is not done to the particular location in the first region territory, the first region can be positioned at any side of the second electrode district (i.e. doped region), also its any both sides or any three sides can be positioned at, or be distributed in the surrounding of the second electrode district, be only be positioned at the both sides of the second electrode district or surrounding so that the distribution of the first region to be described for the first region in the present embodiment, but this point can not be used for the concretism limiting the embodiment of the present invention.
It will be appreciated by those skilled in the art that, the density of capacitor with three factors about: one is the thickness of dielectric layer, two is dielectric constants of medium, three is effective areas of dielectric layer, once determine the base material and doping condition etc. of capacitor, the thickness of dielectric layer and the dielectric constant of medium just secure, and therefore increasing the best controllable direction of capacitance density is exactly the effective area as far as possible increasing dielectric layer, is effective PN junction area in the present invention.
The embodiment of the present invention has broken away from the constraint of MIMIMI...M multilayer " sandwich " structure of conventional three-dimensional capacitor, overturn the structure of traditional capacitor plane formula, 3 D stereo groove is adopted to make two interelectrode dielectric layers of capacitor, namely the first electrode in the present embodiment and the second electrode are equivalent to two opposite polarity pole plates of capacitor, the PN junction that body layer and doped region contact area are formed is equivalent to the dielectric layer between capacitor two pole plates, because groove structure is 3-D solid structure, therefore the effective area of dielectric layer is far longer than the effective area of the dielectric layer of mim structure capacitor, thus substantially increase the capacitance density of capacitor.
Relative to the manufacture craft of traditional capacitor, first, the effect of the junction capacitance of the PN junction in the present embodiment is equivalent to the effect of dielectric layer, adopts the low and simply ripe doping process of cost to instead of the growth technique of conventional dielectric layer, overcomes dielectric layer and be difficult to growth and the problem of somewhat expensive; Secondly, two electrodes in the present embodiment adopt an evaporation or sputtering technology to be formed, and decrease procedure of processing, reduce production cost; Again, due to semiconductor PN have forward conduction oppositely by characteristic, and the breakdown characteristics that can recover in addition when reverse voltage is greater than certain value, can be applicable to the protection process to electrostatic, surge of electric power in circuit.
Further, the quantity of the groove of the capacitor in the present embodiment, depth-to-width ratio, distribution mode and distribution density can change accordingly according to the requirement of different capacitors, thus meet the requirement of different capacitors to capacitance density.And in theory, the capacitance density of the capacitor in the present embodiment can up to 10nF/mm
2-15nF/mm
2, the requirement of low frequency decoupling and high frequency decoupling can be met simultaneously.
Corresponding with said method embodiment, another embodiment of the present invention discloses the high density embedded capacitor adopting said method to make, and Figure 10 is the profile of this high density embedded capacitor, and Figure 11 is its vertical view, and this capacitor comprises:
Body layer 101, in described body layer 101 surface, there is multiple groove 105, bulk layer mate-rial between the bottom of described groove, sidewall and adjacent trenches has the doped region 107 of certain doping content and doping thickness, described body layer 101 is three-dimensional PN junction region with described doped region 107 contact area;
Be positioned at the first electrode 112 on the body layer surface of described both sides, doped region 107 or surrounding, be positioned at described doped region on the surface and cover the second electrode 113 of the bulk layer mate-rial between the bottom of described groove, sidewall and adjacent trenches, the polarity of described first electrode 112 and the second electrode 113 is contrary, and electrical insulation therebetween, described first electrode and the second electrode are all formed in the first metal layer surface, and the two is formed in same photoetching and etch step;
Be close to the etching barrier layer 102 on the body layer surface at edge, described doped region, described etching barrier layer 102 by described first electrode 112 and the second electrode isolation 113, to make electrical insulation between described first electrode and the second electrode.
In addition, also comprise the metal electrode 117 and 118 be positioned on described first electrode 112 and the second electrode 113 surface, draw the first electrode 112 and the second electrode 113 respectively, metal electrode 113 need are distributed in the top (i.e. the join domain of adjacent trenches) of the second electrode 113, play the effect of extraction electrode.
As shown in figure 11, only both sides, doped region are distributed in for the first electrode 112 in the present embodiment, if described bulk layer mate-rial adopts P type low-resistance silicon substrate, described doped region is N-type doping, the first electrode 112 in Figure 11 is the P type top electrode (positive electrode) of capacitor, second electrode 113 of zone line is the N-type bottom electrode (negative electrode) of capacitor, the second electrode region has the groove that the surface coverage distributed in array has metallic aluminium, and trench cross-section shape is preferably regular hexagon, circle or square.
The resistivity of aforementioned p-type silicon substrate is preferably between 0.01 Ω cm-0.5 Ω cm, and the thickness of described doped region is selected between 0.1 μm-3 μm, and be preferably between 0.5 μm-1.5 μm, the thickness of doped region is more preferably 1 μm.
Show through theory analysis and experimental result, the capacitor that the present invention makes not only has larger capacitance density, and its capacitance density is at 10nF/mm
2-15nF/mm
2within, and still can keep good characteristic in high frequency, the requirement of low frequency decoupling and high frequency decoupling can be met simultaneously.
Capacitor in the present embodiment adopts silicon-based substrate, due to silicon based system encapsulation technology have with conventional microelectronic process compatible, reliability is high and be easy to integrated, the capacitor that the embodiment of the present invention provides can be applicable to the various application scenarios of embedded capacitor.
The above embodiment is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (13)
1. a high density embedded capacitor manufacture method, is characterized in that, comprising:
There is provided substrate, described substrate comprises body layer and is positioned at the etching barrier layer on described body layer surface;
Multiple groove figure is formed in described etching barrier layer surface;
To have the etching barrier layer of described groove figure for mask, in described body layer surface, form multiple groove, described groove vertical degree is good and have high-aspect-ratio;
Remove the etching barrier layer materials between adjacent trenches, to form the doped region figure of this capacitor on the surface at described etching barrier layer;
There is the etching barrier layer of described doped region figure for mask, bulk layer mate-rial between the bottom of described groove, sidewall and adjacent trenches is adulterated, obtain the doped region of this capacitor, to form three-dimensional PN junction in described body layer and described doped region contact area;
Retain the partial etching barrier material at next-door neighbour edge, described doped region, remove the partial etching barrier material of both sides, described doped region or surrounding, expose part body layer material, as the first region of this capacitor;
The first metal layer is formed on the surface in described body layer, described the first metal layer and described doped region material and all form ohmic contact between described the first metal layer and described bulk layer mate-rial, described the first metal layer covers the doped region material between the bottom of described the first region and described groove, sidewall and adjacent trenches;
Remove part the first metal layer material, form the first electrode and second electrode of this capacitor, the polarity of described first electrode and the second electrode is contrary, and electrical insulation therebetween, described first electrode is positioned at both sides or the surrounding of described doped region, described second electrode is positioned at described doped region on the surface, and wherein, the part the first metal layer material of removal is located close on the partial etching barrier layer surface at edge, described doped region;
Also comprise after forming the first electrode and the second electrode, described first electrode and the second electrode surface form the second metal level, to draw described first electrode and the second electrode; Wherein, adopt sputtering or evaporation process, the silicon chip surface with photoresist layer is formed the second metal level, then the stripping technology that removes photoresist is adopted, silicon chip is placed in acetone soln or other solution that removes photoresist soaks, until photoresist layer comes off, to remove second metal layer material in electrical insulation region, form metal electrode, the first electrode and the second electrode can be drawn.
2. high density embedded capacitor manufacture method according to claim 1, it is characterized in that, the depth-to-width ratio of described groove is between 1:1-10:1.
3. high density embedded capacitor manufacture method according to claim 2, is characterized in that, the degree of depth of described groove is between 2 μm-100 μm.
4. high density embedded capacitor manufacture method according to claim 2, is characterized in that, the thickness of the bulk layer mate-rial between described adjacent trenches is greater than 2 times of the thickness of described doped region, and is less than 20 μm.
5. high density embedded capacitor manufacture method according to claim 4, is characterized in that, the thickness of described doped region is between 0.1 μm-3 μm.
6. high density embedded capacitor manufacture method according to claim 5, it is characterized in that, the method forming described doped region is, high-temperature diffusion process is adopted to form described doped region, this process is specially, under high temperature within 1000 DEG C-1200 DEG C, carry out the prediffusion of 1min-10min, with make the concentration stabilize of diffuse source remain on preset concentration under, keep described high temperature and preset concentration afterwards, spread continuously, comprise the overall time of the described High temperature diffusion of described prediffusion time within 10min-90min.
7. high density embedded capacitor manufacture method according to claim 6, is characterized in that, described bulk layer mate-rial is P-type silicon substrate, and described doped region is N-type doping, and the diffuse source of described doped region is POCl3, and described preset concentration is 8 × 10
20cm
-3, the overall time of described High temperature diffusion is 80min.
8. high density embedded capacitor manufacture method according to claim 7, is characterized in that, the resistivity of described P-type silicon substrate is between 0.01 Ω cm-0.5 Ω cm.
9. high density embedded capacitor manufacture method according to claim 1, is characterized in that, described multiple groove is that array is distributed in described body layer surface.
10. high density embedded capacitor manufacture method according to claim 9, is characterized in that, the shape of cross section of described groove is regular hexagon, circle or square.
11. high density embedded capacitor manufacture methods according to claim 1, it is characterized in that, described the first metal layer material is aluminium, and described second metal layer material is gold.
The 12. high density embedded capacitors adopting the method described in any one of claim 1-11 to make, is characterized in that, comprising:
Body layer, in described body layer surface, there is multiple groove, bulk layer mate-rial between the bottom of described groove, sidewall and adjacent trenches has the doped region of certain doping content and doping thickness, described body layer and described doped region contact area are three-dimensional PN junction region;
Be positioned at the first electrode on the body layer surface of both sides, described doped region or surrounding, be positioned at described doped region on the surface and cover the second electrode of the bulk layer mate-rial between the bottom of described groove, sidewall and adjacent trenches, the polarity of described first electrode and the second electrode is contrary, and electrical insulation therebetween, described first electrode and the second electrode are all formed in the first metal layer surface, and the two is formed in same photoetching and etch step;
Be close to the etching barrier layer on the body layer surface at edge, described doped region, described etching barrier layer by described first electrode and the second electrode isolation, to make electrical insulation between described first electrode and the second electrode;
Be positioned at the second metal level on described first electrode and the second electrode surface, described second metal level draws described first electrode and the second electrode.
13. high density embedded capacitors according to claim 12, it is characterized in that, described bulk layer mate-rial is P-type silicon substrate, and described doped region is N-type doping, the resistivity of described P-type silicon substrate is at 0.01 Ω cm-0.5 Ω cm, and the thickness of described doped region is between 0.1 μm-3 μm.
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| CN103474429A (en) * | 2013-09-18 | 2013-12-25 | 华进半导体封装先导技术研发中心有限公司 | Capacitor array |
| CN104007147B (en) * | 2014-06-06 | 2016-07-13 | 华进半导体封装先导技术研发中心有限公司 | The detecting device of bottom electrode surface and detection method in high aspect ratio microstructures |
| CN105845773B (en) * | 2016-03-30 | 2017-08-25 | 江苏欧达丰新能源科技发展有限公司 | Solar battery sheet three-dimensional PN junction processing technology |
| DE102017223853A1 (en) * | 2017-12-28 | 2019-07-04 | Kautex Textron Gmbh & Co. Kg | A method of determining a quality property of an operating fluid in an operating fluid reservoir for a motor vehicle and operating fluid reservoir for carrying out the method |
| CN108878543A (en) * | 2018-06-29 | 2018-11-23 | 上海华虹宏力半导体制造有限公司 | capacitor and its manufacturing method |
| CN116489989A (en) * | 2022-01-13 | 2023-07-25 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
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