CN101800165B - Production method for channel capacitor - Google Patents
Production method for channel capacitor Download PDFInfo
- Publication number
- CN101800165B CN101800165B CN2009100776702A CN200910077670A CN101800165B CN 101800165 B CN101800165 B CN 101800165B CN 2009100776702 A CN2009100776702 A CN 2009100776702A CN 200910077670 A CN200910077670 A CN 200910077670A CN 101800165 B CN101800165 B CN 101800165B
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- capacitance
- electrode
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 230000000717 retained effect Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 238000001704 evaporation Methods 0.000 claims description 14
- 230000008020 evaporation Effects 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000000615 nonconductor Substances 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 238000000137 annealing Methods 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 2
- 238000012545 processing Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 8
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000011241 protective layer Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 11
- 238000000059 patterning Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000009616 inductively coupled plasma Methods 0.000 description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a production method for a channel capacitor, comprising the steps of providing a high-doped low-resistant semiconductor substrate using Si as a substrate, on which a layer of SiO2 grows as a mask layer, a physical protective layer and an electrical insulating layer; etching SiO2 on the Si layer and opening capacitance windows with different areas; preparing the substrate with a channel and a P type electrode region through etching; directly using SiO2 retained in the Si substrate as the mask to form a high-doped n+ layer on the surface of the Si substrate channel and a PN joint junction capacitance at the joint depth; depositing metal on the surface of the capacitance in large area; forming metal electrodes in an opened window layer, N type electrode and P type layer electrode regions; and annealing the prepared channel capacitance at high temperature to form good ohmic contact on the P, N electrodes. The invention overcomes the problem that the medium layer is difficult to grow and the cost is expensive and the like, thereby decreasing processing steps and reducing cost.
Description
Technical field
The present invention relates to field of microelectronic devices, particularly a kind of manufacture method of trench capacitor of based semiconductor PN junction.
Background technology
Along with people to the requirement of electronic product to miniaturization, multi-functional, the development of directions such as environment-friendly type, people make great efforts to seek to do electronic system more little, integrated level is more and more higher, function is done more and more, and is more and more stronger.Many new technologies have been produced thus, new material, new design.For example system level chip (System-on-Chip, SOC), and with the closely-related system in package of the present invention technology such as (System-in-Package SiP, System-on-Package SoP) be exactly the typical case representative of these technology.And electric capacity is integrated, and promptly imbedding electric capacity then is one of key technology that realizes SOP.This has the advantage of highly significant owing to imbedding electric capacity compared to patch capacitor, and promptly imbedding electric capacity has littler stray inductance and resistance, this means that it can be applied to the high-frequency high-speed electronic system.
Decoupling capacitor is widely used in the various electronic systems, it generally is connected between the power supply and ground in the supply network in the electronic system, utilize the electric capacity frequency more little principle of high impedance more, the high-frequency noise in the electric power network is reduced, thereby the noise in the electric power network is played inhibitory action.In the practical application, because intrinsic stray inductance and the resistance of capacitor, any capacitor all can not be accomplished the full frequency band decoupling from the low frequency to the high frequency.In general, capacitor appearance value is big more, and is just good more to low frequency decoupling effect, but volume is just big more, and stray inductance and resistance are also big more, just poor more to the decoupling effect of high frequency; Capacitor appearance value is more little, and volume is just more little, and stray inductance and resistance are just more little, therefore can be used for high frequency, but because the appearance value is little, low frequency decoupling weak effect.So generally be that capacitor with a plurality of different appearance values is together in parallel, Da Rong value capacitor is to the low frequency component decoupling, the low-capacitance capacitor is to the high fdrequency component decoupling.This solution is feasible to the electronic system space without limits the time, but just infeasible when there is strict restriction in the electronic system space.Obviously, optimal situation is that a capacitor has big appearance value and little stray inductance and resistance.Because stray inductance and resistance are directly proportional with volume, volume is big more, and stray inductance and resistance are just big more.So another saying is that optimal decoupling capacitor is to have minimum volume and maximum appearance value.The decoupling capacitor that is used for intermediate frequency decoupling (500MHz is between several GHz) now is generally multi-layer ceramics surface mount capacitor (MLCC), is of a size of 0201 (0.6 * 0.3 * 0.3 millimeter) or 0402 (1.0 * 0.5 * 0.5 millimeter).It is to be superimposed together by the ceramic dielectric diaphragm of printed electrode (interior electrode) mode with dislocation, form ceramic chip through disposable high temperature sintering, seal up metal level (external electrode) again at the two ends of chip, thereby form the structure of a similar only stone, so also be monolithic capacitor.This patch capacitor device still needs to be connected with circuit by lead-in wire, has increased parasitic parameter to Effect on Performance.At present, in the SOP field, have increasing invention and research to relate to and imbed electric capacity, various countries scholar and associated mechanisms have also dropped into lot of manpower and material resources in this regard.Up to now, the common application of imbedding electric capacity has following several form: lamination type multi-chip module (MCM-L), ceramic-type multi-chip module (MCM-C), sedimentation type multi-chip module (MCM-D).Based on metal-insulator-metal (MIM) structure, its representative value of the capacitance density of imbedding electric capacity on especially silica-based is 0.7～0.9nF/mm but up to now,
2This capacitance density is that the ideal that low value is used is selected, for example radio frequency middle impedance coupling.But, the appearance of be difficult to satisfy the requirement of 1～100nF capacitance because little this limitation of its capacitance density is difficult to such as the problems such as decoupling under the radio frequency. channel-type electric capacity is exactly in order to increase effective capacitance area; As the flat medium people of Shanghai Hong Li Semiconductor Manufacturing Co., Ltd gold in " channel-type metal-insulating layer-metal capacitor structure and its formation method " (patent No.: CN 1700408), used the raceway groove method increase effective area utilization with than capacitance, the people such as Taiwan Maode Science Co., Ltd Li Yue river " the formation channel capacitance is in method and the channel capacitance of substrate " (patent No.: CN 1862764A) and Huabang Electronics Co., Ltd execute this one-tenth " semiconductor device and the manufacture method thereof that comprise channel-type electric capacity " (patent No.: 1447437) also the manufacture craft to mim structure formula channel capacitance detailed description is also arranged. People such as the Leonard of Arkansas university even electric capacity has been prepared into the MIMIMI...M structure as shown in Figure 1 increase the density of electric capacity with this.General silica-based channel-type electric capacity has still adopted mim structure, and promptly the polysilicon with the n+ type is a bottom crown, as dielectric layer, utilizes metal such as method of evaporating deposit Ti/Al as the electric capacity top crown by materials such as methods such as low pressure chemical gas phase substrate deposition SiNx again.This kind method complex procedures needs repeatedly photoetching, LPCVD growing polycrystalline silicon and dielectric layer, and in report not to the description of high frequency performance.
The present invention utilizes the notion of semiconductor PN electric capacity, avoid traditional mim structure, the same channel capacitance that adopts can increase effective capacitance area, when guaranteeing big capacitance density, reduce required operation and strengthen its high frequency performance, design and made under 2.5GHz capacitance density greater than 2nF/mm
2Channel capacitance.And reverse voltage does not change with breakdown current within the specific limits when having reverse breakdown owing to PN junction, and another important difference of capacitor of the present invention and other capacitors is to reduce or to prevent the influence to Circuits System such as static, surge.
Summary of the invention
(1) technical problem that will solve
Main purpose of the present invention is to provide a kind of manufacture method of trench capacitor of based semiconductor PN junction, by silicon substrate being carried out dry etching increasing the effective area of electric capacity, increases capacitance in the unit two-dimensional areas with this.
In addition, the invention provides a kind of non-traditional MIM " sandwich " typical capacitor structure, directly utilize the manufacture craft of the PN junction channel-type decoupling capacitance that semiconductor P district, N district form by depletion layer at the interface.Because semiconductor PN junction capacitance some special natures under high frequency, and the forward conduction that semiconductor had, oppositely by and under certain voltage special electrology characteristic such as reverse breakdown, can realize functions such as decoupling, antistatic, surge simultaneously.
(2) technical scheme
For achieving the above object, the invention provides a kind of manufacture method of trench capacitor, this method comprises:
Providing with Si is the highly doped low resistance semiconductor substrate of substrate, growth one dielectric layer such as SiO on substrate
2As mask layer, physical protection layer and electrical insulator layer;
Adopt the photoresist mask and according to needed capacitance etching SiO
2To the Si layer, leave the electric capacity window of different area;
In this window, utilize photoresist, prepare substrate and P type layer electrode district by etching with raceway groove as mask;
Directly utilize the SiO that is retained on the Si substrate
2As mask, form the highly doped n of one deck in the silicon substrate channel surface
+Layer forms the PN junction junction capacitance at its junction depth place;
Utilize evaporation or sputter at capacitive surface large tracts of land evaporation metal,, use wet etching, form metal electrode at the Window layer of leaving, N type electrode and P type layer electrode zone with photoresist as mask;
The channel capacitance for preparing is at high temperature annealed, make on two electrodes of its P, N and all form good Ohmic contact.
In the such scheme, described is the highly doped low resistance semiconductor substrate of substrate with Si, and its resistivity is 0.01～0.3 Ω cm.
In the such scheme, the described SiO that on substrate, grows
2Layer adopts PECVD or thermal oxidation process, SiO
2The thickness of layer is 7000～8000 dusts.
In the such scheme, described etching dielectric layer SiO
2Adopt dry method ICP etching.
In the such scheme, described in window etching prepare substrate and P type layer electrode adopts dry method ICP etch silicon substrate with raceway groove, make it to form substrate and P type layer electrode with channel shape.
In the such scheme, described at the highly doped n of silicon substrate channel surface formation one deck
+Layer is to form by the method that spreads.
In the such scheme, described formation n
+The impurity source of diffusion is POCl during layer
3
In the such scheme, two electrodes of the PN junction junction capacitance of described formation all are positioned at the silicon chip homonymy.
In the such scheme, described on the Window layer of leaving, N type electrode and P type layer electrode the metal of evaporation be Al.
(3) beneficial effect
From technique scheme as can be seen, the present invention has compared several advantages with the manufacture craft and the capacitance characteristic of common channel-type electric capacity.At first, the present invention has broken away from the constraint of traditional MIM " sandwich " structure capacitive, directly utilizes the junction capacitance of PN junction, has overcome dielectric layer and has been difficult to growth, problems such as expense costliness.With relatively cheap, the doped and substituted of technical maturity.Secondly, electrode evaporation in the two poles of the earth is finished, and has reduced procedure of processing, has reduced cost.The 3rd and since forward conduction that semiconductor PN has oppositely by characteristic, and at the breakdown characteristics that reverse voltage can recover during greater than certain value in addition, can be applicable in the circuit protection to static, surge phenomenon.The 4th, theory analysis and measured result show that the capacitor that the present invention makes not only has bigger capacitance density, and still can keep characteristic preferably under high frequency.
Description of drawings
Fig. 1 is the basic structure profile that illustrates silica-based common multilayer mim structure electric capacity, wherein:
101-is the substrate of matrix with silicon;
102-silica dioxide medium layer;
The electrode of 103-MIM structure capacitive;
The dielectric layer of 104-MIM structure capacitive;
The 105-holding wire;
The dielectric layer that 106-shields;
Fig. 2 is the method flow diagram of making trench capacitor provided by the invention;
Fig. 3 a to Fig. 3 i is section of structure, is the manufacturing process according to the PN junction channel-type electric capacity with channel shape of a kind of specific embodiment according to the present invention drafting.Wherein:
301-P type low-resistance silicon substrate;
The 302-dielectric layer;
303-photoresist material;
The n that 304-forms by diffusing, doping
+The district;
The 305-Al electrode layer.
Fig. 4 is the vertical view of the prepared pn knot channel-type junction capacitance of the present invention.Wherein:
The P type electrode of electric capacity among 401-the present invention;
The N type electrode of electric capacity among 402-the present invention;
Pass through the formed raceway groove of method of dry etching among 403-the present invention;
404-P type provided by the present invention low-resistance silicon substrate.
Fig. 5 is the measured result that concerns of the reactance absolute value of a typical capacitor and frequency, and its area is 0.04mm
2
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The manufacture craft of channel-type PN junction junction capacitance provided by the invention comprises the following steps: to provide one to have low highly doped rate, the P type silicon chip of low-resistivity at least; On silicon chip, form the dielectric layer that one deck plays mask, isolation and electrical insulation effect; According to the size of required capacitance and electrode, form the mask graph of a patterning by photoresist; Use dry etching SiO
2To the Sj substrate; Form the second layer mask graph of a patterning; Use this figure of dry etching to make the Si substrate form required " raceway groove " shape; Form n by being entrained in P type Si surface
+The district; Utilize means such as evaporation or sputter at capacitive surface large tracts of land evaporation metal Al; As mask, use wet etching to form metal electrode with photoresist at the Window layer of leaving, N type electrode and P type layer electrode zone; Annealing improves ohmic contact.
As shown in Figure 2, Fig. 2 is the method flow diagram of making trench capacitor provided by the invention, and this method comprises:
Step 201: providing with Si is the highly doped low resistance semiconductor substrate of substrate, growth one deck SiO on substrate
2As mask layer, physical protection layer and electrical insulator layer;
Step 202: adopt the photoresist mask and according to needed capacitance etching SiO
2To the Si layer, leave the electric capacity window of different area;
Step 203: in this window, utilize photoresist, prepare substrate and P type layer electrode district by etching with raceway groove as mask;
Step 204: directly utilize the SiO that is retained on the Si substrate
2As mask, form the highly doped n of one deck in the silicon substrate channel surface
+Layer forms the PN junction junction capacitance at its junction depth place;
Step 205: utilize evaporation or sputter at capacitive surface large tracts of land evaporation metal,, use wet etching, form metal electrode at the Window layer of leaving, N type electrode and P type layer electrode zone with photoresist as mask;
Step 206: the channel capacitance for preparing is at high temperature annealed, make on two electrodes of its P, N and all form good Ohmic contact.
The trench type capacitor that with the electrode is one side together below is an example, and the concrete implementation step of the present invention is as follows:
Fig. 3 a to Fig. 3 i is the flow process profile of the PN channel-type junction capacitance with channel shape of making according to the present invention.
Step 3, shown in Fig. 3 c, utilize the photoresist layer 303 of patterning to be used as the required mask material of etching, dielectric layer 302 is carried out anisotropic etching, the equipment of etching can be selected for example reactive plasma etching (PIE), inductively coupled plasma etching (ICP), and its plasma gas can be selected CF
3The figure 303 of photoresist layer is transferred on the dielectric layer 302.Select suitable solution or dry etching program to remove photoresist layer again.
Step 4, shown in Fig. 3 d, the photoresist layer that utilizes patterning once more forms required raceway groove photoresist pattern 303 as mask material, and wherein P type electrode 306 places protect with photoresist.Wherein photoresist is counter-rotating glue, for example AZ5214.Because channel depth is greater than 20 microns, for satisfying the etching requirement, photoresist need keep certain thickness, and the coating thickness of photoresist should be greater than 3 microns in this step.
Step 5 shown in Fig. 3 e, utilizes the photoresist layer 303 of patterning to be used as the required mask material of etching, and silicon substrate is carried out anisotropic etching, and as ICP, its plasma gas can be selected SF
6, C
2H
4Mist, with the figure transfer of photoresist layer to silicon substrate 301.Select suitable solution or dry etching program to remove photoresist layer again.
Step 6 shown in Fig. 3 f, directly utilizes remaining dielectric layer 302 as mask graph, and silicon substrate is mixed.The mode of mixing has ion to inject and spread two major types, owing to need carry out the doping in N type district at sidewall, considers that ion is injected with very strong directivity, therefore adopts method of diffusion to carry out the N type in this example and mixes.Diffuse source is POCl
3, under the temperature of 1000 degree Celsius, carry out prediffusion, under this temperature, carry out 30 minutes heat treatment again, make forming PN junction 304 from the about 1 micron depths of silicon face.
Step 7, shown in Fig. 3 g, at device top layer large tracts of land evaporation metal, its equipment can be selected methods such as electron beam evaporation, magnetron sputtering.Owing to use the metal adhesive ability of magnetically controlled sputter method evaporation stronger, adopted magnetically controlled sputter method in this experiment.In addition, metal electrode can be selected materials such as Ti-Au, Al for use, because the Al material is easy to the P type, N type silicon forms the lower ohmic contact of resistivity simultaneously, selects the electrode material of Al 305 as P type, N type district in this example for use.
Step 8 shown in Fig. 3 h, utilizes the photoresist layer 303 of patterning to make mask material once more, to protecting as the Al material of electrode part.In this process, formed the figure of N region electrode.If electrode at the matrix heteropleural, then carries out the making of electrode to the matrix bottom surface when this step.
Step 9 shown in Fig. 3 i, uses corrosion of metals liquid to corrode being exposed to photoresist protection metal in addition, forms P, the two poles of the earth, N district to duplicate the photoresist figure.Use Al as electrode in this example, therefore select for use the Al corrosive liquid to corrode.The Al corrosive liquid is generally by H
3PO
4(mass percent 85%): HNO
3(mass percent 65%): CH
3COOH (mass percent 100%): H
2O: NH
4F (mass percent 40%) was by 76: 3: 15: 5: 0.01 proportioning (volume ratio) form.Selecting suitable solution or dry etching program removal photoresist layer.
Step 10 places this device and carries out in the annealing furnace 350～450 degree annealing Celsius, 30 minutes time.In order to form good Ohmic contact.The vertical view of resulting devices as shown in Figure 4.
Fig. 5 utilizes the PN junction channel-type junction capacitance of method for preparing to utilize vector network analyzer to test the result of its high frequency characteristics.As we know from the figure, this electric capacity still can keep capacitance characteristic preferably more than 2G.The two-dimensional areas of electric capacity is 0.04mm
2, capacitance is 88pF, its capacitance density is 2200pF/mm
2
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. the manufacture method of a trench capacitor is characterized in that, this method comprises:
Providing with Si is the highly doped low resistance semiconductor substrate of substrate, growth one deck SiO on substrate
2As mask layer, physical protection layer and electrical insulator layer;
Adopt the photoresist mask and according to needed capacitance etching SiO
2To the Si layer, leave the electric capacity window of different area;
In this window, utilize photoresist, prepare substrate and P type layer electrode district by etching with raceway groove as mask;
Directly utilize the SiO that is retained on the Si substrate
2As mask, form the highly doped n of one deck in the silicon substrate channel surface
+Layer forms the PN junction junction capacitance at its junction depth place;
Utilize evaporation or sputter at capacitive surface large tracts of land evaporation metal,, use wet etching, form metal electrode at the Window layer of leaving, N type electrode and P type layer electrode zone with photoresist as mask;
The channel capacitance for preparing is at high temperature annealed, make on two electrodes of its P, N and all form good Ohmic contact.
2. the manufacture method of trench capacitor as claimed in claim 1 is characterized in that, described is the highly doped low resistance semiconductor substrate of substrate with Si, and its resistivity is 0.01～0.3 Ω cm.
3. the manufacture method of trench capacitor as claimed in claim 1 is characterized in that, the described SiO that grows on substrate
2Adopt PECVD or thermal oxidation process, SiO
2The thickness of layer is 7000～8000 dusts.
4. the manufacture method of trench capacitor as claimed in claim 1 is characterized in that, described etching SiO
2Adopt dry method ICP etching.
5. the manufacture method of trench capacitor as claimed in claim 1, it is characterized in that, described in window etching prepare substrate and P type layer electrode adopts dry method ICP etch silicon substrate with raceway groove, make it to form substrate and P type layer electrode with channel shape.
6. the manufacture method of trench capacitor as claimed in claim 1 is characterized in that, and is described at the highly doped n of silicon substrate channel surface formation one deck
+Layer is to form by the method that spreads.
7. the manufacture method of trench capacitor as claimed in claim 6 is characterized in that, described formation n
+The impurity source of diffusion is POCl during layer
3
8. the manufacture method of trench capacitor as claimed in claim 1 is characterized in that, two electrodes of the PN junction junction capacitance of described formation all are positioned at the silicon chip homonymy.
9. the manufacture method of trench capacitor as claimed in claim 1 is characterized in that, described on the Window layer of leaving, N type electrode and P type layer electrode the metal of evaporation be Al.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100776702A CN101800165B (en) | 2009-02-11 | 2009-02-11 | Production method for channel capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100776702A CN101800165B (en) | 2009-02-11 | 2009-02-11 | Production method for channel capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101800165A CN101800165A (en) | 2010-08-11 |
| CN101800165B true CN101800165B (en) | 2011-05-11 |
Family
ID=42595783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100776702A Active CN101800165B (en) | 2009-02-11 | 2009-02-11 | Production method for channel capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101800165B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094068B (en) * | 2011-10-31 | 2015-11-18 | 成都锐华光电技术有限责任公司 | High density embedded capacitor and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5330926A (en) * | 1990-11-14 | 1994-07-19 | Nec Corporation | Method of fabricating semiconductor device having a trenched cell capacitor |
| CN1404126A (en) * | 2001-08-22 | 2003-03-19 | 矽统科技股份有限公司 | Embedding process of making metal capacitor and its product |
| CN1536647A (en) * | 2003-04-08 | 2004-10-13 | 南亚科技股份有限公司 | Method for increasing capacitance of channel capacitor |
-
2009
- 2009-02-11 CN CN2009100776702A patent/CN101800165B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5330926A (en) * | 1990-11-14 | 1994-07-19 | Nec Corporation | Method of fabricating semiconductor device having a trenched cell capacitor |
| CN1404126A (en) * | 2001-08-22 | 2003-03-19 | 矽统科技股份有限公司 | Embedding process of making metal capacitor and its product |
| CN1536647A (en) * | 2003-04-08 | 2004-10-13 | 南亚科技股份有限公司 | Method for increasing capacitance of channel capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101800165A (en) | 2010-08-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI673760B (en) | Laminated semiconductor wafer and method for manufacturing bonded semiconductor wafer | |
| US9818688B2 (en) | Dielectric region in a bulk silicon substrate providing a high-Q passive resonator | |
| JP2007258713A (en) | Integration passive device substrate | |
| CN103094068B (en) | High density embedded capacitor and preparation method thereof | |
| CN105867037A (en) | Array substrate, preparation method of array substrate and liquid crystal display panel | |
| EP1743372A1 (en) | Semiconductor device and method of manufacturing such a device | |
| CN108336152A (en) | Groove-shaped silicon carbide SBD device with floating junction and its manufacturing method | |
| CN100533967C (en) | Electronic device | |
| CN101800165B (en) | Production method for channel capacitor | |
| US6486017B1 (en) | Method of reducing substrate coupling for chip inductors by creation of dielectric islands by selective EPI deposition | |
| CN100514641C (en) | Structure and manufacture of network thin-film IC with transverse venting diode | |
| CN101814531B (en) | Capacitor composed by utilizing semiconductor PN junction capacitance and manufacturing method thereof | |
| KR101041752B1 (en) | Semiconductor filter of multi-stage structure and fabrication method thereof | |
| US11978808B2 (en) | Vertical etch heterolithic integrated circuit devices | |
| CN105261586A (en) | Preparation method for substrate with charge traps and insulation buried layer | |
| CN111834344B (en) | Low-electromagnetic-loss silicon-based gallium nitride microwave millimeter wave transmission line and preparation method thereof | |
| CN106469716B (en) | A kind of vertical-type capacitor arrangement | |
| CN104112708A (en) | Method for manufacturing integrated filter with ESD protection and EMI prevention | |
| CN102024788B (en) | Semiconductor device for interconnection process and manufacturing method thereof | |
| KR100970923B1 (en) | Semiconductor filter device and fabrication method thereof | |
| CN105140107A (en) | Preparation method for substrate with charge trap and insulation buried layer | |
| CN106952895B (en) | A kind of manufacturing method of MIM capacitor structure | |
| CN104517803A (en) | Decoupling capacitor structure in integrated passive device (IPD) and manufacturing method of decoupling capacitor structure | |
| CN110010588B (en) | Complementary three-dimensional broadband capacitor based on coaxial through-silicon-via array | |
| US9379202B2 (en) | Decoupling capacitors for interposers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: CHENGDU RHOPTICS OPTOELECTRONIC TECHNOLOGY CO., LT Free format text: FORMER OWNER: INST OF MICROELECTRONICS, C. A. S Effective date: 20140730 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 100029 CHAOYANG, BEIJING TO: 610041 CHENGDU, SICHUAN PROVINCE |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20140730 Address after: 610041, Sichuan, Chengdu hi tech Development Zone, 188 Rui Rui Road, No. 6, No. 2 building Patentee after: CHENGDU RUIHUA OPTOELECTRONIC TECHNOLOGY Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20210220 Address after: 214028 building D1, China Sensor Network International Innovation Park, No. 200, Linghu Avenue, New District, Wuxi City, Jiangsu Province Patentee after: National Center for Advanced Packaging Co.,Ltd. Address before: 2 / F, no.188-6, Zirui Avenue, Chengdu hi tech Development Zone, Sichuan 610041 Patentee before: CHENGDU RUIHUA OPTOELECTRONIC TECHNOLOGY Co.,Ltd. |
|
| TR01 | Transfer of patent right |