CN103077901B - The method for packing of semiconductor package part and apply its semiconductor package part formed - Google Patents
The method for packing of semiconductor package part and apply its semiconductor package part formed Download PDFInfo
- Publication number
- CN103077901B CN103077901B CN201310047921.9A CN201310047921A CN103077901B CN 103077901 B CN103077901 B CN 103077901B CN 201310047921 A CN201310047921 A CN 201310047921A CN 103077901 B CN103077901 B CN 103077901B
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- Prior art keywords
- chip
- substrate
- groove
- semiconductor package
- package part
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Abstract
A kind of method for packing of semiconductor package part and apply its semiconductor package part formed.Semiconductor package part comprises substrate, chip and packaging body.Chip has one in the face of a first surface and of substrate is away from a second surface of substrate.Packaging body coats chip and there is a groove and a upper surface, the upper surface of packaging body higher than or be aligned in the second surface of chip, its further groove is connected and the second surface of exposed chip with the upper surface of packaging body, and the bottom surface of groove is lower than the second surface of chip.
Description
Technical field
The invention relates to a kind of method for packing of semiconductor package part and apply its semiconductor package part formed, and relate to especially a kind of improve the semiconductor package part of heat dissipation problem method for packing and apply its semiconductor package part formed.
Background technology
Traditional semiconductor package part comprises chip and packaging body.In order to protect IC, the side of the usual coating chip of packaging body and upper surface.But, the heat of complete so coated not easily dissipation chip on the contrary.
In addition, if though the upper surface of chip and lateral margin are exposed in the external world completely have the risk that preferably radiating effect easily causes the external force collision of chip chance and damage.
Summary of the invention
The present invention has about a kind of semiconductor package part, in an embodiment, can improve the not good problem of known chip cooling and the risk that chip can be reduced to suffer extraneous collision and damage.
According to the present invention, a kind of method for packing of semiconductor package part is proposed.The method for packing of semiconductor package part comprises the following steps.There is provided a patrix and a counterdie, patrix comprises one can deformation element; Arrange a substrate and a chip in counterdie, its chips to be located on substrate and to be positioned at can have a upper surface immediately below deformation element; Matched moulds counterdie and patrix and form a die cavity, making can deformation element extruding chip and form a ring-type teat, and a bottom surface of ring-type teat is lower than the upper surface of chip, and counterdie and patrix are after matched moulds, and an end face of die cavity aligns or higher than the upper surface of chip; And, fill in the die cavity of an encapsulating material between patrix and counterdie, wherein encapsulating material coating chip and cover the end face of die cavity.
According to the present invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a substrate, a chip and a packaging body.Chip has one in the face of a first surface and of substrate is away from a second surface of substrate.Packaging body coats chip and there is a groove and a upper surface, the upper surface of packaging body higher than or be aligned in the second surface of chip, its further groove is connected and the second surface of exposed chip with the upper surface of packaging body, and the bottom surface of groove is lower than the second surface of chip.
For foregoing of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing, be described in detail below:
Accompanying drawing explanation
Figure 1A illustrates the outside drawing of the semiconductor package part according to one embodiment of the invention.
Figure 1B illustrates the cutaway view along direction 1B-1B ' in Figure 1A.
Fig. 2 illustrates the schematic diagram of the measuring semiconductor packaging part of Figure 1B.
Fig. 3 A to 3C illustrates the process drawing of the semiconductor package part of Figure 1B.
Main element symbol description:
100: semiconductor package part
110: substrate
110u, 130u: upper surface
120: chip
120b: first surface
120u: second surface
120s: side
121,140: electrical contact
130: packaging body
130 ': encapsulating material
130b, 221b, 2131b: bottom surface
130r: groove
130r1: the first sub-groove
130r2: the second sub-groove
130s: medial surface
150: pressing plate
160: test fingers
210: patrix
211: upper die body
212: middle plate
212r, 221r: recess
213: can deformation element
213s1: outside
213s2: inner side
2131: annular protrusion
220: counterdie
221: lower mold body
222: loading plate
230r: die cavity
230u, 212u: end face
2131: ring-type teat
D1, D2: internal diameter
H1, H2, H3, H4, H5: distance
P: compressed thickness
S: mould fluid space
T1, T2: thickness
Embodiment
Please refer to Figure 1A, it illustrates the outside drawing of the semiconductor package part according to one embodiment of the invention.Semiconductor package part 100 comprises substrate 110, chip 120, packaging body 130 and at least one electrical contact 140.
Substrate 110 can be organic (organic) substrate, pottery (ceramic) substrate 110, silicon substrate, metal support plate or interposer substrate.In addition, substrate 110 can be single or multiple lift circuit base plate.
Please refer to Figure 1B, it illustrates the cutaway view along direction 1B-1B ' in Figure 1A.Chip 120 is located on the upper surface 110u of substrate 110 in orientation down with its active surface (being such as the first surface 120b towards substrate 110 of chip 120), and being electrically connected at substrate 110 by least one electrical contact 121, this kind of chip 120 is called and covers crystalline substance (flip chip).Electrical contact 121 is projection, soldered ball or conductive pole such as.
The side 120s of packaging body 130 coating chip 120 and there is groove 130r.The second surface 120u away from substrate 110 of groove 130r exposed chip 120.In this example, the whole second surface 120u of groove 130r exposed chip 120, using provides maximum and exposes area, with fast the heat loss of chip 120 to outside semiconductor package part 100.
The bottom surface 130b of groove 130r lower than the second surface 120u of chip 120, but higher than the first surface 120b of chip 120.Because the bottom surface 130b of groove 130r is higher than the first surface 120b of chip 120, make between the bottom surface 130b of groove 130r and the first surface 120b of chip 120, to form a mould fluid space S.In packaging technology, the encapsulating material 130 ' (Fig. 3 C) in flowable state can fill up space between the first surface 120b of the chip 120 and upper surface 110u of substrate 110 and coated electrical contact 121 swimmingly through mould fluid space S thus.
In one example, the distance H1 of the upper surface 130u of packaging body 130 and the second surface 120u of chip 120 is between 0 to 110 micron, and the distance H2 of the second surface 120u of chip 120 and the bottom surface 130b of groove 130r is between 0 to 110 micron, make the distance H3 (conjunction of distance H1 and H2) of the upper surface 130u of packaging body 130 and the bottom surface 130b of groove 130r between 0 to 220 micron.In addition, the thickness T1 of chip 120 about 800 microns, so also can be thinner or thicker.The value of above-mentioned distance H1, H2 and H3 also can adjust with the thickness of chip, and wherein distance H2 and distance H1, lower than distance H3, can avoid the upper surface of substrate to expose the problem causing reliability to reduce according to an embodiment of the invention.
Groove 130r extends from the upper surface 130u of packaging body 130 toward the direction of chip 120 and substrate 110, and groove 130r is connected and the second surface 120u of exposed chip 120 with the upper surface 130u of packaging body 130.Groove 130r comprises the first sub-groove 130r1 and the second sub-groove 130r2.First sub-groove 130r1 is communicated in the second sub-groove 130r2, and the second surface 120u of exposed chip 120, be such as the whole second surface 120u of exposed chip 120, to promote the radiating effect to chip 120.
The internal diameter D1 of the second sub-groove 130r2 from the upper surface 130u of packaging body 130 toward the direction convergent of the bottom surface 130b of groove 130r, and forms a bowl-type groove, V-type groove or other suitable recess profile, and this example is for bowl-type groove.With regard to the profile of the second sub-groove 130r2, after the medial surface 130s of the second sub-groove 130r2 extends a distance H3 from the upper surface 130u of packaging body 130 toward substrate 110 direction, then extend to the side 120s of chip 120 toward the direction of the second surface 120u of chip 120.When the medial surface 130s of the second sub-groove 130r2 and the contact position of side 120s are more near the second surface 120u of chip 120, the scope that packaging body 130 covers the side 120s of chip 120 is larger.In this example, the second surface 120u of medial surface 130s contact chip 120 of the second sub-groove 130r2 and the corner of side 120s, can make packaging body 130 cover the whole side 120s of chip 120.
Please refer to Fig. 2, it illustrates the schematic diagram of the measuring semiconductor packaging part of Figure 1B.When semiconductor package part 100 acceptance test, pressing plate 150 can be pressed on semiconductor package part 100, makes electrical contact 140 in electrical contact to test fingers 160.Because the upper surface 130u of the packaging body 130 of the present embodiment is higher than the second surface 120u of chip 120, therefore pressing plate 150 contacts the upper surface 130u of packaging body 130, and directly can not be pressed onto chip 120, and then reduces the probability that chip 120 damages.
In another example, the upper surface 130u of the packaging body 130 and second surface 120u of chip 120 can substantial alignment, such as, be coplanar.Under this design, pressing plate 150 compresses the second surface 120u of the chip 120 and upper surface 130u of packaging body 130 simultaneously, making chip 120 and packaging body 130 share compression chord together, because this reducing the compression chord of chip 120 itself, and then reducing the probability of chip 120 damage.
Please refer to Fig. 3 A to Fig. 3 B, it illustrates the process drawing of the semiconductor package part of Figure 1B.
As shown in Figure 3A, patrix 210 and counterdie 220 are provided.Patrix 210 comprises upper die body 211, middle plate 212 and can deformation element 213, wherein, middle plate 212 is located on upper die body 211, and middle plate 212 has the recess 212r of an opening towards counterdie 220, can be located on the end face 212u of the recess 212r of middle plate 212 by deformation element 213.The internal diameter D2 of recess 212r, from the end face 212u of recess 212r toward the opening direction convergent of recess 212r, makes to establish can not drop easily by deformation element 213 in the inner.Can deformation element 213 be such as be made up of rubber or suitable elastomeric material, material behavior by this, make easily to be installed in the recess 212r of middle plate 212 by deformation element 213, and be installed in the wall that the interior rear generation resilience force of recess 212r compresses recess 212r, and then be stable in recess 212r.
Counterdie 220 comprises lower mold body 221 and loading plate 222.Lower mold body 221 has recess 221r, and loading plate 222 can be located on the bottom surface 221b of recess 221r.Loading plate 222 liftable, to adjust the height and position of substrate 110 provided thereon.
As shown in Figure 3A, arrange substrate 110 and chip 120 in the bottom of counterdie 220, wherein substrate 110 is located on loading plate 22, and chip 120 to be located on substrate 110 by electrical contact 121 and to be positioned at can immediately below deformation element 213.
As shown in Figure 3 B, matched moulds counterdie 220 and patrix 210.Such as, patrix 210 moves and matched moulds toward the direction of counterdie 220, in process, the extruding of chip 120 can be subject to and form ring-type teat 2131 in the side 120s of chip 120 by deformation element 213, wherein ring-type teat 2,131 one closed circular teat, its around the side 120s of chip 120 and the bottom surface 2131b of ring-type teat 2131 lower than the second surface 120u of chip 120.
After patrix 210 and counterdie 220 matched moulds, can be determined by following formula (1) by compression one compressed thickness P, this compressed thickness P by deformation element 213.
P＝(T2+H5)-H4.................................................(1)
In formula (1), thickness T2 (Fig. 3 A) can the original depth of deformation element 213, the distance of the end face 212u of the plate 212 and upper surface 110u of substrate 110 in distance H4, and the second surface 120u of distance H5 chip 120 is to the distance of the upper surface 110u of substrate 110.Design (getting final product the design of deformation element 213 compression ratio) via suitable compressed thickness P, make can closely be pressed on the second surface 120u of chip 120 by deformation element 213, to avoid or the encapsulating material 130 ' (Fig. 3 C) reduced in flowable state in subsequent technique flow to the second surface 120u that can cover chip 120 between deformation element 213 and chip 120.
In this example, compressed thickness P is less than the thickness T1 of chip 120, so can make the first surface 120b of bottom surface 2131b higher than chip 120 of ring-type teat 2131.In one example, the thickness T1 of chip 120 is such as about 800 microns; So also can adopt thinner or thicker chip, if this, can coordinate adjustment by the thickness T2 of deformation element 213 and compressed thickness P, with the geometry kenel of ring-type teat 2131 obtaining expection or preset.Because the bottom surface 2131b of ring-type teat 2131 is higher than the first surface 120b of chip 120, make to form a mould fluid space S between the bottom surface 2131b of ring-type the teat 2131 and first surface 120b of chip 120, this mould fluid space S can allow the encapsulating material 130 ' (Fig. 3 C) in flowable state flow to space between the first surface 120b of chip 120 and substrate 110 swimmingly.
After patrix 210 and counterdie 220 matched moulds, the end face 230u of middle plate 212 higher than or the second surface 120u of substantial alignment chip 120, this example illustrates for the second surface 120u higher than chip 120.In one example, the distance H1 of the end face 230u of middle plate 212 and the second surface 120u of chip 120 is between 0 to 110 micron, and the distance H2 of the second surface 120u of chip 120 and the bottom surface 2131b of ring-type teat 2131 is between 0 to 110 micron, make the distance of the end face 230u of middle plate 212 and the bottom surface 2131b of ring-type teat 2131 between 0 to 220 micron.
When patrix 210 and counterdie 220 matched moulds, between the middle plate 212 of patrix 210 and the loading plate 222 of counterdie 220, form a die cavity 230r.The profile of die cavity 230r can determine the outline of the packaging body 130 of follow-up formation, and the right embodiment of the present invention does not limit the contour shape of die cavity 230r, and therefore the outline of packaging body 130 can have multiple geometric shape.
As shown in Figure 3 C, the encapsulating material 130 ' of filled high-temperature flowable state is in die cavity 230r, wherein encapsulating material 130 ' is after touching the outside 213s1 of annular protrusion 2131, walk around the inner side 213s2 of bottom surface 2131b to annular protrusion 2131 of annular protrusion 2131, and the side 120s covering chip 120 at least partially.In addition, encapsulating material 130 ' also enters into the space between the first surface 120b of the chip 120 and upper surface 110u of substrate 110 via the mould fluid space S between the bottom surface 2131b of annular protrusion 2131 and the upper surface 110u of substrate 110, and coated electrical contact 121, under this design, extra primer (underfill) can be omitted.In addition, after encapsulating material 130 ' mold filling, encapsulating material 130 ' covers the end face 230u of die cavity 230r, and forms the upper surface 130u of encapsulating material 130 '.Become the packaging body 130 of Figure 1B after encapsulating material 130 ' cooled and solidified, so far, form semiconductor package part 100 as shown in Figure 1A.
In sum, although the present invention with embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (11)
1. a method for packing for semiconductor package part, is characterized in that, comprising:
There is provided a patrix and a counterdie, this patrix comprises one can deformation element;
Arrange a substrate and a chip on this counterdie, wherein this chip to be located on this substrate and to be positioned at this and can have a upper surface immediately below deformation element;
This counterdie of matched moulds and this patrix form a die cavity, this can extrude this chip and forms a ring-type teat by deformation element, one bottom surface of this ring-type teat is lower than this upper surface of this chip, and this counterdie and this patrix are after matched moulds, end face alignment or this upper surface higher than this chip of this die cavity; And
Fill in an encapsulating material this die cavity between this counterdie and this patrix, wherein this encapsulating material this chip coated and cover this end face of this die cavity.
2. method for packing as claimed in claim 1, is characterized in that, in the step of this counterdie of matched moulds and this patrix, this bottom surface of this ring-type teat is higher than a lower surface of this chip.
3. method for packing as claimed in claim 1, is characterized in that, in arranging this chip and this substrate in the step of this counterdie, this chip is located on this substrate with an electrical contact; In filling in this encapsulating material this step in this die cavity, this encapsulating material is filled in this electrical contact coated between this chip and this substrate.
4. method for packing as claimed in claim 1, it is characterized in that, this counterdie comprises:
One lower mold body, has a recess; And
One loading plate, is located at this recess of this lower mold body;
In arranging this chip and this substrate in this step of this counterdie, this substrate is located on this loading plate.
5. method for packing as claimed in claim 1, it is characterized in that, this can be made up of rubber by deformation element.
6. a semiconductor package part, is characterized in that, comprising:
One substrate, has a upper surface;
One chip, have one in the face of the first surface and of substrate is away from the second surface of this substrate, the first surface of this chip is located at the upper surface of this substrate and is electrically connected at this substrate; And
One packaging body, this chip coated, this packaging body has a groove and a upper surface, this upper surface of this packaging body higher than or be aligned in this second surface of this chip, this groove has a bottom surface, wherein this groove is connected with this upper surface of this packaging body and exposes this second surface of this chip, and this bottom surface of this groove is lower than this second surface of this chip.
7. semiconductor package part as claimed in claim 6, it is characterized in that, this groove exposes this second surface whole of this chip.
8. semiconductor package part as claimed in claim 6, it is characterized in that, this chip has a side, and this packaging body covers this side of this chip at least partially.
9. semiconductor package part as claimed in claim 6, it is characterized in that, this groove comprises one first sub-groove and one second sub-groove, and this first sub-groove exposes this second surface of this chip, and this second sub-groove is around a side of this chip.
10. semiconductor package part as claimed in claim 6, is characterized in that, this bottom surface of this groove is higher than the lower surface of this chip.
11. semiconductor package parts as claimed in claim 6, is characterized in that, more comprise:
One electrical contact, is electrically connected this chip and this substrate between this first surface and this substrate of this chip;
Wherein, this packaging body is formed at this electrical contact coated between this chip and this substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310047921.9A CN103077901B (en) | 2013-02-06 | 2013-02-06 | The method for packing of semiconductor package part and apply its semiconductor package part formed |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310047921.9A CN103077901B (en) | 2013-02-06 | 2013-02-06 | The method for packing of semiconductor package part and apply its semiconductor package part formed |
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| Publication Number | Publication Date |
|---|---|
| CN103077901A CN103077901A (en) | 2013-05-01 |
| CN103077901B true CN103077901B (en) | 2015-10-28 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1347154A (en) * | 2000-10-05 | 2002-05-01 | 三洋电机株式会社 | Semiconductor device and semiconductor assembly |
| JP5169964B2 (en) * | 2009-04-10 | 2013-03-27 | 株式会社デンソー | Mold package mounting structure and mounting method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100652405B1 (en) * | 2005-03-28 | 2006-12-01 | 삼성전자주식회사 | Mold die set for preventing a resin bleed defect and manufacturing method of semiconductor package using the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1347154A (en) * | 2000-10-05 | 2002-05-01 | 三洋电机株式会社 | Semiconductor device and semiconductor assembly |
| JP5169964B2 (en) * | 2009-04-10 | 2013-03-27 | 株式会社デンソー | Mold package mounting structure and mounting method |
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| CN103077901A (en) | 2013-05-01 |
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