CN103077901A - Packaging method of semiconductor packaging member and semiconductor packaging member formed by applying packaging method - Google Patents
Packaging method of semiconductor packaging member and semiconductor packaging member formed by applying packaging method Download PDFInfo
- Publication number
- CN103077901A CN103077901A CN2013100479219A CN201310047921A CN103077901A CN 103077901 A CN103077901 A CN 103077901A CN 2013100479219 A CN2013100479219 A CN 2013100479219A CN 201310047921 A CN201310047921 A CN 201310047921A CN 103077901 A CN103077901 A CN 103077901A
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- Prior art keywords
- chip
- substrate
- groove
- counterdie
- semiconductor package
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Abstract
The invention discloses a packaging method of a semiconductor packaging member and a semiconductor packaging member formed by applying the packaging method. The semiconductor packaging member comprises a base plate, a chip and a packaging body. The chip is provided with a first surface facing the base plate and a second surface which is far away from the base plate. The packaging body packages the chip and is provided with a slot and an upper surface, the upper surface of the packaging body is higher than or aligned to the second surface of the chip; and the slot is connected with the upper surface of the packaging body and protrudes the second surface of the chip, and the bottom surface of the slot is lower than the second surface.
Description
Technical field
The invention relates to a kind of method for packing of semiconductor package part and use the semiconductor package part of its formation, and particularly relevant for a kind of method for packing of the semiconductor package part that improves heat dissipation problem and use the semiconductor package part of its formation.
Background technology
Traditional semiconductor package part comprises chip and packaging body.In order to protect chip, the side of the common coating chip of packaging body and upper surface.Yet complete like this coating is difficult for the heat of dissipation chip on the contrary.
In addition, if though the upper surface of chip and lateral margin are exposed to fully and have better radiating effect in the external world and easily cause chip to meet the external force collision and the risk damaged.
Summary of the invention
The present invention among one embodiment, can improve the not good problem of known chip cooling and can reduce chip suffering extraneous collision and the risk of damage relevant for a kind of semiconductor package part.
According to the present invention, a kind of method for packing of semiconductor package part is proposed.The method for packing of semiconductor package part may further comprise the steps.Provide a patrix and a counterdie, but patrix comprises a deformation element; One substrate and a chip are set in counterdie, but its chips is located on the substrate and is positioned under the deformation element and has a upper surface; Matched moulds counterdie and patrix and form a die cavity, but make deformation element extruding chip and form a ring-type teat, a bottom surface of ring-type teat is lower than the upper surface of chip, and counterdie and patrix be behind matched moulds, and an end face of die cavity aligns or is higher than the upper surface of chip; And, fill in the die cavity of an encapsulating material between patrix and counterdie, wherein the end face of encapsulating material coating chip and covering die cavity.
According to the present invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a substrate, a chip and a packaging body.Chip has a first surface and the second surface away from substrate in the face of substrate.Packaging body coats chip and have a groove and a upper surface, the upper surface of packaging body is higher than or is aligned in the second surface of chip, and its further groove links to each other with the upper surface of packaging body and the second surface of exposed chip, and the bottom surface of groove is lower than the second surface of chip.
For foregoing of the present invention can be become apparent, embodiment cited below particularly, and cooperation accompanying drawing are described in detail below:
Description of drawings
Figure 1A illustrates the outside drawing according to the semiconductor package part of one embodiment of the invention.
Figure 1B illustrates among Figure 1A the cutaway view along direction 1B-1B '.
Fig. 2 illustrates the schematic diagram of the measuring semiconductor packaging part of Figure 1B.
Fig. 3 A to 3C illustrates the process drawing of the semiconductor package part of Figure 1B.
The main element symbol description:
100: semiconductor package part
110: substrate
110u, 130u: upper surface
120: chip
120b: first surface
120u: second surface
120s: side
121,140: electrical contact
130: packaging body
130 ': encapsulating material
130b, 221b, 2131b: bottom surface
130r: groove
130r1: the first sub-groove
130r2: the second sub-groove
130s: medial surface
150: pressing plate
160: test fingers
210: patrix
211: upper die body
212: middle plate
212r, 221r: recess
213: but the deformation element
213s1: the outside
213s2: inboard
2131: annular protrusion
220: counterdie
221: lower mold body
222: loading plate
230r: die cavity
230u, 212u: end face
2131: the ring-type teat
D1, D2: internal diameter
H1, H2, H3, H4, H5: distance
P: compressed thickness
S: mould fluid space
T1, T2: thickness
Embodiment
Please refer to Figure 1A, it illustrates the outside drawing according to the semiconductor package part of one embodiment of the invention.Semiconductor package part 100 comprises substrate 110, chip 120, packaging body 130 and at least one electrical contact 140.
Please refer to Figure 1B, it illustrates among Figure 1A the cutaway view along direction 1B-1B '.Chip 120 is located on the upper surface 110u of substrate 110 in the orientation down with its active surface (for example being the first surface 120b towards substrate 110 of chip 120), and being electrically connected at substrate 110 by at least one electrical contact 121, this kind chip 120 is called and covers crystalline substance (flip chip).Electrical contact 121 is projection, soldered ball or conductive pole for example.
The side 120s of packaging body 130 coating chips 120 and have groove 130r.The second surface 120u away from substrate 110 of groove 130r exposed chip 120.In this example, the whole second surface 120u of groove 130r exposed chip 120, using provides maximum to expose area, with fast the heat loss of chip 120 to semiconductor package part 100.
The bottom surface 130b of groove 130r is lower than the second surface 120u of chip 120, but is higher than the first surface 120b of chip 120.Because the bottom surface 130b of groove 130r is higher than the first surface 120b of chip 120, formation one mould fluid space S between the bottom surface 130b that makes groove 130r and the first surface 120b of chip 120.In packaging technology, the encapsulating material 130 ' (Fig. 3 C) that is flowable state can fill up swimmingly the space between the upper surface 110u of the first surface 120b of chip 120 and substrate 110 through mould fluid space S thus and coat electrical contact 121.
In one example, the distance H 1 of the upper surface 130u of packaging body 130 and the second surface 120u of chip 120 is between 0 to 110 micron, and the distance H 2 of the bottom surface 130b of the second surface 120u of chip 120 and groove 130r is between 0 to 110 micron, makes the distance H 3 (distance H 1 and H2 close) of bottom surface 130b of the upper surface 130u of packaging body 130 and groove 130r between 0 to 220 micron.In addition, approximately 800 microns of the thickness T 1 of chip 120 so also can be thinner or thicker.The value of above-mentioned distance H 1, H2 and H3 also can be with the thickness adjustment of chip, and wherein distance H 2 is lower than distance H 3 with distance H 1 according to an embodiment of the invention, can avoid the upper surface of substrate to expose the problem that causes reliability to reduce.
Groove 130r from the upper surface 130u of packaging body 130 toward chip 120 and the direction of substrate 110 extend, groove 130r is linked to each other and the second surface 120u of exposed chip 120 with the upper surface 130u of packaging body 130.Groove 130r comprises the first sub-groove 130r1 and the second sub-groove 130r2.The first sub-groove 130r1 is communicated in the second sub-groove 130r2, and the second surface 120u of exposed chip 120, for example is the whole second surface 120u of exposed chip 120, to promote the radiating effect to chip 120.
The direction convergent of the bottom surface 130b of the inside diameter D 1 of the second sub-groove 130r2 from the upper surface 130u of packaging body 130 toward groove 130r, and consist of a bowl-type groove, V-type groove or other suitable recess profile, this example is take the bowl-type groove as example.Profile with regard to the second sub-groove 130r2, after the medial surface 130s of the second sub-groove 130r2 extends a distance H 3 from the upper surface 130u of packaging body 130 toward substrate 110 directions, extend to again the side 120s of chip 120 toward the direction of the second surface 120u of chip 120.When the contact position of the medial surface 130s of the second sub-groove 130r2 and side 120s more near the second surface 120u of chip 120, the scope of side 120s that packaging body 130 covers chips 120 is larger.In this example, the second surface 120u of the medial surface 130s contact chip 120 of the second sub-groove 130r2 and the corner of side 120s can make packaging body 130 cover the whole side 120s of chip 120.
Please refer to Fig. 2, it illustrates the schematic diagram of the measuring semiconductor packaging part of Figure 1B.When semiconductor package part 100 acceptance test, pressing plate 150 can be pressed on the semiconductor package part 100, makes electrical contact 140 electrical contacts to test fingers 160.Because the upper surface 130u of the packaging body 130 of the present embodiment is higher than the second surface 120u of chip 120, thus the upper surface 130u of pressing plate 150 contact packaging bodies 130, and can directly not be pressed onto chip 120, and then reduce the probability that chip 120 damages.
In another example, the upper surface 130u of packaging body 130 can align in fact with the second surface 120u of chip 120, for example is coplanar.Under this design, pressing plate 150 compresses the second surface 120u of chip 120 and the upper surface 130u of packaging body 130 simultaneously, therefore make chip 120 and packaging body 130 share together compression chord, reduced the compression chord of chip 120 itself, and then reduced the probability that chip 120 damages.
Please refer to Fig. 3 A to Fig. 3 B, it illustrates the process drawing of the semiconductor package part of Figure 1B.
As shown in Figure 3A, provide patrix 210 and counterdie 220.But patrix 210 comprises upper die body 211, middle plate 212 and deformation element 213, wherein, middle plate 212 is located on the upper die body 211, and middle plate 212 has an opening towards the recess 212r of counterdie 220, but deformation element 213 is located on the end face 212u of recess 212r of middle plate 212.The opening direction convergent of the inside diameter D 2 of recess 212r from the end face 212u of recess 212r toward recess 212r, but the deformation element 213 of establishing in the inner can not dropped easily.But deformation element 213 for example is to be made by rubber or suitable elastomeric material, material behavior by this, but deformation element 213 easily is installed in the recess 212r of middle plate 212, and the generation resilience force compresses the wall of recess 212r after being installed in the recess 212r, and then be stable in the recess 212r.
As shown in Figure 3A, substrate 110 and chip 120 are set in the bottom of counterdie 220, wherein substrate 110 is located on the loading plate 22, but and chip 120 is located on the substrate 110 by electrical contact 121 and be positioned under the deformation element 213.
Shown in Fig. 3 B, matched moulds counterdie 220 and patrix 210.For example, patrix 210 moves and matched moulds toward the direction of counterdie 220, in the process, but deformation element 213 is subject to the extruding of chip 120 and forms ring-type teat 2131 in the side of chip 120 120s, ring-type teat 2,131 one closed circular teats wherein, its bottom surface 2131b around the side 120s of chip 120 and ring-type teat 2131 is lower than the second surface 120u of chip 120.
Behind patrix 210 and counterdie 220 matched moulds, but deformation element 213 compressed compressed thickness P, and this compressed thickness P can be determined by following formula (1).
P＝(T2+H5)-H4.................................................(1)
In the formula (1), thickness T 2 (Fig. 3 A) but the distance of the upper surface 110u of the end face 212u of plate 212 and substrate 110 in the original depth of deformation element 213, distance H 4, and the second surface 120u of distance H 5 chips 120 is to the distance of the upper surface 110u of substrate 110.Via suitable compressed thickness P design (getting final product the design of deformation element 213 compression ratios), but make deformation element 213 closely be pressed on the second surface 120u of chip 120, avoid or reduce the encapsulating material 130 ' (Fig. 3 C) that is flowable state in the subsequent technique but flow to deformation element 213 and chip 120 between and cover the second surface 120u of chip 120.
In this example, compressed thickness P is less than the thickness T 1 of chip 120, so can make the bottom surface 2131b of ring-type teat 2131 be higher than the first surface 120b of chip 120.In one example, the thickness T 1 of chip 120 for example is approximately 800 microns; So also can adopt thinner or thicker chip, if this, but the thickness T 2 of deformation element 213 and compressed thickness P can cooperate adjustment, to obtain the geometry kenel of expection or default ring-type teat 2131.Because the bottom surface 2131b of ring-type teat 2131 is higher than the first surface 120b of chip 120, make between the first surface 120b of the bottom surface 2131b of ring-type teat 2131 and chip 120 and form a mould fluid space S, this mould fluid space S can allow the encapsulating material 130 ' (Fig. 3 C) that is flowable state flow to swimmingly the first surface 120b of chip 120 and the space between the substrate 110.
Behind patrix 210 and counterdie 220 matched moulds, the end face 230u of middle plate 212 is higher than or the second surface 120u of the chip 120 that aligns in fact, and this example is take the second surface 120u that is higher than chip 120 as the example explanation.In one example, the distance H 1 of the end face 230u of middle plate 212 and the second surface 120u of chip 120 is between 0 to 110 micron, and the distance H 2 of the bottom surface 2131b of the second surface 120u of chip 120 and ring-type teat 2131 is between 0 to 110 micron, makes the distance of bottom surface 2131b of the end face 230u of middle plate 212 and ring-type teat 2131 between 0 to 220 micron.
When patrix 210 and counterdie 220 matched moulds, form a die cavity 230r between the middle plate 212 of patrix 210 and the loading plate 222 of counterdie 220.The profile of die cavity 230r can determine the outline of the packaging body 130 of follow-up formation, and the right embodiment of the invention does not limit the contour shape of die cavity 230r, so the outline of packaging body 130 can have multiple geometric shape.
Shown in Fig. 3 C, the encapsulating material 130 ' of filled high-temperature flowable state is in die cavity 230r, wherein encapsulating material 130 ' is after touching the outside 213s1 of annular protrusion 2131, walk around the bottom surface 2131b of annular protrusion 2131 to the inboard 213s2 of annular protrusion 2131, and cover at least a portion of the side 120s of chip 120.In addition, encapsulating material 130 ' also enters into space between the upper surface 110u of the first surface 120b of chip 120 and substrate 110 via the mould fluid space S between the upper surface 110u of the bottom surface 2131b of annular protrusion 2131 and substrate 110, and coating electrical contact 121, under this design, can omit extra primer (underfill).In addition, after encapsulating material 130 ' mold filling, encapsulating material 130 ' covers the end face 230u of die cavity 230r, and forms the upper surface 130u of encapsulating material 130 '.Become the packaging body 130 of Figure 1B after the encapsulating material 130 ' cooled and solidified, so far, form the semiconductor package part 100 shown in Figure 1A.
In sum, although the present invention discloses as above with embodiment, so it is not to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (11)
1. the method for packing of a semiconductor package part is characterized in that, comprising:
Provide a patrix and a counterdie, but this patrix comprises a deformation element;
One substrate and a chip are set on this counterdie, but wherein this chip is located on this substrate and is positioned under this deformation element and has a upper surface;
This counterdie of matched moulds and this patrix form a die cavity, but should push this chip and form a ring-type teat by the deformation element, one bottom surface of this ring-type teat is lower than this upper surface of this chip, and this counterdie and this patrix be behind matched moulds, an end face of this die cavity alignment or be higher than this upper surface of this chip; And
Fill in an encapsulating material this die cavity between this counterdie and this patrix, wherein this encapsulating material coats this chip and covers this end face of this die cavity.
2. method for packing as claimed in claim 1 is characterized in that, in the step of this counterdie of matched moulds and this patrix, this bottom surface of this ring-type teat is higher than a lower surface of this chip.
3. method for packing as claimed in claim 1 is characterized in that, in this chip and this substrate being set in the step of this counterdie, this chip is located on this substrate with an electrical contact; In filling this encapsulating material this step in this die cavity, this encapsulating material is filled between this chip and this substrate and coats this electrical contact.
4. method for packing as claimed in claim 1 is characterized in that, this counterdie comprises:
One lower mold body has a recess; And
One loading plate is located at this recess of this lower mold body;
In this chip and this substrate being set in this step of this counterdie, this substrate is located on this loading plate.
5. method for packing as claimed in claim 1 is characterized in that, but should be made by rubber by the deformation element.
6. a semiconductor package part is characterized in that, comprising:
One substrate;
One chip has first surface and the second surface away from this substrate in the face of substrate; And
One packaging body, coat this chip, this packaging body has a groove and a upper surface, this upper surface of this packaging body is higher than or is aligned in this second surface of this chip, this groove has a bottom surface, wherein this groove links to each other with this upper surface of this packaging body and exposes this second surface of this chip, and this bottom surface of this groove is lower than this second surface of this chip.
7. semiconductor package part as claimed in claim 6 is characterized in that, this groove exposes whole this second surface of this chip.
8. semiconductor package part as claimed in claim 6 is characterized in that, this chip has a side, and this packaging body covers at least a portion of this side of this chip.
9. semiconductor package part as claimed in claim 6 is characterized in that, this groove comprises one first sub-groove and one second sub-groove, and this first sub-groove exposes this second surface of this chip, and this second sub-groove is around a side of this chip.
10. semiconductor package part as claimed in claim 6 is characterized in that, this bottom surface of this groove is higher than the lower surface of this chip.
11. semiconductor package part as claimed in claim 6 is characterized in that, more comprises:
One electrical contact is between this first surface of this chip and this substrate and be electrically connected this chip and this substrate;
Wherein, this packaging body is formed between this chip and this substrate and coats this electrical contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310047921.9A CN103077901B (en) | 2013-02-06 | 2013-02-06 | The method for packing of semiconductor package part and apply its semiconductor package part formed |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310047921.9A CN103077901B (en) | 2013-02-06 | 2013-02-06 | The method for packing of semiconductor package part and apply its semiconductor package part formed |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103077901A true CN103077901A (en) | 2013-05-01 |
| CN103077901B CN103077901B (en) | 2015-10-28 |
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| CN201310047921.9A Active CN103077901B (en) | 2013-02-06 | 2013-02-06 | The method for packing of semiconductor package part and apply its semiconductor package part formed |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1347154A (en) * | 2000-10-05 | 2002-05-01 | 三洋电机株式会社 | Semiconductor device and semiconductor assembly |
| US20060214283A1 (en) * | 2005-03-28 | 2006-09-28 | Sang-Uk Kim | Semiconductor packaging mold and method of manufacturing semiconductor package using the same |
| JP5169964B2 (en) * | 2009-04-10 | 2013-03-27 | 株式会社デンソー | Mold package mounting structure and mounting method |
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2013
- 2013-02-06 CN CN201310047921.9A patent/CN103077901B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1347154A (en) * | 2000-10-05 | 2002-05-01 | 三洋电机株式会社 | Semiconductor device and semiconductor assembly |
| US20060214283A1 (en) * | 2005-03-28 | 2006-09-28 | Sang-Uk Kim | Semiconductor packaging mold and method of manufacturing semiconductor package using the same |
| JP5169964B2 (en) * | 2009-04-10 | 2013-03-27 | 株式会社デンソー | Mold package mounting structure and mounting method |
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| Publication number | Publication date |
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| CN103077901B (en) | 2015-10-28 |
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