CN103053025A - 具有阈值电压设定掺杂剂结构的先进晶体管 - Google Patents

具有阈值电压设定掺杂剂结构的先进晶体管 Download PDF

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CN103053025A
CN103053025A CN2011800358321A CN201180035832A CN103053025A CN 103053025 A CN103053025 A CN 103053025A CN 2011800358321 A CN2011800358321 A CN 2011800358321A CN 201180035832 A CN201180035832 A CN 201180035832A CN 103053025 A CN103053025 A CN 103053025A
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threshold voltage
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CN103053025B (zh
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L·希弗伦
P·拉纳德
L·斯卡德
S·E·汤普森
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Triple Fujitsu Semiconductor Co., Ltd.
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Abstract

一种具有阈值电压设定掺杂剂结构的先进晶体管，包括具有长度Lg的栅极和掺杂为具有第一掺杂剂浓度的阱。屏蔽区域定位在所述阱与所述栅极之间且具有大于5×1018个掺杂剂原子/cm3的第二掺杂剂浓度。阈值电压设定区域由设置定位在所述屏蔽区域上方的阈值电压偏移平面形成。所述阈值电压设定区域可以由德尔塔掺杂形成且具有介于Lg/5与Lg/1之间的厚度。所述结构使用最小的晕环注入或不使用晕环注入来将沟道掺杂剂浓度保持在小于5×1017个掺杂剂原子/cm3。

Description

具有阈值电压设定掺杂剂结构的先进晶体管
相关申请
本申请要求2009年9月30日提交的美国临时申请No.61/247300的优先权，将该临时申请的公开内容通过引用并入于此。本申请还要求其公开内容通过引用并入于此的2009年11月17日提交的美国临时申请No.61/262122以及其公开内容通过引用并入于此的2010年2月18日提交的、发明名称为“Electronic Devices and Systems,and Methods for Making andUsing the Same”的美国专利申请No.12/708497的优先权。本申请还要求其公开内容通过引用并入于此的2010年6月22日提交的美国临时申请No.61/357492的优先权。
技术领域
本公开内容涉及形成具有包括阈值电压设定掺杂剂结构的改进的工作特性的先进晶体管的结构和工艺。
背景技术
场效应晶体管（FET）导通或关断时的电压是晶体管工作的关键参数。具有通常约为工作电压（VDD）的0.3倍的低阈值电压（VT）的晶体管能够迅速开关，但是还是具有相对较高的关态电流泄漏。具有通常约为工作电压（VDD）的0.7倍的高阈值电压（VT）的晶体管开关较慢，但是具有相对较低的关态电流泄漏。半导体电子设计者通过制造具有带有不同阈值电压的多个晶体管器件的管芯，对于高速关键路径采用低VT而不经常访问的电路则采用节省电能的高VT，来采用其优点。
用于设定VT的常规解决方案包括采用VT掺杂剂对晶体管沟道进行掺杂。通常，掺杂剂剂量越高，器件的VT越高。沟道还可以由源极和漏极周围的高注入角“袋状物”（pocket）或“晕环”（halo）注入来掺杂。沟道VT注入和晕环注入可以关于晶体管的源极和漏极对称或不对称，并且将两者一起使用来使VT增大到期望的电平。不幸的是，这样的注入对电子迁移率产生不利的影响，这主要是因为沟道中的掺杂剂散射增大，并且随着晶体管尺寸向下缩小，对于有用的VT设定点，在纳米级晶体管中所需的掺杂剂密度和注入位置控制越来越难以支持。
许多半导体制造商都试图通过采用新的晶体管类型（包括全部或部分耗尽的绝缘体上硅（SOI）晶体管）来避免体CMOS的缩放问题（包括具有纳米级栅极晶体管尺寸的晶体管中的不利的“短沟道效应”）。SOI晶体管构建在绝缘体层之上的薄硅层上，并通常需要VT设定沟道注入或晕环注入来工作。不幸的是，形成合适的绝缘体层十分昂贵且难以完成。早期的SOI器件构建在绝缘蓝宝石晶片上而非硅晶片上，并且因为成本高，通常仅用于特殊应用（例如军用航空电子设备或卫星）。现代的SOI技术可以使用硅晶片，但需要昂贵且费时的额外的晶片处理步骤来制作延伸跨越器件质量单晶硅的表面层下的整个晶片的绝缘氧化硅层。
在硅晶片上制作这样的氧化硅层的一种常用方法需要高剂量氧离子注入和高温退火，以在体硅晶片中形成埋入氧化物（BOX）层。或者，可以通过将一个硅晶片键合到表面上具有氧化物层的另一硅晶片（“处理”晶片）来制造SOI。使用在处理晶片的BOX层的顶部上留下单晶硅的薄晶体管质量层的工艺来将这对晶片分开。这就是所谓的“层转移”技术，因为该技术将薄硅层转移到处理晶片的热生长氧化物层上。
如所预期的，BOX形成或层转移这两者都是具有相对较高故障率的昂贵制造技术。因此，对于许多领先的制造商而言，制造SOI晶体管不是经济上有吸引力的解决方案。当重新设计晶体管以应对“浮体（floating body）”效应、研发新的SOI特定晶体管工艺的需要和其它电路变化的成本被添加到SOI晶片的成本时，很显然需要其它解决方案。
正在研究的另一可能的先进晶体管采用多栅极晶体管，其类似于SOI晶体管，通过在沟道中少量掺杂或不掺杂来使不利的缩放和短沟道效应最小化。通常称为finFET（由于由栅极部分地围绕的鳍形状的沟道），对具有28纳米或更低晶体管栅极尺寸的晶体管提出使用finFET晶体管。但同样，类似于SOI晶体管，虽然换到全新的晶体管架构解决了某些缩放、VT设定点和短沟道效应问题，但是又产生了需要比SOI更加显著的晶体管布局重新设计的其它问题。考虑到可能需要复杂的非平面晶体管制造技术来制作finFET以及创建finFET的新工艺流程的未知困难，制造商一直不愿在能制作finFET的半导体制造设施上投资。
附图说明
图1示出了具有改进的阈值电压设定区域掺杂剂结构的DDC晶体管；
图2示出了具有阈值电压设定区域掺杂剂结构的一个掺杂剂分布；
图3示意性地示出了预退火阈值电压掺杂剂分布；以及
图4示出了支持德尔塔（delta）掺杂的VT结构的代表性流程图。
具体实施方式
纳米级的体CMOS晶体管（栅极长度通常小于100纳米的晶体管）越来越难以制造，部分因为VT缩放不匹配VDD缩放。通常，对于栅极尺寸大于100纳米的晶体管而言，晶体管的栅极长度的减小包括工作电压VDD的大致成比例的减小，这一起确保了大致相当的电场和工作特性。减小工作电压VDD的能力部分取决于能准确地设定阈值电压VT，但是随着晶体管大小减小，由于多种因素（例如包括随机掺杂剂波动（RDF））而变得越来越困难。对于使用体CMOS工艺制作的晶体管而言，设定阈值电压VT的主要参数是沟道中掺杂剂的量。从理论上讲，这可以精确地完成，以便在同一芯片上的相同晶体管具有相同的VT，但实际上阈值电压可以显著变化。这意味着这些晶体管将不会响应于相同栅极电压在同一时间全部导通，某些可以永远不导通。对于具有100nm或更小的栅极和沟道长度的纳米级晶体管而言，RDF是VT的变化的主要决定因素，通常称为西格玛（sigma）VT或σVT，并且随着沟道长度减小，由RDF引起的σVT的量只增大。
图1中示出了可使用常规平面CMOS工艺在体CMOS衬底上制造的改进的晶体管。根据某些所描述的实施例，场效应晶体管（FET）100配置成具有大大减小的短沟道效应以及精确设定阈值电压Vt的能力。FET100包括栅极电极102、源极104、漏极106和定位在沟道110上的栅极电介质108。在工作时，沟道110被深耗尽，与常规晶体管相比，形成可以描述为深耗尽沟道（DDC）的沟道，且部分地通过高度掺杂的屏蔽区域112来设定耗尽深度。虽然沟道110基本上未掺杂，并且如图所示定位在高度掺杂的屏蔽区域112上，但是沟道110可以包括具有不同掺杂剂浓度的简单或复杂分层。这种掺杂的分层可以包括掺杂剂浓度小于屏蔽区域112的阈值电压设定区域111，其可选地定位在沟道110中的栅极电介质108与屏蔽区域112之间。阈值电压设定区域111允许小幅调整FET100的工作阈值电压，同时留下基本上未掺杂的沟道110的体。具体而言，邻近于栅极电介质108的沟道110的部分应当保持不掺杂。此外，穿通抑制区域113形成在屏蔽区域112的下方。类似于阈值电压设定区域111，穿通抑制区域113的掺杂剂浓度小于屏蔽区域112，同时高于轻掺杂阱衬底114的整体掺杂剂浓度。
在工作中，可以将偏置电压122VBS施加到源极104以进一步修改工作阈值电压，并且P+端子126可以在连接部124连接到P阱114以使电路闭合。栅极堆叠包括栅极电极102、栅极接触部118和栅极电介质108。包括栅极间隔部130以使源极和漏极与栅极分离，并且可选的源极/漏极延伸部（SDE）132或“尖端”在栅极间隔部和栅极电介质108下延伸源极和漏极，稍微减小了栅极长度并改进了FET100的电气特性。
在此示例性实施例中，FET100示出为N沟道晶体管，其具有由N型掺杂材料制成的源极和漏极，形成在作为P型掺杂的硅衬底的衬底上，且设置有形成在衬底116上的P阱114。然而，将会理解通过适当改变衬底或掺杂剂材料，可以替代由诸如砷化镓基材料等其它合适的衬底形成的非硅P型半导体晶体管。可以使用常规的掺杂剂注入工艺和材料形成源极104和漏极106，并且源极104和漏极106例如可以包括诸如应力感应的源极/漏极结构、升起和/或凹陷的源极/漏极、不对称掺杂、反掺杂（counter-doped）或晶体结构修改的源极/漏极、或根据LDD（低掺杂漏极）技术的源极/漏极延伸区域的注入掺杂等修改。也可以使用各种其它的技术来修改源极/漏极工作特性，在某些实施例中包括作为补偿掺杂剂的多相（heterogeneous）掺杂剂材料来修改电气特性。
栅极电极102可以由传统材料形成，优选包括但不限于金属、金属合金、金属氮化物、金属硅化物、以及其叠层和其组合物。在某些实施例中，栅极电极102也可以由多晶硅形成，例如包括高掺杂多晶硅和多晶硅锗合金。金属或金属合金可以包括含有铝、钛、钽的那些金属或金属合金、或其氮化物，该氮化物包括含有钛的化合物，诸如氮化钛等。栅极电极102的形成可以包括硅化物法、化学气相沉积法和物理气相沉积法，诸如但不限于蒸镀法和溅射法。通常，栅极电极102的总厚度为从约1至约500纳米。
栅极电介质108可以包括常规电介质材料，诸如氧化物、氮化物和氧氮化物等。或者，栅极电介质108通常可以包括较高介电常数的电介质材料，包括但不限于氧化铪、铪硅酸盐、氧化锆、氧化镧、氧化钛、钡锶钛酸盐和铅锆钛酸盐、金属类电介质材料和其它具有电介质性质的材料。优选的含有铪的氧化物包括HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx等。取决于组合物和可用沉积处理设备，栅极电介质108可以由以下方法形成，诸如热或等离子氧化、氮化法、化学气相沉积法（包括原子层沉积法）和物理气相沉积法等。在某些实施例中，可以使用多层或复合层、叠层和电介质材料的组合混合物。例如，栅极电介质层可以由厚度约0.3与1nm之间的SiO2基绝缘体以及厚度约0.5与4nm之间的氧化铪基绝缘体形成。通常，栅极电介质层的总厚度从约0.5至约5纳米。
沟道区域110形成在栅极电介质108下方和高度掺杂的屏蔽区域112上方。沟道区域110还接触源极104和漏极106，并且在源极104和漏极106之间延伸。优选地，沟道区域包括邻近栅极电介质108或其附近的基本上未掺杂的硅，其掺杂剂浓度小于5×1017个掺杂剂原子/cm3。沟道厚度的范围通常可以从5至50纳米。在某些实施例中，沟道区域110由屏蔽区域上外延生长的纯的或基本上纯的硅形成。
如所公开的，阈值电压设定区域111定位在屏蔽区域112上方，并且通常形成为薄掺杂层。在某些实施例中，德尔塔掺杂、可控原位沉积或原子层沉积可以用于形成基本上平行且关于屏蔽区域112垂直偏移的掺杂剂平面。适当改变掺杂剂浓度、厚度以及与栅极电介质层和屏蔽区域的分离使得可以可控地略微调节工作FET100的阈值电压。在某些实施例中，阈值电压设定区域111掺杂为具有约1×1018个掺杂剂原子/cm3与约1×1019个掺杂剂原子/cm3之间的浓度。阈值电压设定区域111可以由若干不同工艺形成，包括：1）原位外延掺杂，2）外延生长薄硅层后严格可控的掺杂剂注入（例如德尔塔掺杂），3）外延生长薄硅层后原子从屏蔽区域112的掺杂剂扩散，或4）这些工艺的任何组合（例如，外延生长硅后进行掺杂剂注入和从屏蔽层112的掺杂剂扩散这两者）。
高度掺杂的屏蔽区域112的位置通常设定了工作FET100的耗尽区的深度。有利的是，屏蔽区域112（和相关耗尽深度）设定在从与栅极长度（Lg/1）可比较的深度至栅极长度的大的分数（Lg/5）的深度范围内的深度处。在优选实施例中，代表性范围在Lg/3至Lg/1.5之间。具有Lg/2或更大的器件对于极低的功率操作而言是优选的，而在高电压下工作的数字或模拟器件通常可以形成有在Lg/5与Lg/2之间的屏蔽区域。例如，可以形成具有32纳米的栅极长度的晶体管，以使得屏蔽区域在低于约16纳米（Lg/2）的栅极电介质的深度处具有峰值掺杂剂密度，并且电压阈值在8纳米（Lg/4）的深度处设定为峰值掺杂剂密度。
在某些实施例中，屏蔽区域112掺杂为具有约5×1018个掺杂剂原子/cm3与约1×1020个掺杂剂原子/cm3之间的浓度，明显大于未掺杂沟道的掺杂剂浓度，且至少略微大于可选的电压阈值设定区域111的掺杂剂浓度。如将理解的，可以修改确切的掺杂剂浓度和屏蔽区域深度，以改进FET100的期望工作特性，或考虑可用的晶体管制造工艺和工艺条件。
为了帮助控制泄漏，穿通抑制区域113形成在屏蔽区域112的下方。通常，穿通抑制区域113通过直接注入到轻掺杂阱中而形成，但它还可以通过从屏蔽区域向外扩散、原位生长、或其它已知工艺形成。类似于阈值电压设定区域111，穿通抑制区域113的掺杂剂浓度小于屏蔽区域122，通常设定在约1×1018个掺杂剂原子/cm3与约1×1019个掺杂剂原子/cm3之间。此外，穿通抑制区域113的掺杂剂浓度设定为高于阱衬底的整体掺杂剂浓度。如将理解的，可以修改确切的掺杂剂浓度和深度，以改进FET100的期望工作特性，或考虑可用的晶体管制造工艺和工艺条件。
由于可以容易地适应良好研发且长期使用的平面CMOS工艺技术，所以与SOI或finFET晶体管相比，形成这样的FET100相对较为简单。
总体而言，与常规纳米级器件相比，制造上述结构的结构和方法可以使得FET晶体管同时具有低工作电压和低阈值电压。此外，DDC晶体管可以配置为使得阈值电压可以借助于电压体（voltage body）偏置发生器而被静态地设定。在某些实施例中，甚至可以动态地控制阈值电压，这使得可以大幅减小晶体管的泄漏电流（通过设定电压偏置以向上调节VT，从而低泄漏、低速工作），或大幅增大晶体管的泄漏电流（通过向下调节VT，从而高泄漏、高速工作）。最终，提供了制造上述结构的这些结构和方法，以设计具有可以在电路处于工作的同时动态调节的FET器件的集成电路。因此，可以用名义上相同的结构设计集成电路中的晶体管，并可以对其进行控制、调制或编程，使其在响应于不同偏置电压的不同工作电压下工作，或者在响应于不同偏置电压和工作电压的不同工作模式下工作。此外，可以为了电路内的不同应用而在制造后对这些进行配置。
如将理解的，按照物理和功能区域或层，描述了注入的或者存在于半导体的衬底或晶体层中的、用于修改半导体的物理和电气特性的原子的浓度。本领域技术人员可以将这些理解为具有特定浓度平均值的材料的三维体积（mass）。或者，它们可以被理解为具有不同的或空间上变化的浓度的子区域或子层。它们也可以存在为小的掺杂剂原子团、基本上类似的掺杂剂原子的区域等，或其它物理实施例。对基于这些性质的区域的描述并不旨在限制形状、确切位置或取向。它们也并不旨在将这些区域或层限制于所采用的任何特定类型或数量的工艺步骤、任何特定类型或数量的层（例如，组合的或整体的）、半导体沉积、蚀刻技术或生长技术。这些工艺可以包括外延形成的区域或原子层沉积、掺杂注入方法工艺、或特定的纵向或横向掺杂剂分布，其包括线性的、单调增大的、倒退的（retrograde）、或其它合适的空间变化的掺杂剂浓度。为了确保维持期望的掺杂剂浓度，预期了各种掺杂剂抗迁移技术，包括低温处理、碳掺杂、原位掺杂剂沉积，和提前闪蒸（advanced flash）或其它退火技术。所得到的掺杂剂分布可以具有不同掺杂剂浓度的一个或多个区域或层，并且无论工艺如何，通过包括红外光谱、卢瑟福背散射（RBS）、二次离子质谱法（SIMS）或使用不同定性或定量掺杂剂浓度确定方法工艺的其它掺杂剂分析工具的技术，浓度的变化和区域或层如何限定可以是或可以不是可检测的。
为了更好地理解包括通过沉积阈值电压偏移平面形成的、清楚限定的阈值电压设定的一个可能的晶体管结构，图2示出了在源极与漏极之间的中线处获得的且从栅极电介质朝向阱向下延伸的深耗尽晶体管的掺杂剂分布202。以每立方厘米掺杂剂原子的数量为单位测量浓度，向下的深度测量为栅极长度Lg的比值。测量为比值而非以纳米为单位的绝对深度能够更好的在不同节点（例如，45nm、32nm、22nm、15nm）处制造的晶体管之间跨越比较，其中结点通常按照最小栅极长度来限定。
如图2中所示，邻近于栅极电介质层的沟道210的区域基本上没有掺杂剂，直到差不多Lg/4的深度浓度小于5×1017个掺杂剂原子/cm3。阈值电压设定区域211的掺杂剂浓度增大到约3×1018个掺杂剂原子/cm3，并且浓度增大另一数量级到约3×1019个掺杂剂原子/cm3，以形成设定工作晶体管中的耗尽区的底部的屏蔽区域212。在约Lg/1的深度处具有约1×1019个掺杂剂原子/cm3的掺杂剂浓度的穿通抑制区域213是屏蔽区域与轻掺杂阱214之间的中间值。在没有穿通抑制区域的情况下，例如构造为具有30nm栅极长度和1.0伏工作电压的晶体管预期具有明显更大的泄漏。当注入所公开的穿通抑制213时，减小了穿通泄漏，使晶体管功率效率更高，而且能够更好地容忍晶体管结构中的工艺变化而没有穿通失效。
虽然能形成穿通抑制区域和屏蔽区域的深掺杂剂注入相对易于控制，但是形成高精度的阈值电压设定区域更加难得多。从屏蔽区域的掺杂剂迁移可以导致阈值电压设定区域的位置和浓度的大量变化，特别是在使用激活掺杂剂经常遇到的高温工艺时。图3中示出了减小不想要的掺杂剂变化的一个预期实施例。曲线图301以掺杂剂分布示出了预退火掺杂剂注入浓度，其导致了诸如关于图2讨论的掺杂剂分布结构。很明显，单独的掺杂剂注入340和342分别用于形成穿通抑制区域和屏蔽区域。采用由用于形成阈值电压偏移平面344和346的德尔塔掺杂中断两次的纯硅沉积来生长外延硅。这些多个平面非常薄，处于一个或两个原子层厚度的数量级，并且掺杂剂极其集中。一个或多个阈值电压偏移平面可以定位在外延沟道中的任何位置，但优选地定位在具栅极电介质至少Lg/5的距离处。退火之后（post-anneal），阈值电压偏移平面略微扩散，形成关于图2所示的期望的阈值电压设定区域。
可以通过分子束外延、有机金属分解、原子层沉积或其它常规处理技术（包括化学或物理气相沉积）来沉积德尔塔掺杂平面。图4中示意性地示出了一个合适的用于形成定位在基本上未掺杂质的沟道下方和屏蔽区域上方的德尔塔掺杂偏移平面的工艺的实施例。
图4是示出一个示例性工艺的工艺流程图300，用于形成具有适合于不同类型的FET结构（包括模拟和数字晶体管这两者）的德尔塔掺杂偏移平面、穿通抑制区域和屏蔽区域的晶体管。这里示出的工艺在其描述中旨在是一般性的和广泛的，以便不模糊本发明的概念，以下阐述更详细的实施例和示例。这些连同其它工艺步骤允许处理和制造包括DDC结构器件以及旧有器件的集成电路，允许覆盖整个范围的具有改进性能和较低功率的模拟和数字器件的设计。
在步骤302中，工艺开始于阱形成，其可以是根据不同实施例和示例的许多不同工艺中的一个。如303中所示，取决于期望的应用和结果，阱形成可以在STI（浅沟槽隔离）形成304之前或之后。硼（B）、铟（I）或其它P型材料可以用于P型注入，砷（As）或磷（P）和其它N型材料可以用于N型注入。对于PMOS阱注入，可以在从10至80keV的范围内且以从1×1013至8×1013/cm2的浓度来注入P+注入。可以在从5至60keV的范围内且以从1×1013至8×1013/cm2的浓度来注入As+。对NMOS阱注入，可以在从0.5至5keV的范围内且在1×1013至8×1013/cm2的浓度范围内注入硼注入B+。可以在10至60keV的范围内且以1×1014至5×1014/cm2的浓度执行锗注入Ge+。为了减小掺杂剂迁移，可以在0.5至5keV的范围内且以1×1013至8×1013/cm2的浓度执行碳注入C+。阱注入可以包括穿通抑制区域、掺杂剂密度高于穿通抑制区域的屏蔽区域以及阈值电压设定区域的顺序注入和/或外延生长和注入（先前所讨论的这些通常由掺杂剂向屏蔽区域上生长的外延层中的注入或扩散形成）。
在某些实施例中，如302A中所示，阱形成302可以包括Ge/B（N）、As（P）的束线注入，随后是外延（EPI）预清洗工艺，最后是非选择性均厚（blanket）EPI沉积。或者，如302B中所示，阱可以使用B（N）、As（P）的等离子注入，随后是EPI预清洗，最后是非选择性（均厚）EPI沉积而形成。德尔塔掺杂可以发生在EPI生长期间的合适阶段，并且如果需要形成具有期望的VT设定点的期望退火后掺杂剂分布，则可以预期多个EPI生长/德尔塔掺杂阶段。或者，如302C中所示，阱形成可以包括B（N）、As（P）的固体源扩散，随后是EPI预清洗，最后是非选择性（均厚）EPI沉积。或者，如302D中所示，阱形成可以包括B（N）、As（P）的固体源扩散，随后是EPI预清洗，最后是非选择性（均厚）EPI沉积。作为又一种选择，阱形成可以简单地包括阱注入，随后是B（N）、P（P）的原位掺杂选择性EPI。本文所描述的实施例允许具有不同阱结构且根据不同参数的、配置在共同衬底上的多个器件中的任一个。
同样可以在阱形成302之前或之后发生的浅沟槽隔离（STI）形成304可以包括在低于900℃的温度下的低温沟槽牺牲氧化物（TSOX）衬垫。栅极堆叠306可以按照多种不同的方法、由不同的材料形成或构建，并且具有不同的功函数。一个选择是多晶（poly）/SiON栅极堆叠306A。另一选择是先栅极（gate-first）工艺306B，其包括SiON/金属/多晶和/或SiON/多晶，随后是高K/金属栅极。另一选择，后栅极（gate-last）工艺306C包括高K/金属栅极堆叠，其中栅极堆叠可以由“先高K后金属栅极”的流程或“后高K后金属栅极”的流程形成。再一选择，306D是包括可调谐范围的功函数的金属栅极，其取决于器件构造，N（NMOS）/P（PMOS）/N（PMOS）/P（NMOS）/中间带隙（Mid-gap）或两者之间的任何地方。在一个示例中，N具有4.05V±200mV的功函数（WF），P具有5.01V±200mV的WF。
接着，在步骤308中，可以注入源极/漏极尖端，或可选地可以取决于应用而不注入。尖端的尺寸可以根据需要而变化，并且将部分地取决于是否使用栅极间隔部（SPCR）。在一个选择中，在308A中可以没有尖端注入。接着，在可选步骤310和312中，PMOS或NMOS EPI层可以形成在源极和漏极区域中，作为用于创建应变沟道的性能增强部。对于后栅极的栅极堆叠选择而言，在步骤314中，形成后栅极模块。这仅可以针对后栅极工艺314A。
可以预期支持多种晶体管类型的管芯（包括具有和不具有穿通抑制的管芯、具有不同阈值电压的管芯、具有和不具有部分地由德尔塔掺杂阈值电压结构设定的阈值电压、以及具有和不具有静态或动态偏置的管芯）。片上系统（SOC）、先进的微处理器、射频、存储器和其它具有一个或多个数字和模拟晶体管配置的管芯可以并入到使用本文所描述的方法的器件中。根据本文所讨论的方法和工艺，可以使用体CMOS在硅上生产出具有DDC和/或具有或不具有穿通抑制的晶体管器件和结构的多种组合的系统。在不同实施例中，管芯可以分割成动态偏置结构、静态偏置结构或无偏置结构单独地或以某种组合存在的一个或多个区域。在动态偏置部分中，例如，可动态调节的器件可以与高和低VT器件和可能的DDC逻辑器件一起存在。
虽然已经描述了特定示例性实施例并且在附图中示出了这些实施例，但是应当理解这些实施例仅仅是例示性的，而并非限制广泛的发明，还应当理解由于本领域技术人员可以做出各种其它修改，所以本发明并不限于所示和所述的特定结构和配置。因此，本说明书和附图应被视为说明性的而非限制性的意义。

Claims (10)

1.一种场效应晶体管结构，包括：
阱，掺杂为具有第一掺杂剂浓度；
屏蔽层，与所述阱接触，并且具有大于5×1018个掺杂剂原子/cm3的第二掺杂剂浓度；以及
均厚层，包括外延生长在所述屏蔽层上的不同掺杂的沟道层和阈值电压设定层，其中所述阈值电压设定层至少部分地通过设置阈值电压偏移平面形成，且所述阈值电压偏移平面定位在屏蔽区域上方且与所述屏蔽区域分离。
2.根据权利要求1所述的场效应晶体管结构，其中：通过德尔塔掺杂来沉积所述电压阈值偏移平面。
3.根据权利要求1所述的场效应晶体管结构，其中：所述电压阈值偏移平面定位在距所述屏蔽区域约3纳米至约10纳米之间。
4.根据权利要求1所述的场效应晶体管结构，还包括多个阈值电压偏移平面。
5.根据权利要求1所述的场效应晶体管结构，其中：所述沟道层邻近于栅极电介质掺杂为具有小于约5×1017个掺杂剂原子/cm3的密度。
6.一种用于形成场效应晶体管结构的方法，包括：
形成掺杂为具有第一掺杂剂浓度的阱；
将屏蔽区域注入到所述阱中，所述屏蔽区域的掺杂剂浓度大于5×1018个掺杂剂原子/cm3；
在所述屏蔽区域的顶部上生长外延均厚层；
在所述外延均厚层中形成至少一个阈值电压偏移平面；以及
在所述外延均厚层中形成沟道层。
7.根据权利要求6所述的方法，其中：所述沟道层掺杂为具有小于约5×1017个掺杂剂原子/cm3的密度。
8.根据权利要求6所述的方法，其中：使用德尔塔掺杂来执行形成至少一个阈值电压偏移平面。
9.根据权利要求6所述的方法，其中：形成至少一个阈值电压偏移平面的步骤还包括：通过分子束外延、有机金属分解、原子层沉积、物理气相沉积和/或化学气相沉积中的至少一个所进行的德尔塔掺杂。
10.根据权利要求6所述的场效应晶体管结构，其中：所述电压阈值偏移平面定位在距所述屏蔽区域约3纳米至约10纳米之间。
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