CN103050391A - Semiconductor substrate breaking method - Google Patents
Semiconductor substrate breaking method Download PDFInfo
- Publication number
- CN103050391A CN103050391A CN2012102867835A CN201210286783A CN103050391A CN 103050391 A CN103050391 A CN 103050391A CN 2012102867835 A CN2012102867835 A CN 2012102867835A CN 201210286783 A CN201210286783 A CN 201210286783A CN 103050391 A CN103050391 A CN 103050391A
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- Prior art keywords
- semiconductor substrate
- delineation
- groove
- silicon substrate
- face
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Abstract
The invention relates to a semiconductor substrate breaking method, protrusion or damage of a breaking surface is minimized when the semiconductor substrate is broken in a grid manner by carving or cutting. when the semiconductor substrate (10) is carved and broken to chips, a V-shaped groove (12) is formed below a predetermined line, a carving line (14) is formed by carving along the predetermined line, a breaking device is used for breaking, thereby protrusion or damage on the back surface of the semiconductor chip is prevented, and the verticality of the cross section is enhanced.
Description
Technical field
The present invention relates to a kind of disconnect method that semiconductor substrate is disconnected.
Background technology
, be broken as in the situation of both chips of sizing being clathrate with semiconductor substrate, such as silicon substrate, SiC substrate etc. in the past, considered usually that utilizing slicing machine to divide was broken into clathrate.Yet, when die size hour etc., depending on purposes, sometimes utilize slicing machine not good.In this case, be to utilize the scoring device shown in patent documentation 1 grade, form the delineation line at silicon substrate in advance.Afterwards, can utilize disconnecting apparatus to disconnect and separated along the delineation line.Silicon substrate is made as (110) face by the crystal orientation that will cut off face, can utilize delineation and disconnects and easily cut off at short notice.
The look-ahead technique document
Patent documentation
Patent documentation 1: Japanese Patent Laid-Open 2011-148098 communique
Summary of the invention
[inventing problem to be solved]
Fig. 1 (a), (b) are expressed as follows order, utilize described method, use scoring device that scribe wheel 102 is crimped on silicon substrate 101 and rotation, and form delineation lines 103 at silicon substrate 101, then, disconnect along delineation line 103.Yet, there are the following problems in the situation of utilizing the method to disconnect, shown in Fig. 1 (c), in the lower end of splitting surface 104, be the back part of silicon substrate 101, the easily projection 105 of the irregular tilted direction of generation, breakages 106 etc. on the direction of riving can be uneven in the most situation of die size.Especially in the less situation of die size, also exist irregular projection, damaged impact larger, cause such problem that hinders and have in the semiconductor fabrication processes such as conveyance step after the disconnection.
The present invention is conceived to this in the past problem points, and when technical problem was delineation and disconnects semiconductor substrate, substrate back can not produce irregular projection, breakage, can not cause the manufacturing step after disconnecting and carry out disjunction with hindering.
[technological means of dealing with problems]
In order to solve described problem, the disconnect method of semiconductor substrate of the present invention is to form the delineation line at semiconductor substrate surface, along this delineation line described semiconductor substrate is disconnected, the back side at described semiconductor substrate forms groove along the delineation preset lines, surface at described semiconductor substrate forms the delineation line along the delineation preset lines, and along described delineation line described semiconductor substrate is disconnected.
In this, the groove that forms on the described semiconductor substrate can be that the cross section is the groove of V font.
In this, the groove that forms on the described semiconductor substrate can be that the cross section is the groove of U font.
In this, described semiconductor substrate can be silicon substrate, and the described crystal orientation that cuts off face can be (110) face.
[invention effect]
According to the present invention with this feature, be pre-formed groove at the back side of semiconductor substrate along the delineation preset lines, it is damaged that the rightabout of delineation face is difficult for producing irregular inclination after therefore disconnecting, and the linearity of separation property, vertical cross-section improves.In addition, owing to projection, breakage tail off, the size inequality of die size diminishes, and the workability that therefore can obtain in the rear steps such as conveyance improves so outstanding effect.
Description of drawings
Fig. 1 represents to delineate and the figure of the processing during the disjunction silicon substrate in the past.
Fig. 2 is the figure of the front silicon substrate of the disjunction of expression embodiments of the present invention.
Fig. 3 is the figure of step of disjunction of the silicon substrate of expression embodiments of the present invention.
Fig. 4 is the semiconductor chip of minute having no progeny of expression embodiment and the projection of side thereof, damaged figure.
Fig. 5 is the chart of an example of maximum, minimum value and mean value of the projection of expression embodiments of the invention and comparative example.
Fig. 6 is the chart of variation of the projection inequality of expression embodiments of the invention and comparative example.
[explanation of symbol]
Embodiment
Fig. 2 is the figure of the upper surface of the silicon substrate before utilizing the disconnect method of embodiments of the present invention to disconnect.Fig. 3 (a) is the end view of silicon substrate 10.This silicon substrate 10 has at foursquare part 11 places of central authorities and is a plurality of functional areas that clathrate is forming set semiconductor circuit pattern, as shown in the figure, along the delineation preset lines each functional area is the shaped like chips disjunction.Among Fig. 3 (a), the crystal orientation of silicon substrate 10 are surfaces for (100) face, the crystal orientation that cuts off face (xz face and yz face) be (110) face.And, shown in the sectional view of Fig. 3 (b), the line parallel with the y axle of the upper face center in this cross section is made as delineation gives alignment, utilize slicing machine to form the groove 12 of V font at the back side of substrate 10 along this line.At this moment, as shown in Figure 2, not only on the y direction of principal axis, on the x direction of principal axis, also form successively parallel a plurality of grooves 12.
Then, shown in Fig. 3 (c), from the surface of silicon substrate 10, utilize the scoring device crimping and rotate scribe wheel 13 and formation delineation line 14.In this case, at x direction of principal axis shown in Figure 2, also form successively parallel a plurality of delineation lines 14 on the y direction of principal axis.Although also depend on the factors such as kind of substrate, scribe wheel, the delineation load for example is preferably 1～5N during delineation, and delineation speed preferably is made as 50～300mm/ about second.In the situation of the thinner thickness of the situation that the angle of the point of a knife of scribe wheel is less, silicon substrate 10, the delineation load also needs to diminish, and for example considers that delineating load when 100～120 ° of point of a knife angles is 1～2N.For example consider that the delineation load is 2～4N when the point of a knife angle is 130～150 °.
Next, shown in Fig. 3 (d), utilize disconnecting apparatus to disconnect along this delineation line 14.During disconnection, attach bonding sheet 15 at the back side of silicon substrate 10, will utilize support portion 16a, 16b to keep delineation line about 14 after silicon substrate 10 counter-rotatings, and disconnect from top by bottom knife 17.This disconnection for example can utilize the disconnecting apparatus of Japanese Patent Laid-Open 2010-173251 number record.So, separation property, separation quality improvement, the linearity of die size improves.
Also having, is to form groove at the back side of silicon substrate in the present embodiment, then begins to form the delineation line from the surface, but also can form first the delineation line on the surface, then forms groove overleaf and disconnects.
And the groove that is pre-formed in the present embodiment at the silicon substrate back side is the V font, but also can form the groove of U font, can also be that only bottom land is the groove of V font.
In addition, present embodiment is take silicon substrate as object, but the present invention also can be applied to other semiconductor substrates such as SiC substrate.The present invention is especially effective for the less semiconductor substrate of die size, die size substrate below for example 5mm.
[embodiment]
(embodiment 1)
Among the embodiment 1, as the substrate of wanting disjunction, utilize the silicon substrate of 0.4mm thickness.The surface of this silicon substrate is that crystal orientation is (100) face, and it is the groove of the V font of 50 μ m that the back side of delineation preset lines forms the degree of depth.Then, use external diameter to delineate as the scribe wheel of the common point of a knife of 145 ° of 2mm φ, point of a knife angle.The delineation load is 2～3N, and delineation speed is 100mm/s.Then, disconnect, divide the foursquare a plurality of chips that are broken into 1.5mm * 1.5mm.
For 20 sample chip that obtain after disconnecting by this way, measure projection, breakage.This mensuration is for dividing the silicon substrate chip 20 of having no progeny shown in Fig. 4 (a), beginning to measure projection, the breakage of following its two ends disjunction from the four directions.It is the groove that is pre-formed overleaf the V font among the embodiment 1, therefore do not consider the slot part of below, shown in Fig. 4 (b) to from cutting off the outstanding part a of face, cut off the face inside and produce damaged part b and measure, and with its absolute value as evaluation object.Like this, shown in Fig. 4 (b)～(d), will be for 1 semiconductor chip, the lower end of each face that cuts off of two about observing from 4 directions, be a, b, c, d, e, f, g, these 8 of h cut off the projection of face, damaged absolute value is measured as the cross section linearity.Then, calculate mean value, peak, the minimum of measurement result of the chip of 20 samples.This moment, the minimum of cross section up rightness was 3 μ m, and peak is 29 μ m, and mean value is 16.4 μ m.And uneven 3 σ are 17.9 μ m.
(embodiment 2)
(embodiment 3)
Embodiment 3 is made as 2.0mm with die size, and groove shape is made as the V font.Other aspects are identical with embodiment 1, also 20 sample chip measured in this case.The minimum of the cross section up rightness of 20 sample chip that determine is 4 μ m, and peak is 28 μ m, and mean value is 11.1 μ m.And uneven 3 σ are 14.7 μ m.
(comparative example 1)
Comparative example 1 is for the silicon substrate identical with embodiment 1, do not form groove and carries out delineation and the disconnection identical with embodiment 1.Also 20 sample chip are measured in this case.At this moment, the minimum of the cross section up rightness of 20 sample chip is 15 μ m, and peak is 60 μ m, and mean value is 30.9 μ m.And described uneven 3 σ are 28.4 μ m.
(comparative example 2)
Comparative example 2 is for the silicon substrate identical with embodiment 3, does not form groove and carries out delineation and the disconnection identical with embodiment 3.Also 20 sample chip are measured in this case.The minimum of the cross section up rightness of 20 sample chip that determine is that 10 μ m, peak are that 42 μ m, mean value are 24.8 μ m.And described uneven 3 σ are 22.5 μ m.
Described embodiment 1～3, comparative example 1,2 as a result summary sheet are shown among Fig. 5 and Fig. 6.Also have, the dot of Fig. 5 represents mean value.Shown in these embodiment and comparative example, arranging overleaf in the situation of groove of V font or U font, can improve the cross section up rightness.And, can obtain to reduce the effect of uneven 3 σ.
[industrial utilizability]
The present invention is in delineation and disconnect semiconductor substrate and minute be broken in the cancellate situation, and is by in advance applying groove processing and can improve the cross section up rightness, useful for the manufacturing step of semiconductor substrate.
Claims (4)
1. the disconnect method of a semiconductor substrate forms the delineation line on the surface of semiconductor substrate, along this delineation line described semiconductor substrate is disconnected,
The back side at described semiconductor substrate forms groove along the delineation preset lines,
Surface at described semiconductor substrate forms the delineation line along the delineation preset lines,
Along described delineation line described semiconductor substrate is disconnected.
2. the disconnect method of semiconductor substrate according to claim 1, the groove that wherein is formed on the described semiconductor substrate is that the cross section is the groove of V font.
3. the disconnect method of semiconductor substrate according to claim 1, the groove that wherein is formed on the described semiconductor substrate is that the cross section is the groove of U font.
4. the disconnect method of semiconductor substrate according to claim 1, wherein said semiconductor substrate is silicon substrate, the described crystal orientation that cuts off face is (110) face.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011225684A JP2013089622A (en) | 2011-10-13 | 2011-10-13 | Breaking method of semiconductor substrate |
| JP2011-225684 | 2011-10-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103050391A true CN103050391A (en) | 2013-04-17 |
| CN103050391B CN103050391B (en) | 2016-12-21 |
Family
ID=48062992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210286783.5A Expired - Fee Related CN103050391B (en) | 2011-10-13 | 2012-08-13 | The disconnection method of semiconductor substrate |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2013089622A (en) |
| KR (1) | KR20130040120A (en) |
| CN (1) | CN103050391B (en) |
| TW (1) | TW201316392A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952793A (en) * | 2014-03-28 | 2015-09-30 | 三星钻石工业股份有限公司 | Breaking method for silicon substrate |
| CN106079116A (en) * | 2015-04-30 | 2016-11-09 | 三星钻石工业股份有限公司 | The disconnection method of brittle substrate |
| CN106079115A (en) * | 2015-04-30 | 2016-11-09 | 三星钻石工业股份有限公司 | The dividing method of adhesive substrates and segmenting device |
| CN109455919A (en) * | 2014-03-31 | 2019-03-12 | 三星钻石工业股份有限公司 | The method for dividing of brittle material substrate |
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|---|---|---|---|---|
| JP6140030B2 (en) * | 2013-08-21 | 2017-05-31 | 三星ダイヤモンド工業株式会社 | Method for dividing wafer laminate for image sensor |
| JP6185792B2 (en) * | 2013-08-29 | 2017-08-23 | 三星ダイヤモンド工業株式会社 | Semiconductor wafer cutting method |
| JP6115438B2 (en) * | 2013-10-16 | 2017-04-19 | 三星ダイヤモンド工業株式会社 | Breaking device and cutting method |
| JP6268917B2 (en) * | 2013-10-25 | 2018-01-31 | 三星ダイヤモンド工業株式会社 | Break device |
| JP6323173B2 (en) * | 2014-05-29 | 2018-05-16 | Tdk株式会社 | Electronic device separation method |
| JP6365056B2 (en) * | 2014-07-22 | 2018-08-01 | 三星ダイヤモンド工業株式会社 | Method for dividing bonded substrate and break blade |
| JP5913489B2 (en) * | 2014-09-03 | 2016-04-27 | 三星ダイヤモンド工業株式会社 | Scribing line forming and cutting method and scribing line forming and cutting apparatus for wafer stack for image sensor |
| JP6005708B2 (en) * | 2014-10-23 | 2016-10-12 | 三星ダイヤモンド工業株式会社 | Method and apparatus for dividing wafer laminate for image sensor |
| JP2017204549A (en) * | 2016-05-11 | 2017-11-16 | サムコ株式会社 | Semiconductor substrate and manufacturing method of the same |
| JPWO2019082724A1 (en) * | 2017-10-27 | 2020-11-12 | 三星ダイヤモンド工業株式会社 | How to divide a substrate with a metal film |
| WO2023058509A1 (en) * | 2021-10-08 | 2023-04-13 | 三星ダイヤモンド工業株式会社 | Sic semiconductor device |
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| JPH10125958A (en) * | 1997-10-20 | 1998-05-15 | Nichia Chem Ind Ltd | Manufacture of gallium nitride compound semiconductor chip |
| JPH11354841A (en) * | 1998-06-04 | 1999-12-24 | Rohm Co Ltd | Fabrication of semiconductor light emitting element |
| JP2001284290A (en) * | 2000-03-31 | 2001-10-12 | Toyoda Gosei Co Ltd | Chip division method for semiconductor wafer |
| TWI262553B (en) * | 2003-09-26 | 2006-09-21 | Advanced Semiconductor Eng | Wafer dicing method |
| JP2010173251A (en) * | 2009-01-30 | 2010-08-12 | Mitsuboshi Diamond Industrial Co Ltd | Substrate breaking device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006179790A (en) * | 2004-12-24 | 2006-07-06 | Canon Inc | Laser cutting method and member that can be cut by it |
| EP2292398A4 (en) * | 2008-06-05 | 2017-05-31 | Mitsuboshi Diamond Industrial Co., Ltd. | Scribing wheel and method for scribing brittle material substrate |
| JP5281542B2 (en) * | 2009-10-29 | 2013-09-04 | 三星ダイヤモンド工業株式会社 | Chip holder unit |
| JP5281544B2 (en) * | 2009-10-30 | 2013-09-04 | 三星ダイヤモンド工業株式会社 | Break device |
| JP2011222623A (en) * | 2010-04-06 | 2011-11-04 | Disco Abrasive Syst Ltd | Method for processing optical device wafer |
-
2011
- 2011-10-13 JP JP2011225684A patent/JP2013089622A/en active Pending
-
2012
- 2012-07-13 KR KR1020120076492A patent/KR20130040120A/en active Search and Examination
- 2012-07-31 TW TW101127620A patent/TW201316392A/en unknown
- 2012-08-13 CN CN201210286783.5A patent/CN103050391B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10125958A (en) * | 1997-10-20 | 1998-05-15 | Nichia Chem Ind Ltd | Manufacture of gallium nitride compound semiconductor chip |
| JPH11354841A (en) * | 1998-06-04 | 1999-12-24 | Rohm Co Ltd | Fabrication of semiconductor light emitting element |
| JP2001284290A (en) * | 2000-03-31 | 2001-10-12 | Toyoda Gosei Co Ltd | Chip division method for semiconductor wafer |
| TWI262553B (en) * | 2003-09-26 | 2006-09-21 | Advanced Semiconductor Eng | Wafer dicing method |
| JP2010173251A (en) * | 2009-01-30 | 2010-08-12 | Mitsuboshi Diamond Industrial Co Ltd | Substrate breaking device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952793A (en) * | 2014-03-28 | 2015-09-30 | 三星钻石工业股份有限公司 | Breaking method for silicon substrate |
| CN109455919A (en) * | 2014-03-31 | 2019-03-12 | 三星钻石工业股份有限公司 | The method for dividing of brittle material substrate |
| CN109455919B (en) * | 2014-03-31 | 2022-03-08 | 三星钻石工业股份有限公司 | Method for dividing brittle material substrate |
| CN106079116A (en) * | 2015-04-30 | 2016-11-09 | 三星钻石工业股份有限公司 | The disconnection method of brittle substrate |
| CN106079115A (en) * | 2015-04-30 | 2016-11-09 | 三星钻石工业股份有限公司 | The dividing method of adhesive substrates and segmenting device |
| CN106079116B (en) * | 2015-04-30 | 2020-07-28 | 三星钻石工业股份有限公司 | Method for breaking brittle material substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2013089622A (en) | 2013-05-13 |
| TW201316392A (en) | 2013-04-16 |
| CN103050391B (en) | 2016-12-21 |
| KR20130040120A (en) | 2013-04-23 |
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Granted publication date: 20161221 Termination date: 20190813 |