CN103035672A - Compound semiconductor device and method of manufacturing the same - Google Patents
Compound semiconductor device and method of manufacturing the same Download PDFInfo
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- CN103035672A CN103035672A CN2012103135800A CN201210313580A CN103035672A CN 103035672 A CN103035672 A CN 103035672A CN 2012103135800 A CN2012103135800 A CN 2012103135800A CN 201210313580 A CN201210313580 A CN 201210313580A CN 103035672 A CN103035672 A CN 103035672A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 150000001875 compounds Chemical class 0.000 title claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 title claims description 19
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- 230000000903 blocking effect Effects 0.000 claims description 58
- 238000000034 method Methods 0.000 claims description 36
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- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 5
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 5
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- 238000004804 winding Methods 0.000 description 4
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- 238000000137 annealing Methods 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
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- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
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- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
- H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a hole barrier layer formed between the electron supply layer and the p-type semiconductor layer, a band gap of the hole barrier layer being larger than that of the electron supply layer.
Description
Technical field
Embodiment discussed in this article relates to compound semiconductor device and manufacture method thereof.
Background technology
In recent years, have the electronic device (compound semiconductor device) that forms successively GaN layer and AlGaN layer above substrate and occurred flourishly, wherein the GaN layer is as the electron channel layer.One of known compound semiconductor device is GaN based high electron mobility transistor (HEMT).The high density two-dimensional gas (2DEG) that the GaN based hemts utilizes the heterojunction boundary place between AlGaN and GaN to generate dexterously.
The band gap of GaN is 3.4eV, the band gap (1.4eV) of its band gap greater than Si (1.1eV) and GaAs.In other words, GaN has large disruptive field intensity.GaN also has large saturated electrons speed.Therefore, GaN is a kind of material with fine prospect for can under high pressure operating and can produce the compound semiconductor device of large output.Therefore, the GaN based hemts is expected to for the high efficiency switch device of motor vehicle and high-breakdown-voltage power device etc.
Most GaN based hemts utilizes highdensity two-dimensional gas to carry out the normal open operation.In brief, even when gate voltage disconnects, electric current still can flow.It is former because there are many electronics in raceway groove.On the other hand, consider failure safe, the normal off operation is important for the GaN based hemts that is used for the high-breakdown-voltage power device.
Therefore, the research of various technology related to the GaN based hemts that realization can be carried out the normal off operation.For example, there is following structure: between gate electrode and active region, be formed with the p-type GaN layer that contains just like p-type impurity such as Mg.
Yet, be difficult to obtain good conductive characteristic (such as, conducting resistance) and service speed.
[patent document 1] Japanese Laid-Open Patent Publication 2010-258313
Summary of the invention
An object of the present invention is to provide a kind of compound semiconductor device that can when obtaining the good conductive characteristic, realize the normal off operation with and manufacture method.
According to aspect of the present embodiment, compound semiconductor device comprises: substrate; Be formed on electron channel layer and electron supply layer on the substrate; Be formed on the electron supply layer or gate electrode, source electrode and the drain electrode of top; Be formed on the p-type semiconductor layer between electron supply layer and the gate electrode; And being formed on hole blocking layer between electron supply layer and the p-type semiconductor layer, the band gap of hole blocking layer is greater than the band gap of electron supply layer.
According to the present embodiment on the other hand, the method for manufacturing compound semiconductor device comprises: form electron channel layer and electron supply layer on substrate; On the electron supply layer or above form gate electrode, source electrode and drain electrode; Before forming gate electrode, form the p-type semiconductor layer between electron supply layer and gate electrode; And before forming the p-type semiconductor layer, forming the hole blocking layer between electron supply layer and p-type semiconductor layer, the band gap of hole blocking layer is greater than the band gap of electron supply layer.
Description of drawings
Fig. 1 is the cross-sectional view that illustrates according to the structure of the compound semiconductor device of the first embodiment;
Fig. 2 is the figure of band structure that the gate electrode below of GaN based hemts is shown;
Fig. 3 A is the cross-sectional view that the structure of a reference example is shown;
Fig. 3 B is the figure that the band structure of described reference example is shown;
Fig. 4 is the figure that operating time and drain electrode electric current Relations Among are shown;
Fig. 5 A to Fig. 5 I illustrates manufacturing successively according to the cross-sectional view of the method for the compound semiconductor device of the first embodiment;
Fig. 6 is the figure that etching process is shown;
Fig. 7 is the cross-sectional view that illustrates according to the structure of the compound semiconductor device of the second embodiment;
Fig. 8 is the cross-sectional view that illustrates according to the structure of the compound semiconductor device of the 3rd embodiment;
Fig. 9 A to Fig. 9 B illustrates manufacturing successively according to the cross-sectional view of the method for the compound semiconductor device of the 4th embodiment;
Figure 10 is the figure that illustrates according to the discrete package part of the 5th embodiment;
Figure 11 is the wiring diagram that illustrates according to power factor correcting (PFC) circuit of the 6th embodiment;
Figure 12 is the wiring diagram that illustrates according to the supply unit of the 7th embodiment;
Figure 13 is the wiring diagram that illustrates according to the high-frequency amplifier of the 8th embodiment;
Embodiment
The present patent application people has studied the reason that is difficult to obtain in the prior art good conductive characteristic (such as conducting resistance) and service speed when being provided with p-type GaN why widely.Found that: the hole in the p-type semiconductor layer is diffused into the raceway groove side of 2DEG; The reverse movement of hole and electronics; And the dark part (bottom) that is positioned under the electrode of source that the hole is accumulated in channel layer is located.The hole of accumulation has been improved the electromotive force of raceway groove and has been increased the conducting resistance of antagonism mobile electronics in raceway groove.In addition, because the hole accumulation has changed current path, so the impact that service speed is changed.Therefore, understand based on these, the inventor produces the idea that the barrier layer that suppresses the hole diffusion is provided.
Below with reference to the accompanying drawings embodiment is described in detail.
(the first embodiment)
The first embodiment will be described.Fig. 1 is the cross-sectional view that illustrates according to the structure of the GaN based hemts (compound semiconductor device) of the first embodiment.
In the first embodiment, as shown in Figure 1, on substrate 1 (for example Si substrate), form compound semiconductor stacked structure 7.Compound semiconductor stacked structure 7 comprises resilient coating 2, electron channel layer 3, wall 4, electron supply layer 5 and hole blocking layer 6.For example, resilient coating 2 can be about thick AlN layer and/or the AlGaN layer of 10nm to 2000nm for example.For example, electron channel layer 3 can be the thick i-GaN layer of about 1000nm to 3000nm (not using intentionally impurity to mix).For example, wall 4 can be the thick i-Al of about 5nm
0.2Ga
0.8N layer (not using intentionally impurity to mix).For example, electron supply layer 5 can be the thick N-shaped AlGaN (n-Al of about 30nm
0.2Ga
0.8N) layer.For example, electron supply layer 5 can be doped with about 5 * 10
18/ cm
3The Si as N-shaped impurity.For example, hole blocking layer 6 can be the thick AlN layer of about 2nm.
In compound semiconductor stacked structure 7, be formed with the element separation zone 20 that limits element area.In element area, in hole blocking layer 6, be formed with recess 10s and 10d.In recess 10s, form active electrode 11s, and in recess 10d, be formed with drain electrode 11d.Recess 10s and 10d can omit, and hole blocking layer 6 can be retained between electron supply layer 5 and source electrode 11s and the drain electrode 11d.When source electrode 11s directly contacts with electron supply layer 5 with drain electrode 11d, the lower and better performances of contact resistance.In plane graph, the zone of the hole blocking layer 6 between source electrode 11s and drain electrode 11d is formed with cap rock 8.Cap rock 8 can be such as the thick p-type GaN of about 50nm (p-GaN) layer.Cap rock 8 can use such as about 5 * 10
19/ cm
3The Mg as the p-type dopant mix.Cap rock 8 is examples of p-type semiconductor layer.
Form dielectric film 12 with covering source electrode 11s and drain electrode 11d above hole blocking layer 6.In dielectric film 12, form opening 13g to expose cap rock 8, in opening 13g, be formed with gate electrode 11g.Form dielectric film 14 with the covering grid electrode 11g above dielectric film 12.Although be used for the not particularly restriction of material of dielectric film 12 and 14, for example can use the Si nitride film. Dielectric film 12 and 14 is examples of terminated film (termination film).
Fig. 2 is the band structure figure of gate electrode below that is illustrated in the GaN based hemts of structure like this; Fig. 3 B is the figure that is illustrated in the band structure of the reference example shown in Fig. 3 A.From Fig. 2 to Fig. 3 A obviously as seen, when the gate electrode 11g in reference example (not comprising hole blocking layer 6) applied voltage, the hole was easy to upwards be diffused into raceway groove.On the other hand, in the present embodiment, because be provided with hole blocking layer 6, even apply voltage for gate electrode 11g, the hole also can be diffused into from p-type cap rock 8 raceway groove of 2DEG hardly.Therefore, can suppress because spread in the hole, the conducting resistance that causes increases and current path changes, and can obtain good conductive characteristic.As shown in Figure 4, for example in the present embodiment, can obtain stable drain electrode electric current I d, and in reference example, drain electrode electric current I d reduces in institute's elapsed time.
When the lattice constant of the nitride-based semiconductor of hole blocking layer 6 was supplied with 5 lattice constant less than electronics, the density of the 2DEG the electron channel layer 3 near was higher and conducting resistance is lower.
Next, with the method for explanation manufacturing according to the GaN based hemts (compound semiconductor device) of the first embodiment.Fig. 5 A to Fig. 5 I shows manufacturing successively according to the cross-sectional view of the method for the GaN based hemts (compound semiconductor device) of the first embodiment;
At first, shown in Fig. 5 A, can be by above substrate 1, forming resilient coating 2, electron channel layer 3, wall 4 and electron supply layer 5 such as crystal growth techniques such as metal organic vapor (MOVPE) and molecular beam epitaxies (MBE).Forming in the technique of AlN layer, AlGaN layer and GaN layer by MOVPE, can use trimethyl aluminium (TMA) gas as the Al source, as trimethyl gallium (TMG) gas in Ga source with as the mist of the ammonia in N source.In technique, ON/OFF and the flow thereof of the supply of trimethyl aluminium gas and trimethyl gallium gas is set suitably according to the composition of compound semiconductor to be grown.Flow for the shared ammonia of all compound semiconductor layers can be set to about 100ccm to 10LM.Growth pressure can be adjusted to about 50 holders to 300 holders, and growth temperature can be adjusted to approximately as 1000 ℃ to 1200 ℃.In the technique of growing n-type compound semiconductor layer, for example, can be by comprising the SiH of Si
4Gas adds in the mist with predetermined flow Si is doped in the compound semiconductor layer.The dosage of Si is adjusted to about 1 * 10
18/ cm
3To 1 * 10
20/ cm
3(for example, 5 * 10
18/ cm
3Or 5 * 10
18/ cm
3About).
Next, shown in Fig. 5 B, for example, can be by above electron supply layer 5, forming hole blocking layer 6 such as crystal growth techniques such as MOVPE and MBE.Hole blocking layer 6 can form continuously with resilient coating 2, electron channel layer 3, separator 4 and electron supply layer 5.In this case, in order to form hole blocking layer 6, can stop TMG gas and SiH
4The supply of gas and can continue TMA gas and NH
3The supply of gas.Thereby can obtain compound semiconductor stacked structure 7.
After this, shown in Fig. 5 C, for example, can be by above hole blocking layer 6, forming cap rock 8 such as crystal growth techniques such as MOVPE and MBE.Cap rock 8 can form continuously with resilient coating 2, electron channel layer 3, separator 4, electron supply layer 5 and hole blocking layer 6.For example, the dosage of the Mg of cap rock 8 is adjusted to about 5 * 10
19/ cm
3To 1 * 10
20/ cm
3(for example 5 * 10
19/ cm
3Or 5 * 10
19/ cm
3About).Then anneal to activate Mg.
Next, shown in Fig. 5 D, in compound semiconductor stacked structure 7 and cap rock 8, form the element separation zone 20 that limits element area.In the process of forming element area of isolation 20, for example form photoetching agent patterns optionally exposing the zone in element separation to be formed zone 20 at cap rock 8, and by coming ion such as Ar ion with photoetching agent pattern as mask.Perhaps, can be with chlorine-containing gas by coming etching cap rock 8 and compound semiconductor stacked structure 7 as etching mask with dry etching with photoetching agent pattern.
After this, shown in Fig. 5 E, etching cap rock 8 is to be retained in it in zone of gate electrode to be formed.In the process of patterning cap rock 8, for example, above cap rock 8, form photoetching agent pattern to cover the zone of cap rock 8 to be kept, then with chlorine-containing gas by coming etching cap rock 8 as etching mask with dry etching with photoetching agent pattern.
Then, shown in Fig. 5 F, recess 10s and recess 10d are formed in the hole blocking layer 6 in the element area.In the process that forms recess 10s and 10d, for example, above compound semiconductor stacked structure 7 and cap rock 8, form photoetching agent pattern exposing the zone of recess 10s to be formed and 10d, and with chloride gas by coming etched cavity barrier layer 6 as etching mask with dry etching with photoetching agent pattern.Next, in recess 10s, form source electrode 11s, and in recess 10d, form drain electrode 11d.For example, can form source electrode 11s and drain electrode 11d by stripping technology.More specifically, form photoetching agent pattern to expose the zone of source electrode 11s to be formed and drain electrode 11d, for example, under making with photoresist as the situation of growth mask, form metal film by evaporation process on whole surface, then photoetching agent pattern is removed with the metal film part that is deposited thereon.In the technique that forms metal film, for example, can form the thick Ta film of about 20nm, then can form the thick Al film of about 200nm.Then as in blanket of nitrogen, under 400 ℃ to 1000 ℃ (for example 550 ℃), metal film is annealed, thus guarantee ohm property.
Then shown in Fig. 5 G, form dielectric film 12 on whole surface.Preferably, form dielectric film 12 by ald (ALD), plasma auxiliary chemical vapor deposition (CVD) or sputter.
Next, shown in Fig. 5 H, in dielectric film 12, form opening 13g and expose cap rock 8 with the position between source electrode 11s and drain electrode 11d in plane graph.
Next, shown in Fig. 5 I, in opening 13g, form gate electrode 11g.Can be by form gate electrode 11g such as stripping technology.More specifically, form photoetching agent pattern to expose the zone of gate electrode 11g to be formed, for example utilize photoetching agent pattern as the situation of growth mask under by forming metal film such as evaporation process on whole surface, then photoetching agent pattern and the deposition part of metal film on it is removed together.In the technique that forms metal film, for example can form the thick Ni film of about 30nm, then can form the thick Au film of about 400nm.After this, form dielectric film 14 with covering grid electrode 11g at dielectric film 12.
Can make thus the GaN based hemts according to the first embodiment.
Notice that the etching selectivity relevant with the dry etching between the AlGaN of the GaN of cap rock 8 and hole blocking layer 6 is large.Therefore, as shown in Figure 6, for etching cap rock 8, in case expose the surface of hole blocking layer 6, then carry out etching and just become unusually difficult.In other words, can utilize hole blocking layer 6 as the dry etching of etching obstacle (etching stopper).Therefore, dry etching can easily be controlled.On the other hand, with the GaN of the GaN of cap rock 8 and electron supply layer 5 between the relevant etching selectivity of dry etching little.Therefore, as shown in Figure 6, when making the GaN based hemts of reference example, even expose the surface of hole blocking layer 6, etching is also carried out easily.Control such as the time of therefore, carrying out relative complex are controlled.
If there is not hole blocking layer 6, then at the During Annealing that Mg is activated, may be diffused in the raceway groove as the Mg of p-type impurity.The present embodiment can stop such Mg diffusion.
Should be noted that hole blocking layer 6 is not limited to AlN layer and AlGaN layer particularly, for example, the AlGaN layer that can use its Al composition to be higher than the Al composition of electron supply layer 5 is used for hole blocking layer 6.Perhaps, for example, the InAlN layer can be used for hole blocking layer 6.When the AlGaN layer was used for hole blocking layer 6, the composition of hole blocking layer 6 can be by Al
yGa
1-yN (x＜y≤1) expression, the composition of electron supply layer is by Al
xGa
1-xN (0＜x＜1) expression.When the InAlN layer was used for hole blocking layer 6, the composition on barrier layer, cave can be by In
zAl
1-zN (0≤z≤1) expression, the composition of electron supply layer is by Al
xGa
1-xN (0＜x＜1) expression.If hole blocking layer 6 is AlN layers, then the thickness of hole blocking layer 6 is preferred 1nm or larger and 3nm or less (such as 2nm), if hole blocking layer 6 is AlGaN layer or InAlN layer, then is preferably 3nm or larger and 8nm or less (such as 5nm).When hole blocking layer 6 was thinner than the lower limit of above-mentioned preferable range, then the hole barrier performance may be low.When hole blocking layer 6 was thicker than the upper limit of above-mentioned preferable range, the normal off operation is difficulty relatively.In addition, as mentioned above, when the lattice constant of the nitride-based semiconductor of hole blocking layer 6 during less than the lattice constant of electron supply layer 5, the density of the 2DEG the electron channel layer near may be higher and conducting resistance may be lower.
(the second embodiment)
Next, the second embodiment will be described.Fig. 7 is the cross-sectional view that illustrates according to the structure of the GaN based hemts (compound semiconductor device) of the second embodiment.
Compare with the first embodiment, in the second embodiment, hole blocking layer 6 extends between source electrode 11s and drain electrode 11d in plane graph, and hole blocking layer 6 only is arranged on below the gate electrode 11g in plane graph.Other structures are similar to the first embodiment.
In addition, be similar to the first embodiment, so the second embodiment of structure has successfully realized suppressing the effect that conducting resistance increases and current path changes in the situation that has hole blocking layer 6.
(the 3rd embodiment)
Next, the 3rd embodiment will be described.Fig. 8 is the cross-sectional view that illustrates according to the structure of the GaN based hemts (compound semiconductor device) of the 3rd embodiment;
Compare with the first embodiment, make gate electrode 11g and compound semiconductor stacked structure 7 form Schottky contacts, the 3rd embodiment adopts dielectric film 12 between gate electrode 11g and compound semiconductor stacked structure 7, to allow dielectric film 12 as gate insulating film.In brief, in dielectric film 12, do not form opening 13g, and adopt MIS type structure.
In addition, be similar to the first embodiment, so the 3rd embodiment of structure has successfully realized suppressing the effect that conducting resistance increases and current path changes in the situation that hole blocking layer 6 exists.
Be used for the not particularly restriction of material of dielectric film 12, wherein preferred example comprises oxide, nitride or the nitrogen oxide of Si, Al, Hf, Zr, Ti, Ta and W.Aluminium oxide is particularly preferred.The thickness of dielectric film 12 can be 2nm to 200nm (for example about 10nm or 10nm).
(the 4th embodiment)
Next, the 4th embodiment will be described.Fig. 9 A to Fig. 9 B illustrates manufacturing successively according to the cross-sectional view of the method for the GaN based hemts (compound semiconductor device) of the 4th embodiment.
In the present embodiment, at first similar to the first embodiment shown in Fig. 9 A, carry out until form the process of electron supply layer 5.Should be noted that electron supply layer 5 forms so that it is than in the first embodiment the thick a little about 2nm of electron supply layer.Then stop the supply of TMA gas and TMG gas, and continue to supply with NH
3Gas, and keep identical or higher temperature.Preferably, the temperature of maintenance exceeds in the temperature that is used to form electron supply layer 5 and than it between 50 ℃ the temperature.Retention time is depended on the maintenance temperature, and when temperature remained the temperature that is used to form electron supply layer 5, preferably the retention time was about 5 minutes.Maintenance under specified temp is preferentially removed Ga from the AlGaN of electron supply layer 5.Therefore, the Ga mark of the surface of electron supply layer 5 descends and the increase of Al mark.In brief, shown in Fig. 9 B, in the surface of electron supply layer 5, form hole blocking layer 6.Should be noted that to keep temperature higher, although it is higher to remove speed, time control is more difficult.After keeping, comprise similarly that with the first embodiment formation from cap rock 8 is until the process of the formation of dielectric film 14.
Because the kind of compound semiconductor layer to be formed is less than the first embodiment, so compare the first embodiment, the 4th embodiment is so that control is comparatively easy.
By after keeping (annealing) formation hole blocking layer 6, can above hole blocking layer 6, form AlN layer etc.
(the 5th embodiment)
The 5th embodiment relates to the discrete package part of the compound semiconductor device that comprises the GaN based hemts.Figure 10 is the figure that illustrates according to the discrete package part of the 5th embodiment.
In the 5th embodiment, as shown in figure 10, use tube core adhesive 234 (such as solders) to be fixed to pad (land) (die pad) 233 according to the back side of the HEMT 210 of the compound semiconductor device of arbitrary embodiment in the first to the 5th embodiment.The termination of wire 235d (such as the Al line) is incorporated into the drain electrode weld pad 226d that is connected to drain electrode 11d, and the other end of wire 235d joins the drain lead 232d that is integrated with pad 233 to.The termination of wire 235s (for example Al wire) is incorporated into the source electrode weld pad 226s that is connected to source electrode 11s, and the other end of wire 235s joins the source lead 232s that separates with pad 233 to.The termination of wire 235g (such as the Al wire) is incorporated into the drain electrode weld pad 226g that is connected to drain electrode 11g, and the other end of wire 235g joins the grid lead 232g that separates with pad 233 to.Come pad 233, HEMT chip 210 etc. is encapsulated with moulded resin 231, so that the part of the part of the part of grid lead 232g, drain lead 232d and source lead 232s is outwards outstanding.
For example, can make the discrete package part by following steps.At first, use tube core adhesive 234 (such as solders) HEMT chip 210 to be engaged to the pad 233 of lead frame.Next, use wire 235g, 235d and 235s, respectively gate pad 226g is connected to the grid lead 232g of lead frame, the weld pad 226d that will drain by the wire joint and is connected to the drain lead 232d of lead frame and the source lead 232s that source electrode weld pad 226s is connected to lead frame.Use moulded resin 231 to be undertaken molded by transmitting molding process.Then lead frame is cut away.
(the 6th embodiment)
Next, the 6th embodiment will be described.The 6th embodiment relates to PFC (power factor correcting) circuit of being furnished with the compound semiconductor device that comprises the GaN based hemts.Figure 11 is the wiring diagram that illustrates according to the pfc circuit of the 6th embodiment.
In the process of making pfc circuit 250, such as solder switch element 251 is connected to diode 252, choking-winding 253 etc. such as using.
(the 7th embodiment)
Next, the 7th embodiment will be described.The 7th embodiment relates to the supply unit of being furnished with the compound semiconductor device that comprises the GaN based hemts.Figure 12 is the wiring diagram that illustrates according to the supply unit of the 7th embodiment.
This supply unit comprise high voltage primary side circuit 261, low-voltage second siding ring 262 and be arranged in primary side circuit 261 and second siding ring 262 between transformer 263.
In the present embodiment, the switch element 251 of pfc circuit 250 be will be used as according to the compound semiconductor device of any embodiment in first to fourth embodiment, and switch element 264a, 264b, 264c and the 264d of full electric bridge inverter circuit 260 used it for.Pfc circuit 250 and full electric bridge inverter circuit 260 are the parts of primary side circuit 261.On the other hand, switch element 265a, the 265b and the 265c that silica-based general MIS-FET (field-effect transistor) are used for secondary side circuit 262.
(the 8th embodiment)
Next, the 8th embodiment will be described.The 8th embodiment relates to the high-frequency amplifier of being furnished with the compound semiconductor device that comprises the GaN based hemts.Figure 13 is the wiring diagram that illustrates according to the high-frequency amplifier of the 8th embodiment.
High-frequency amplifier comprises digital predistortion circuit 271, frequency mixer 272a, 272b and power amplifier 273.
The nonlinear distortion of digital predistortion circuit 271 compensated input signals.Frequency mixer 272a mixes AC signal with the input signal that has compensated nonlinear distortion.Power amplifier 273 comprises the compound semiconductor device according to the arbitrary embodiment in first to fourth embodiment, and the input signal that will mix with ac signal amplifies.In the example of shown the present embodiment, when switching, the signal of outlet side can mix with AC signal by frequency mixer 272b, and can be sent back to digital predistortion circuit 271.
The composition that is used for the compound semiconductor layer of compound semiconductor stacked structure has no particular limits, and can use GaN, AlN and InN etc.Can also use their mixed crystal.
The structure of gate electrode, source electrode and drain electrode is not limited to the structure in the above-described embodiment.For example, they can be constructed by individual layer.The method that forms these electrodes is not limited to stripping technology.Annealing after the formation of source electrode can be omitted, as long as can obtain ohm property.Can anneal to gate electrode.
In the present embodiment, substrate can be carborundum (SiC) substrate, Sapphire Substrate, silicon substrate, GaN substrate and GaAs substrate or similar material.Substrate can be any in conductive substrates, SI-substrate and the dielectric substrate.
According to compound semiconductor device described above etc., having in the situation of hole blocking layer, when realizing the normal off operation, can obtain good conductive characteristic.
Claims (18)
1. compound semiconductor device comprises:
Substrate;
Be formed on electron channel layer and electron supply layer on the described substrate;
Be formed on the described electron supply layer or the gate electrode of top, source electrode and drain electrode;
Be formed on the p-type semiconductor layer between described electron supply layer and the described gate electrode; With
Be formed on the hole blocking layer between described electron supply layer and the described p-type semiconductor layer, the band gap of described hole blocking layer is greater than the band gap of described electron supply layer.
2. compound semiconductor device according to claim 1, wherein
The composition of described electron supply layer is by Al
xGa
1-xN (0＜x＜1) expression, and
The composition of described hole blocking layer is by Al
yGa
1-yN (x＜y≤1) expression.
3. compound semiconductor device according to claim 1, wherein
The composition of described electron supply layer is by Al
xGa
1-xN (0＜x＜1) expression, and
The composition of described hole blocking layer is by In
zAl
1-zN (0≤z≤1) expression.
4. each described compound semiconductor device in 3 according to claim 1, wherein said electron channel layer is the GaN layer.
5. each described compound semiconductor device in 3 according to claim 1, wherein said p-type semiconductor layer is the GaN layer that comprises Mg.
6. each described compound semiconductor device in 3 according to claim 1 also comprises the gate insulating film that is formed between described gate electrode and the described p-type semiconductor layer.
7. each described compound semiconductor device in 3 according to claim 1 also comprises the zone that covers between described gate electrode and the described source electrode and the terminated film of the described electron supply layer in each zone in the zone between described gate electrode and the described drain electrode.
8. supply unit comprises:
Compound semiconductor device, described compound semiconductor device comprises:
Substrate;
Be formed on electron channel layer and electron supply layer on the described substrate;
Be formed on the described electron supply layer or the gate electrode of top, source electrode and drain electrode;
Be formed on the p-type semiconductor layer between described electron supply layer and the described gate electrode; With
Be formed on the hole blocking layer between described electron supply layer and the described p-type semiconductor layer, the band gap of described hole blocking layer is greater than the band gap of described electron supply layer.
9. amplifier comprises:
Compound semiconductor device, described compound semiconductor device comprises:
Substrate;
Be formed on electron channel layer and electron supply layer on the described substrate;
Be formed on the described electron supply layer or the gate electrode of top, source electrode and drain electrode;
Be formed on the p-type semiconductor layer between described electron supply layer and the described gate electrode; With
Be formed on the hole blocking layer between described electron supply layer and the described p-type semiconductor layer, the band gap of described hole blocking layer is greater than the band gap of described electron supply layer.
10. method of making compound semiconductor device comprises:
On substrate, form electron channel layer and electron supply layer;
On the described electron supply layer or above form gate electrode, source electrode and drain electrode;
Before forming described gate electrode, form the p-type semiconductor layer between described electron supply layer and described gate electrode; And
Before forming described p-type semiconductor layer, form the hole blocking layer between described electron supply layer and described p-type semiconductor layer, the band gap of described hole blocking layer is greater than the band gap of described electron supply layer.
11. the method for manufacturing compound semiconductor device according to claim 10, wherein
The composition of described electron supply layer is by Al
xGa
1-xN (0＜x＜1) expression, and
The composition of described hole blocking layer is by Al
yGa
1-yN (x＜y≤1) expression.
12. the method for manufacturing compound semiconductor device according to claim 10, wherein
The composition of described electron supply layer is by Al
xGa
1-xN (0＜x＜1) expression, and
The composition of described hole blocking layer is by In
zAl
1-zN (0≤z≤1) expression.
13. the method for each described manufacturing compound semiconductor device in 12 according to claim 10 wherein forms described hole blocking layer and comprises from the surface of described electron supply layer and remove Ga.
14. the method for each described manufacturing compound semiconductor device in 12 according to claim 10 wherein forms described p-type semiconductor layer and comprises and use described hole blocking layer to carry out patterning as the etching obstacle by dry etching.
15. the method for each described manufacturing compound semiconductor device in 12 according to claim 10, wherein said electron channel layer is the GaN layer.
16. the method for each described manufacturing compound semiconductor device in 12 according to claim 10, wherein said p-type semiconductor layer is the GaN layer that comprises Mg.
17. the method for each described manufacturing compound semiconductor device in 12 also is included between described gate electrode and the described p-type semiconductor layer and forms gate insulating film according to claim 10.
18. the method for each described manufacturing compound semiconductor device in 12 according to claim 10 also comprises the terminated film of the described electron supply layer in each zone in the zone that forms between regional and described gate electrode and the described drain electrode that covers between described gate electrode and the described source electrode.
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|---|---|
| US (1) | US20130075751A1 (en) |
| JP (1) | JP2013074179A (en) |
| KR (1) | KR101358586B1 (en) |
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| TW (1) | TWI472036B (en) |
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| CN112133749A (en) * | 2020-09-15 | 2020-12-25 | 西安电子科技大学芜湖研究院 | P-type cap layer enhanced HEMT device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| US20130075751A1 (en) | 2013-03-28 |
| TW201314906A (en) | 2013-04-01 |
| TWI472036B (en) | 2015-02-01 |
| JP2013074179A (en) | 2013-04-22 |
| KR20130034585A (en) | 2013-04-05 |
| KR101358586B1 (en) | 2014-02-04 |
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