CN103023489B - The method of decimal type phase-locked loop and the phase noise for reducing decimal type phase-locked loop - Google Patents
The method of decimal type phase-locked loop and the phase noise for reducing decimal type phase-locked loop Download PDFInfo
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Abstract
A method for decimal type phase-locked loop and the phase noise for reducing decimal type phase-locked loop, can be applicable to wideband communication and radio-frequency communication field, reduces the phase noise of decimal type phase-locked loop, promotes communication quality and cost benefit.The present invention utilizes the frequency eliminator design through improvement, reaches the object of the mistake sampling frequency of raising ∑-sigma-delta modulator.Therefore, decimal type phase-locked loop framework proposed by the invention and method for designing can reach with simple and easy and reliable frequency eliminator design the effect reducing phase noise, avoid the complexity excessively increasing hardware designs simultaneously.
Description
Technical field
The present invention has about communication and radio circuit design, espespecially a kind of method of the phase noise about reduction decimal type phase-locked loop.
Background technology
In recent years, communication system science and technology has remarkable progress, and the application surface of various telecommunications product is also increasingly extensive, makes the wherein a kind of necessary component-phase-locked loop of many communication systems, becomes the target that association area research staff falls over each other research and development.
At present, the frequency resolution adopting the frequency synthesizer of integer type phase-locked loop to export is lower, and therefore, association area has has researched and developed the frequency synthesizer proposing to adopt decimal type phase-locked loop.Owing to adopting decimal type phase-locked loop that the frequency outputed signal can be made to be the little several times of reference frequency, therefore the frequency resolution adopting the frequency synthesizer of decimal type phase-locked loop to export is higher.Decimal type phase-locked loop most now all adopts ∑-sigma-delta modulator to control frequency eliminator (FrequencyDivider), make it in different clock cycle, produce different integral multiple frequency elimination coefficients, and then to obtain average frequency elimination coefficient be set decimal, realize the object of decimal frequency elimination.
Please refer to Fig. 1, describe the sample architecture schematic diagram of existing decimal type phase-locked loop 10.As shown in the figure, this decimal type phase-locked loop 10 comprises crystal oscillator 102, phase detector (PhaseDetector; PD) 104, charge pump (ChargePump; CP) 106, loop filter (LoopFilter; LP) 108, voltage-controlled oscillator (VoltageControlledOscillator; VCO) 110, radio frequency frequency eliminator (RFDivider) 112 and decimal frequency eliminator (FractionalFrequencyDivider) 114.This phase detector 104 produces charging control signal 104a or discharge control signal 104b.This loop filter 108 is that low pass filter is (by resistance R, electric capacity C
1, C
2formed).This radio frequency frequency eliminator 112 is to the phase-locked clock signal S of this voltage-controlled oscillator 110
f0carry out integer frequency elimination (N is the divisor of integer frequency elimination), then carry out decimal frequency elimination (I+K/F is the divisor of decimal frequency elimination) with this decimal frequency eliminator 114, produce phase place feedback signal S
fr, as the clock signal of this ∑-sigma-delta modulator, and feedback to this phase detector 104.
Please refer to Fig. 2, for showing the test result of the phase noise of the decimal type phase-locked loop 10 of Fig. 1.Curve VO (phase noise of voltage-controlled oscillator under phase lock loop locks pattern), VF (phase noise of voltage-controlled oscillator under free-run mode), LO (phase noise that ∑-sigma-delta modulator produces), LT (phase noise of overall phase-locked loop) represent the phase noise under various operation situation respectively.
The noise produced to suppress decimal frequency eliminator and the reference spur (referencespurs) produced because of decimal frequency elimination, in general ∑-sigma-delta modulator is adopted sampling (oversampling) and noise transfer (noiseshaping) technology, the former can reduce the noise in whole frequency range, and the noise of low frequency part can be transferred to HFS by the latter, and then by the loop filter (or low pass filter) of phase-locked loop by its filtering.In addition, in order to ensure to produce correct fractional frequency division coefficient, the clock signal of ∑-sigma-delta modulator can only be the output of this decimal frequency eliminator, and the sampling frequency that is crossing sampling can only be the output frequency of this decimal frequency eliminator.Simultaneously, in order to the noise ensureing to be transferred to high frequency can filtering effectively, the frequency range bandwidth of the phase locked loop system of usual employing decimal frequency elimination is all designed to smaller, otherwise may need to adopt the ∑-sigma-delta modulator of more high-order, so that noise is transferred to higher frequency, the further complexity increasing design, also needs the filter of more high-order to carry out the noise of filtering high frequency.But the practical application of many communication systems now all requires to adopt the phase locked loop system of decimal frequency elimination must have wider system bandwidth, to suppress the phase noise of voltage controlled oscillator (VCO), or realizes fast frequency hopping function.
Therefore, how to propose one and can produce comparatively low phase noise and larger frequency range, unlikely decimal type phase-locked loop and the relevant design method significantly increasing hardware cost and design complexities simultaneously, and then promote the application of decimal type phase-locked loop on high frequency and wideband communication, the real technical problem being current all circles and desiring most ardently solution.
Summary of the invention
In view of the shortcoming of above-mentioned prior art, the object of the present invention is to provide the decimal type phase-locked loop had compared with low phase noise and larger frequency range, and unlikely significantly increase the prerequisite of design complexities under, reach simplified design and the effect promoting usefulness simultaneously.
Another object of the present invention is, provides the method that effectively can reduce phase noise that decimal type phase-locked loop produces and reference spur, and promotes the application of decimal type phase-locked loop on high frequency and wideband communication.
For reaching above-mentioned purpose and other object, the invention provides a kind of decimal type phase-locked loop to comprise: phase detector, in order to receive reference voltage signal and phase place feedback signal, and this reference voltage signal and this phase place feedback signal are compared, to produce charging control signal or discharge control signal; Charge pump, in order to receive the charging control signal or discharge control signal that this phase detector produces, and produces charging output signal or electric discharge output signal according to this charging control signal or this discharge control signal; Loop filter, is electrically connected to this charge pump, to receive this charging output signal or electric discharge output signal, and produces the oscillation control signal of differentiation according to this charging output signal or electric discharge output signal; Voltage-controlled oscillator, is electrically connected to this loop filter, to receive this oscillation control signal, and produces phase-locked clock signal according to this oscillation control signal; Decimal frequency eliminator, is electrically connected to this voltage-controlled oscillator, to carry out decimal frequency elimination and reset clock signal to this phase-locked clock signal; And loop frequency eliminator, be electrically connected to this decimal frequency eliminator and this phase detector, to carry out integer frequency elimination to this back coupling clock signal, and export this phase place feedback signal and give this phase detector.
In addition, the present invention provides again a kind of method of the phase noise for reducing decimal type phase-locked loop, be applied in decimal type phase-locked loop, the method comprises: receive reference voltage signal and phase place feedback signal, and this reference voltage signal and this phase place feedback signal are compared, to produce charging control signal or discharge control signal; Charging output signal or electric discharge output signal is produced according to this charging control signal or this discharge control signal; This charging output signal or electric discharge output signal produce the oscillation control signal of differentiation; Phase-locked clock signal is produced according to this oscillation control signal; Decimal frequency elimination is carried out to this phase-locked clock signal, and reset clock signal; And integer frequency elimination is carried out to this back coupling clock signal, and export this phase place feedback signal.
Compared to prior art, the present invention not only can promote the frequency range of decimal type phase-locked loop effectively, to realize fast frequency hopping, and the phase noise of decimal type phase-locked loop can be reduced under the prerequisite increasing hardware complexity not significantly, significantly improve currently available technology realize decimal type phase-locked loop face narrower about frequency range and phase noise is too high, hardware cost improve and design complexities increase problem.
Accompanying drawing explanation
Fig. 1 describes the sample architecture schematic diagram of existing decimal type phase-locked loop;
Fig. 2 shows the test result of the phase noise of the decimal type phase-locked loop of Fig. 1;
Fig. 3 describes the configuration diagram of decimal type phase-locked loop according to embodiments of the invention;
Fig. 4 describes the further configuration diagram of decimal type phase-locked loop according to embodiments of the invention;
Fig. 5 shows the test result of the phase noise of decimal type phase-locked loop according to an embodiment of the invention; And
Fig. 6 describes the flow chart of the present invention for reducing the method for the phase noise of decimal type phase-locked loop.
Primary clustering symbol description
10 decimal type phase-locked loops
102 crystal oscillators
104 phase detectors
104a charging control signal
104b discharge control signal
106 charge pumps
108 loop filters
110 voltage-controlled oscillators
112 radio frequency frequency eliminators
114 decimal frequency eliminators
30 decimal type phase-locked loops
302 reference voltage generators
304 phase detectors
304a charging control signal
304b discharge control signal
306 charge pumps
308 loop filters
310 voltage-controlled oscillators
312 radio frequency frequency eliminators
314 decimal frequency eliminators
316 loop frequency eliminators
40 decimal type phase-locked loops
402 crystal oscillators
404 phase detectors
404a charging control signal
404b discharge control signal
406 charge pumps
408 loop filters
410 voltage-controlled oscillators
412 radio frequency frequency eliminators
414 decimal frequency eliminators
416 loop frequency eliminators
S
ref, S
ref' reference voltage signal
S
fr, S
fr', S
fr" phase place feedback signal
S
f0, S
f0', S
f0' phase-locked clock signal
CLK ', CLK " feedback clock signal
N, N ', N " integer
M ', M " integer
I, I ', I " integer
K, K ', K " integer
F, F ', F " integer
PD phase detector
CP charge pump
LF loop filter
VCO voltage-controlled oscillator
LT curve
LO curve
VF curve
VO curve
S601, S602, S603, S604, S605, S606 step.
Embodiment
The technology contents of the present invention is described by particular specific embodiment below, and the personage being familiar with this skill can be understood other advantage and effect of the present invention easily by the content that this specification disclosed.The present invention also can be implemented by other different instantiation or be applied, and the every details in this specification also based on different viewpoints and application, can carry out various modification and change under not departing from the spirit of the present invention.
Please refer to Fig. 3, describe the configuration diagram of the decimal type phase-locked loop 30 of the embodiment of the present invention.As shown in the figure, this decimal type phase-locked loop 30 comprises reference voltage generator 302 (as crystal oscillator), phase detector 304, charge pump 306, loop filter 308, voltage-controlled oscillator 310, radio frequency frequency eliminator 312, decimal frequency eliminator 314 and loop frequency eliminator 316.
It is f that this reference voltage generator 302 produces frequency
rreference voltage signal S
ref(consider according to circuit design, also can produce reference current signal), and export this signal to this phase detector 304.In preferred embodiment of the present invention, this reference voltage generator 302 can be designed to crystal oscillator, and it has stable frequency of oscillation, originates as reliable frequency of oscillation.
This phase detector 304 receives this reference voltage signal S
refand the phase place feedback signal S to be produced by loop frequency eliminator 316
fr', and to this reference voltage signal S
refwith this phase place feedback signal S
fr' compare, to produce charging control signal 304a or discharge control signal 304b.
The charging control signal 304a that this phase detector 304 of this charge pump 306 reception produces or discharge control signal 304b, and produce charging output signal (charging operations) or electric discharge output signal (discharge operation) according to this, export and give this loop filter 308.
This loop filter 308 is electrically connected to this charge pump 306, to receive this charging output signal or electric discharge output signal, and produces the oscillation control signal of differentiation according to this charging output signal or electric discharge output signal.In preferred embodiment of the present invention, this loop filter 308 can be designed to low pass filter or other filter form, viewing system and designer's demand and determine.
Voltage-controlled oscillator 310 is electrically connected to this loop filter 308, to receive this oscillation control signal, and is f according to this oscillation control signal generation frequency
0phase-locked clock signal S
f0'.
Should be specified at this, this radio frequency frequency eliminator 312 arranges based on system operating frequency or functional requirements, may unnecessary setting in some other phase-locked loop framework.In the present embodiment, this radio frequency frequency eliminator 312 is designed to integer frequency eliminator, in order to being f to frequency
0phase-locked clock signal S
f0' carry out the action of integer frequency elimination (except frequency is N ').In some phase-locked loop framework, this decimal frequency eliminator 314 is electrically connected to this voltage-controlled oscillator 310, with to this phase-locked clock signal S
f0' carry out the action of decimal frequency elimination (divisor is I '+K '/F ').
In the present embodiment, this decimal frequency eliminator 314 is electrically connected to this integer frequency eliminator 312, receive this integer frequency eliminator 312 to produce frequency be f
0the output signal of/N, to carry out the action of decimal frequency elimination (divisor is I '+K '/F ') to this output signal, and reset clock signal CLK '.In addition, this back coupling clock signal CLK ' can then as the clock pulse input signal of this decimal frequency eliminator 314 itself.
This loop frequency eliminator 316 is electrically connected to this decimal frequency eliminator 314 and this phase detector 304, and to carry out integer frequency elimination (except frequency is for M ") to this back coupling clock signal CLK ', and output frequency is f
r' phase place feedback signal S
fr' to this phase detector 304.
Please refer to Fig. 4, describe the configuration diagram of the decimal type phase-locked loop 40 of the embodiment of the present invention.As shown in the figure, decimal type phase-locked loop 40 is further detailed for the framework of decimal type phase-locked loop 30.In the present embodiment, crystal oscillator 402 produces reference voltage signal S
ref', and by this reference voltage signal S
ref' export phase detector 404 to.
This phase detector 404 can according to this reference voltage signal S
ref' and S
fr" comparative result produce charging control signal 404a or discharge control signal 404b, to control this charge pump 406, charge or discharge operation is carried out to the output of self, produce charging output signal or electric discharge output signal.
The charge/discharge output signal that this charge pump 406 produces then is electrically connected to this loop filter 408, and the undesired frequency content of filtering whereby, to produce the oscillation control signal of differentiation.In the present embodiment, this loop filter 408 is designed to low pass filter (be made up of resistance R ', electric capacity C1 ', C2 '), can undesired radio-frequency component or noise in this oscillation control signal of filtering.
The phase-locked clock signal S that this voltage-controlled oscillator 410 produces according to this oscillation control signal
f0" after this radio frequency frequency eliminator 412 (integer frequency eliminator) carries out integer frequency elimination (except frequency is N "), be resent to this decimal frequency eliminator 414 carry out further decimal frequency elimination (divisor is I "+K "/F ") action, feedback clock signal CLK to produce ".
This loop frequency eliminator 416 receives the back coupling clock signal CLK that this voltage-controlled oscillator 410 exports " and by its integer frequency elimination (except frequency is M "), to produce output frequency for f
r" phase place feedback signal S
fr".
In the present embodiment, this decimal frequency eliminator 414 comprises ∑-sigma-delta modulator, in order to control the running of this decimal frequency eliminator 414, and this back coupling clock signal CLK " through the clock pulse input signal of back coupling as this ∑-sigma-delta modulator.This back coupling clock signal CLK " frequency can be this phase place feedback signal S
fr" M of frequency " doubly, this feature will make decimal type phase-locked loop of the present invention have extremely significant usefulness compared to existing technologies to improve and cost benefit.
For example, when this decimal type phase-locked loop 40 is in the lock state, this phase place feedback signal S
fr" frequency should extremely close to this reference voltage signal S
ref' frequency, but, this back coupling clock signal CLK " frequency can be designed to apparently higher than this phase place feedback signal S
fr" frequency.Thus, the mistake sampling frequency of this ∑-sigma-delta modulator can significantly improve, and then the phase noise suppressing ∑-sigma-delta modulator to produce, and via the loop frequency eliminator 416 of lower-order, phase noise can be given filtering.Therefore, the present invention reaches by the mistake sampling frequency effectively improving this ∑-sigma-delta modulator the effect reducing system phase noise, and more high-order ∑-sigma-delta modulator can be avoided adopting to increase with the cost that more high-order loop frequency eliminator may bring simultaneously.
Please refer to Fig. 5, show the test result of the phase noise of decimal type phase-locked loop according to an embodiment of the invention.Wherein, reference voltage signal is set as 50MHz, system bandwidth is set to 1MHz, ∑-sigma-delta modulator is set to three rank and except frequency M=5 time.Curve VO1 (phase noise of voltage-controlled oscillator under phase lock loop locks pattern), VF1 (phase noise of voltage-controlled oscillator under free-run mode), LO1 (phase noise that ∑-sigma-delta modulator produces), LT1 (phase noise of overall phase-locked loop) represent the phase noise under various operation situation respectively.As shown in the figure, compared to shown in Fig. 2 about the test result of existing decimal type phase-locked loop, the phase noise test result of decimal type phase-locked loop proposed by the invention is obviously suppressed, such as: when deviation frequency is 1MHz, phase noise test result of the present invention comparatively prior art improves 26dBc/Hz.
Please refer to Fig. 6, describe the flow chart of the present invention for reducing the method for the phase noise of decimal type phase-locked loop.First, in step S601, receive reference voltage signal and phase place feedback signal, and this reference voltage signal and this phase place feedback signal are compared, to produce charging control signal or discharge control signal, then proceed to step S602.
In step S602, receive this charging control signal or this discharge control signal, and produce charging output signal or electric discharge output signal according to this charging control signal or this discharge control signal, then proceed to step S603.
In step S603, receive this charging output signal or electric discharge output signal, and produce the oscillation control signal of differentiation according to this charging output signal or electric discharge output signal, then proceed to step S604.
In step S604, receive this oscillation control signal, and produce phase-locked clock signal according to this oscillation control signal, then proceed to step S605.
In step S605, receive this phase-locked clock signal, and decimal frequency elimination is carried out to this phase-locked clock signal, then proceed to step S606.
Finally, in step S606, integer frequency elimination is carried out to this back coupling clock signal, and export this phase place feedback signal.
In an embodiment, this phase-locked clock signal is carried out to the step S606 of decimal frequency elimination, also comprise and first integer frequency elimination is carried out to this phase-locked clock signal, then the step of decimal frequency elimination is carried out to this phase-locked clock signal through integer frequency elimination.
In sum, the method for decimal type phase-locked loop of the present invention and the phase noise for reducing decimal type phase-locked loop, can be applied to wideband and radio-frequency (RF) system design, communication quality and cost benefit are got a promotion.In addition, the ∑-sigma-delta modulator of decimal type phase-locked loop of the present invention can adopt higher mistake sampling frequency, reaches the effect reducing phase noise.Moreover the method for the phase noise for reducing decimal type phase-locked loop of the present invention can utilize simple and easy and design reliably, realizes the reduction of phase noise easily, avoids the raising causing hardware cost because design complexities significantly increases simultaneously.
Above-described embodiment is the principle of illustrative the present invention and effect thereof only, but not for limiting the present invention.Any the person skilled in the art all under the spirit and category of the present invention, can carry out modifying to above-described embodiment and changes.Therefore, the rights protection scope of the present invention, should listed by claims.
Claims (6)
1. a decimal type phase-locked loop, it produces different integral multiple frequency elimination coefficients within the different clock cycle, makes produced average frequency elimination coefficient be set decimal, and this decimal type phase-locked loop comprises:
Phase detector, in order to receive reference voltage signal and phase place feedback signal, and compares this reference voltage signal and this phase place feedback signal, to produce charging control signal or discharge control signal;
Charge pump, in order to receive the charging control signal or discharge control signal that this phase detector produces, and produces charging output signal or electric discharge output signal according to this charging control signal or this discharge control signal;
Loop filter, is electrically connected to this charge pump, to receive this charging output signal or electric discharge output signal, and produces the oscillation control signal of differentiation according to this charging output signal or electric discharge output signal;
Voltage-controlled oscillator, is electrically connected to this loop filter, to receive this oscillation control signal, and produces phase-locked clock signal according to this oscillation control signal;
Integer frequency eliminator, is electrically connected to this voltage-controlled oscillator, produces output signal to carry out integer frequency elimination to this phase-locked clock signal;
Decimal frequency eliminator, is electrically connected to this integer frequency eliminator, carries out decimal frequency elimination and reset clock signal with the output signal produced this integer frequency eliminator; And
Loop frequency eliminator, is electrically connected to this decimal frequency eliminator and this phase detector, carries out integer frequency elimination with the back coupling clock signal exported this decimal frequency eliminator, and exports this phase place feedback signal and give this phase detector.
2. decimal type phase-locked loop according to claim 1, it is characterized in that, this decimal frequency eliminator comprises sigma-delta modulator, this sigma-delta modulator is the running controlling this decimal frequency eliminator, and the back coupling clock signal that this decimal frequency eliminator exports is through the clock pulse input signal of back coupling as this sigma-delta modulator.
3. decimal type phase-locked loop according to claim 1, is characterized in that, this reference voltage signal produced by crystal oscillator.
4., for reducing a method for the phase noise of decimal type phase-locked loop, be applied in decimal type phase-locked loop, the method comprises:
Receive reference voltage signal and phase place feedback signal, and this reference voltage signal and this phase place feedback signal are compared, to produce charging control signal or discharge control signal;
Charging output signal or electric discharge output signal is produced according to this charging control signal or this discharge control signal;
The oscillation control signal of differentiation is produced according to this charging output signal or electric discharge output signal;
Phase-locked clock signal is produced according to this oscillation control signal;
With integer frequency eliminator, integer frequency elimination carried out to this phase-locked clock signal and produce output signal;
With decimal frequency eliminator, decimal frequency elimination is carried out to the output signal that this integer frequency eliminator produces, and reset clock signal; And
With loop frequency eliminator, integer frequency elimination is carried out to the back coupling clock signal that this decimal frequency eliminator exports, and export this phase place feedback signal.
5. the method for the phase noise for reducing decimal type phase-locked loop according to claim 4, is characterized in that, this reference voltage signal produced by crystal oscillator.
6. the method for the phase noise for reducing decimal type phase-locked loop according to claim 4, it is characterized in that, this decimal frequency eliminator comprises sigma-delta modulator, and in order to control the running of this decimal frequency eliminator, and this back coupling clock signal is through the clock pulse input signal of back coupling as this sigma-delta modulator.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055800A (en) * | 1990-04-30 | 1991-10-08 | Motorola, Inc. | Fractional n/m synthesis |
| TW200529566A (en) * | 2004-02-26 | 2005-09-01 | Mediatek Inc | Phase locked loop for generating a output signal |
| CN1945974A (en) * | 2005-08-18 | 2007-04-11 | 三星电子株式会社 | Semiconductor device, spread spectrum clock generator and method thereof |
| CN101114832A (en) * | 2006-07-28 | 2008-01-30 | 晨星半导体股份有限公司 | Delta-sigma modulated fractional-n pll frequency synthesizer |
| CN102291125A (en) * | 2010-06-15 | 2011-12-21 | 开曼晨星半导体公司 | Fast phase locking system for automatically calibrated fractional-N phase lock loop (PLL) |
-
2011
- 2011-09-20 CN CN201110279926.5A patent/CN103023489B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055800A (en) * | 1990-04-30 | 1991-10-08 | Motorola, Inc. | Fractional n/m synthesis |
| TW200529566A (en) * | 2004-02-26 | 2005-09-01 | Mediatek Inc | Phase locked loop for generating a output signal |
| CN1945974A (en) * | 2005-08-18 | 2007-04-11 | 三星电子株式会社 | Semiconductor device, spread spectrum clock generator and method thereof |
| CN101114832A (en) * | 2006-07-28 | 2008-01-30 | 晨星半导体股份有限公司 | Delta-sigma modulated fractional-n pll frequency synthesizer |
| CN102291125A (en) * | 2010-06-15 | 2011-12-21 | 开曼晨星半导体公司 | Fast phase locking system for automatically calibrated fractional-N phase lock loop (PLL) |
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| CP03 | Change of name, title or address |
Address after: 310000 Room 101, 1st Floor, Block C, No. 57, Changhe Street, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: Hangzhou Bolian Intelligent Technology Co.,Ltd. Address before: Room 106, Building No. 1, 611 Jianghong Road, Changhe Street, Binjiang District, Hangzhou City, Zhejiang 310000 Patentee before: HANGZHOU GUBEI ELECTRONICS TECHNOLOGY Co.,Ltd. |
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| TR01 | Transfer of patent right |
Effective date of registration: 20220824 Address after: Room 2502, Area A, Building 1, No. 57, Jiang 2nd Road, Changhe Street, Binjiang District, Hangzhou City, Zhejiang Province, 310000 Patentee after: Hangzhou Beilian Low Carbon Technology Co.,Ltd. Address before: 310000 Room 101, 1st Floor, Block C, No. 57, Changhe Street, Binjiang District, Hangzhou City, Zhejiang Province Patentee before: Hangzhou Bolian Intelligent Technology Co.,Ltd. |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Decimal phase locked loop and methods for reducing phase noise in decimal phase locked loop Effective date of registration: 20230613 Granted publication date: 20160420 Pledgee: Hangzhou United Rural Commercial Bank Limited by Share Ltd. Baoshan Branch Pledgor: Hangzhou Beilian Low Carbon Technology Co.,Ltd. Registration number: Y2023980043832 |