CN102957336A - Pulse width modulation circuit for direct-current broken circuit - Google Patents
Pulse width modulation circuit for direct-current broken circuit Download PDFInfo
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- CN102957336A CN102957336A CN2011102401309A CN201110240130A CN102957336A CN 102957336 A CN102957336 A CN 102957336A CN 2011102401309 A CN2011102401309 A CN 2011102401309A CN 201110240130 A CN201110240130 A CN 201110240130A CN 102957336 A CN102957336 A CN 102957336A
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Abstract
The invention discloses a pulse width modulation circuit for a direct-current broken circuit. The circuit comprises a first pulse generation circuit, a second pulse generation circuit, a first driving generation circuit, a second driving generation circuit and an output circuit, wherein the first pulse generation circuit is used for converting direct-current input voltage to pulse voltage with the pulse width T1; the second pulse generation circuit is used for converting the pulse voltage with the pulse width T1 to pulse voltage with the pulse width T2; the first driving generation circuit is used for frequency division of the pulse voltage with the pulse width T1 and outputting the pulse voltage DRIVER1 subjected to frequency division to the output circuit; the second driving generation circuit is used for frequency division of the pulse voltage with the pulse width T2 and outputting the pulse voltage DRIVER2 subjected to frequency division to the output circuit; and the output circuit is used for outputting the pulse voltage DRIVER1 outputted by the first driving generation circuit and the pulse voltage DRIVER2 outputted by the second driving generation circuit and outputting total driving pulse voltage DRIVER.
Description
Technical field
The present invention relates to electric and electronic technical field, relate in particular to a kind of pulse-width modulation circuit for direct current interruption.
Background technology
Along with the development of science and technology, green energy resource constantly enters among the daily productive life.Yet luminous energy, wind energy transformation are that electric energy becomes the current research focus.Could use to load and generally need to be transformed to alternating current through inverter for the direct voltage that obtains by photovoltaic battery array, wind power generation or other the whole bag of tricks in the prior art.Be usually less than the electrical network crest voltage, can't directly be linked among the electrical network, for the user.Therefore, usually direct voltage need to be boosted to and to realize that voltage-type generates electricity by way of merging two or more grid systems after being higher than the electrical network crest voltage.Usually the method that adopts has: the single-stage buck type generates electricity by way of merging two or more grid systems, be connected to the grid by inverter after will organizing the generator unit series connection more, this method system topological is simple, the one-level energy conversion just can be realized generating electricity by way of merging two or more grid systems, but when output dc voltage is lower than the electrical network crest voltage, the inverter cisco unity malfunction reduces system's generating efficiency; Two Stages is generated electricity by way of merging two or more grid systems, and prime DC/DC converter is realized boost function, and rear class DC/AC inverter is realized generating electricity by way of merging two or more grid systems, although the method can be under lower VD normal power generation; The transformer booster type generates electricity by way of merging two or more grid systems, and realizes being incorporated into the power networks feed after combining inverter is boosted through transformer.
In realizing process of the present invention, the inventor finds that there are the following problems at least in the prior art:
The high direct voltage part of photovoltaic DC-to-AC converter of the prior art breaks down or other emergencies need to turn-off the time at circuit, produces easily the high-voltage arc discharge phenomenon, thereby causes fire or dangerously can't in time realize direct current interruption.
Summary of the invention
Embodiments of the invention provide a kind of pulse-width modulation circuit for direct current interruption, cooperate hardware circuit, arc extinguishing when realizing the high voltage direct current disconnection.For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of pulse-width modulation circuit for direct current interruption provided by the invention comprises: the first pulse generating circuit, the second pulse generating circuit, first drive circuit for generating, second and drive circuit for generating and output circuit;
Wherein, described the first pulse generating circuit is used for DC input voitage is converted into the pulse voltage that pulse duration is T1;
Described the second pulse generating circuit is converted into the pulse voltage that pulse duration is T2 for the pulse voltage that with pulse duration is T1;
Described first drives circuit for generating, carry out frequency division for the pulse voltage that with described pulsewidth is T1 and process, and the pulse voltage DRIVER1 behind the frequency division exports to output circuit;
Described second drives circuit for generating, carry out frequency division for the pulse voltage that with described pulsewidth is T2 and process, and the pulse voltage DRIVER2 behind the frequency division exports to output circuit;
Described output circuit is used for the pulse voltage DRIVER1 of described the first driving circuit for generating output and the pulse voltage DRIVER2 of described the second driving circuit for generating output are exported processing, exports total driving pulse voltage DRIVER.
A kind of pulse-width modulation circuit for direct current interruption that the embodiment of the invention provides drives circuit for generating, second by the first pulse generating circuit, the second pulse generating circuit, first and drives circuit for generating and output circuit; Wherein, described the first pulse generating circuit is used for DC input voitage is converted into the pulse voltage that pulse duration is T1; Described the second pulse generating circuit is converted into the pulse voltage that pulse duration is T2 for the pulse voltage that with pulse duration is T1; Described first drives circuit for generating, carry out frequency division for the pulse voltage that with described pulsewidth is T1 and process, and the pulse voltage DRIVER1 behind the frequency division exports to output circuit; Described second drives circuit for generating, carry out frequency division for the pulse voltage that with described pulsewidth is T2 and process, and the pulse voltage DRIVER2 behind the frequency division exports to output circuit; Described output circuit, be used for the pulse voltage DRIVER1 of described the first driving circuit for generating output and the pulse voltage DRIVER2 of described the second driving circuit for generating output are exported processing, export total driving pulse voltage DRIVER, when input INPUT is high voltage direct current, conducting and shutoff by DRIVERK control IGBT switching tube, make the copped wave of output voltage OUTPUT high pressure, the high direct voltage part that prevents photovoltaic DC-to-AC converter breaks down or other emergencies produce the high-voltage arc discharge phenomenon need to turn-off the time at circuit, realizes timely direct current interruption.
Description of drawings
A kind of pulse-width modulation circuit figure for direct current interruption that Fig. 1 provides for the embodiment of the invention;
The circuit diagram of a kind of pulse-width modulation circuit for direct current interruption that Fig. 2 provides for the embodiment of the invention;
A kind of pulse-width modulation circuit sequential chart for direct current interruption that Fig. 3 provides for the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing a kind of pulse-width modulation circuit for direct current interruption that the embodiment of the invention provides is described in detail.
As shown in Figure 1, a kind of pulse-width modulation circuit figure for direct current interruption that provides for the embodiment of the invention; This circuit comprises: the first pulse generating circuit 101, the second pulse generating circuit 102, first drive circuit for generating 103, second and drive circuit for generating 104 and output circuit 105;
Wherein, described the first pulse generating circuit 101 is used for DC input voitage is converted into the pulse voltage that pulse duration is T1;
Described the second pulse generating circuit 102 is converted into the pulse voltage that pulse duration is T2 for the pulse voltage that with pulse duration is T1;
Described first drives circuit for generating 103, carry out frequency division for the pulse voltage that with described pulsewidth is T1 and process, and the pulse voltage DRIVER1 behind the frequency division exports to output circuit;
Described second drives circuit for generating 104, carry out frequency division for the pulse voltage that with described pulsewidth is T2 and process, and the pulse voltage DRIVER2 behind the frequency division exports to output circuit;
Described output circuit 105 is used for the pulse voltage DRIVER1 of described the first driving circuit for generating output and the pulse voltage DRIVER2 of described the second driving circuit for generating output are exported processing, exports total driving pulse voltage DRIVER.
The circuit diagram of a kind of pulse-width modulation circuit for direct current interruption that provides for the embodiment of the invention as shown in Figure 2; This circuit comprises: the first pulse generating circuit 101, the second pulse generating circuit 102, first drive circuit for generating 103, second and drive circuit for generating 104 and output circuit 105;
Wherein, described the first pulse generating circuit comprises: the 3rd resistance R 3, the six resistance R 6, the ten resistance R 10, the 14 resistance R 14, the 15 resistance R 15, the 17 resistance R 17, the 50 resistance R 50, the three capacitor C, 3, the first amplifier N1 and the first diode V10;
Described the 14 resistance R 14 1 termination DC input voitage V1, the other end links to each other with described the 15 resistance R 15; The positive input terminal of described the first amplifier N1 of described the 15 resistance R 15 another terminations;
Described the 50 resistance R 50 1 termination DC input voitage, the other end links to each other with described the 17 resistance R 17; The negative input end of described the first amplifier N1 of described the 17 resistance R 17 another terminations;
Described the tenth resistance R 10 1 ends link to each other other end ground connection with described the 14 resistance R 14 other ends;
Described the 3rd capacitor C 3 one ends link to each other other end ground connection with described the 50 resistance R 50 other ends;
Described the 3rd resistance R 3 one ends link to each other the positive input terminal of described the first amplifier N1 of another termination with the first diode V10 is anodal; Described the first diode V10 negative pole links to each other with the output of described the first amplifier N1;
Between the positive input terminal and output of 6 parallel connections of described the 6th resistance R and described the first amplifier N1;
The power access end of described the first amplifier N1 and described DC input voitage V1 join.
Wherein, described the second pulse generating circuit comprises: the 16 resistance R 16, the second triode Q2, the 8th resistance R 8, the 12 resistance R 12, the first capacitor C 1, the first triode Q1, the 19 resistance R 19, the 20 resistance R 20, the 21 resistance R 21, the 4th capacitor C 4, the 5th capacitor C 5, the 4th voltage-stabiliser tube V40, the 23 resistance R 23, the 22 resistance R 22, the 24 resistance R 24, the 25 resistance R 25, the second amplifier N2;
Described the 16 resistance R 16 1 ends link to each other with the output of described the first amplifier N1, and the other end links to each other with the base stage of described the second triode Q2;
The grounded emitter of described the second triode Q2, collector electrode link to each other with an end of described the 8th resistance R 8 and described the 12 resistance R 12 respectively;
Between the emitter and collector electrode of 1 parallel connection of described the first capacitor C and described the second triode Q2;
The other end of described the 8th resistance R 8 links to each other with the emitter of described the first triode;
The other end of described the 12 resistance R 12 links to each other with the base stage of described the first triode;
The collector electrode of described the first triode links to each other with an end of described the 19 resistance;
The other end of described the 19 resistance respectively with described the 21 resistance R 21, described the 4th capacitor C 4, the negative pole of described the 4th voltage-stabiliser tube V40 links to each other with an end of described the 23 resistance R 23;
The other end of described the 21 resistance R 21 respectively with described the 5th capacitor C 5, an end of described the 25 resistance R 25 links to each other; The other end ground connection of described the 5th capacitor C 5; The negative input end of the described second amplifier N2 of another termination of described the 25 resistance R 25 links to each other;
Described the 4th capacitor C 4 other end ground connection;
The plus earth of described the 4th voltage-stabiliser tube V40;
The other end of described the 23 resistance R 23 links to each other with an end of described the 22 resistance R 22 and described the 24 resistance R 24 respectively;
The other end ground connection of described the 22 resistance R 22;
The other end of described the 24 resistance R 24 links to each other with the positive input terminal of described the second amplifier N2;
Described the 20 resistance R 20 is connected in parallel between the positive input terminal and output of described the second amplifier N2.
Wherein, described the first driving circuit for generating comprises: the 4th resistance R 4, the 11 resistance R 11, the first resistance R 1, the 5th resistance R 5, the second resistance R 2, the 9th resistance R 9, four high guaily unit N4, the second capacitor C 2, the second diode V20, the 13 resistance R 13, the 3rd diode V30, the 18 resistance R 18 and the 7th resistance R 7;
One end of described the 4th resistance R 4 links to each other with second source V2, and the other end links to each other with described the 11 resistance R 11, described the first resistance R 1, described the second capacitor C 2 respectively;
Described the 11 resistance R 11 other end ground connection;
Described the first resistance R 1 other end links to each other with described the second resistance R 2, described the 5th resistance R 5 respectively; Described the 5th resistance R 5 other ends link to each other with the positive input terminal of described four high guaily unit N4; Described the second resistance R 2 other ends link to each other with described the 7th resistance R 7 one ends; Described the 7th resistance R 7 other ends of stating link to each other with described four high guaily unit N4 output;
Described the second capacitor C 2 other ends link to each other with described the 9th resistance R 9, described the second diode V20 positive pole, described the 18 resistance R 18 respectively; The other end of described the 9th resistance R 9 links to each other with described four high guaily unit N4 negative input end; Described the second diode V20 negative pole links to each other with described the 13 resistance R 13 1 ends; The other end of described the 18 resistance R 18 links to each other with described the 3rd diode V30 negative pole; The other end of described the 13 resistance R 13 is anodal with described the 3rd diode V30, an end of described the 7th resistance R 7 links to each other, and the pulse voltage DRIVER1 behind the output frequency division.
Wherein, described the second driving circuit for generating comprises: the 32 resistance R 32, the 36 resistance R 36, the 30 resistance R 30, the 33 resistance R 33, the 31 resistance R 31, the 35 resistance R 35, the 3rd amplifier N3, the 8th capacitor C 8, the 8th diode V80, the 37 resistance R 37, the 9th diode V90, the 38 resistance R 38 and the 34 resistance R 34;
One end of described the 32 resistance R 32 links to each other with second source V2, and the other end links to each other with described the 36 resistance R 36, described the 30 resistance R 30, described the 8th capacitor C 8 respectively;
Institute's the 36 resistance R 36 other end ground connection;
Described the 30 resistance R 30 other ends link to each other with described the 31 resistance R 31, described the 33 resistance R 33 respectively; Described the 33 resistance R 33 other ends link to each other with the positive input terminal of described the 3rd amplifier N3; Described the 31 resistance R 31 other ends link to each other with described the 34 resistance R 34 1 ends; Described the 34 resistance R 34 other ends of stating link to each other with described the 3rd amplifier N3 output;
Described the 8th capacitor C 8 other ends link to each other with described the 35 resistance R 35, described the 8th diode V80 positive pole, described the 38 resistance R 38 respectively; The other end of described the 35 resistance R 35 links to each other with described the 3rd amplifier N3 negative input end; Described the 8th diode V80 negative pole links to each other with described the 37 resistance R 37 1 ends; The other end of described the 38 resistance R 38 links to each other with described the 9th diode V90 negative pole; The other end of described the 37 resistance R 37 is anodal with described the 9th diode V90, an end of described the 34 resistance R 34 links to each other, and the pulse voltage DRIVER2 behind the output frequency division.
Further, described the second driving circuit for generating also comprises: the 26 resistance R 26, the 27 resistance R 27, the 28 resistance R 28, the 29 resistance R 29, the 3rd triode Q3, the 4th triode Q4, the 6th capacitor C 6, the 7th capacitor C 7 and the 7th diode V70;
Described the 28 resistance R 28 resistance link to each other with the output of described the second amplifier N2, and the other end links to each other with described the 4th triode Q4 base stage;
Described the 4th triode Q4 collector electrode links to each other with an end of described the 26 resistance R 26, described the 27 resistance R 27 respectively; Grounded emitter;
Described the 26 resistance R 26 another termination power VCC;
Described the 3rd triode Q3 base stage of described the 27 resistance R 27 another terminations;
Described the 3rd triode Q3 emitter meets described power supply VCC, and collector electrode links to each other with an end of described the 29 resistance R 29; The other end of described the 29 resistance R 29 links to each other with described the 3rd amplifier N3 power access end;
An end links to each other with the other end of described the 29 resistance R 29 after described the 6th capacitor C 6, the 7th capacitor C 7 and the 7th diode V70 parallel connection; Other end ground connection.
Wherein, described output circuit comprises: the 5th diode V50 and the 6th diode V60;
Pulse voltage DRIVER1 behind the anodal input of described the 5th diode V50 frequency division;
Pulse voltage DRIVER2 behind the anodal input of described the 6th diode V60 frequency division;
Described the 5th diode V50 negative pole is exported total driving pulse voltage DRIVER with after described the 6th diode V60 negative pole is in parallel.
Specific implementation principle below in conjunction with 2 pairs of realization circuit of the present invention of accompanying drawing is explained in detail:
At first provide one to add positive voltage V1 to circuit, described positive voltage V1 is above-described DC input voitage namely, and V1 is through resistance R 14, enter the positive input terminal of amplifier N1 after R10 dividing potential drop and the R15 current limliting, V1 enters the negative input end of N1, resistance R 15, R17 through a RC charging circuit, R6, R3, V1 and amplifier N1 have formed a basic comparison circuit, namely when positive input voltage during greater than the negative input voltage, amplifier output high level, otherwise output low level then.When circuit is started working, because this moment, positive input terminal was higher than negative input end voltage, amplifier output this moment high level, then V1 is through R50, the RC charging circuit charging that C 3 forms, the negative input voltage raises gradually, when being charged to negative voltage and equaling positive phase voltage, amplifier output low level, i.e. the circuit impulse wave T1 that to be output as a high level lasting time be t1.Wherein t1 can pass through divider resistance R14, and R10 and RC charging circuit parameter are regulated; When T1 was high level, NPN managed the base voltage of Q2 greater than emitter voltage, the Q2 conducting, the base voltage of PNP pipe Q1 is less than emitter voltage, the Q1 conducting, this moment, external input voltage VCC produced V2 through divider resistance R19, and V2 is as the supply power voltage of amplifier N2 and N4.Need to prove that amplifier N2 described herein and N4 can be integrated on the chip, like this, the feeder ear of described amplifier N2 and N4 and earth terminal can adopt same feeder ear and the earth terminal on the described chip.
V2 is through divider resistance R22, after R23 dividing potential drop and the R24 current limliting, be input to the positive input terminal of amplifier N2, V2 is through R21, and the charging circuit that C5 forms enters the negative input end of N2, resistance R 24, R25, R20 and amplifier N2 form a typical comparison circuit, and the principle that produces with T1 is identical, and this moment, amplifier N2 produced the impulse wave T2 that high level lasting time is t2; V2 is through divider resistance R4, and R11 enters by R1, R5,, R2, R9, R7, C2, V2, R13, R18, V30, the square wave circuit for generating that N4 forms, namely enter amplifier N4 positive input terminal.When amplifier N4 output voltage greater than through the partial pressure value of R4, two resistance of R11 the time, V30 conducting and V20 cut-off, the reverse charging time constant is the product of R18 and C2, when output voltage passes through the partial pressure value of R4, two resistance of R11 less than V30, V20 conducting and V30 cut-off, the reverse charging time constant is the product of R13 and C2.Choose the different duty ratios that drive DRIVER1 that just can change from the ratio of R18 of R13, by changing resistance R 13, the value of R18 and capacitor C 2 can change the cycle that drives DRIVER1; When T2 was high level, NPN managed the base voltage of Q4 greater than emitter voltage in addition, the Q4 conducting, and the base voltage of PNP pipe Q3 is less than emitter voltage, the Q3 conducting, this moment, external input voltage VCC produced V3 through divider resistance R29, and V3 is as the supply power voltage of amplifier N3, V3 is through divider resistance R32 in addition, and R36 enters by R30, R35, R33, R31, R37, C8, V80, R38, the square wave circuit for generating that V90, N3 form namely enters into the positive input terminal of described amplifier N3.When amplifier N3 output voltage greater than through R32, during the partial pressure value of two resistance of R36, V90 conducting and V80 cut-off, the reverse charging time constant is the product of R38 and C8, when output voltage passes through R324 less than V3, during the partial pressure value of two resistance of R36, V80 conducting and V90 cut-off, the reverse charging time constant is the different duty ratios that drive DRIVER2 that just can change of ratio that R37 and the product of C8 are chosen R37 and R38, by changing resistance R 37, the value of R38 and capacitor C 8 can change the cycle that drives DRIVER2, DRIVER1 and DRIVER2 are by two diode V50, V60 produces and drives DRIVER, when DRIVER1 is high level, and diode V50 conducting, when DRIVER2 is high level, the V60 conducting, namely as long as there is one to be high level among DRIVER1 and the DRIVER2, DRIVER namely exports high level.
When input direct voltage INPUT, through a switching tube S1, DRIVER is as the drive control signal of this switching tube, this moment, output voltage OUTPUT was that INPUT is through the waveform after the copped wave, as shown in Figure 3, the arcing phenomenon that has produced when namely having realized preventing direct current interruption has very large practicality so this circuit is used in the direct current interruption of photovoltaic DC-to-AC converter.
A kind of pulse-width modulation circuit for direct current interruption that the embodiment of the invention provides drives circuit for generating, second by the first pulse generating circuit, the second pulse generating circuit, first and drives circuit for generating and output circuit; Wherein, described the first pulse generating circuit is used for DC input voitage is converted into the pulse voltage that pulse duration is T1; Described the second pulse generating circuit is converted into the pulse voltage that pulse duration is T2 for the pulse voltage that with pulse duration is T1; Described first drives circuit for generating, carry out frequency division for the pulse voltage that with described pulsewidth is T1 and process, and the pulse voltage DRIVER1 behind the frequency division exports to output circuit; Described second drives circuit for generating, carry out frequency division for the pulse voltage that with described pulsewidth is T2 and process, and the pulse voltage DRIVER2 behind the frequency division exports to output circuit; Described output circuit, be used for the pulse voltage DRIVER1 of described the first driving circuit for generating output and the pulse voltage DRIVER2 of described the second driving circuit for generating output are exported processing, export total driving pulse voltage DRIVER, the high direct voltage part that prevents photovoltaic DC-to-AC converter breaks down or other emergencies produce the high-voltage arc discharge phenomenon need to turn-off the time at circuit, realizes timely direct current interruption.
The above; be the specific embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion by described protection range with claim.
Claims (7)
1. a pulse-width modulation circuit that is used for direct current interruption is characterized in that, comprising: the first pulse generating circuit, the second pulse generating circuit, first drive circuit for generating, second and drive circuit for generating and output circuit;
Wherein, described the first pulse generating circuit is used for DC input voitage is converted into the pulse voltage that pulse duration is T1;
Described the second pulse generating circuit is converted into the pulse voltage that pulse duration is T2 for the pulse voltage that with pulse duration is T1;
Described first drives circuit for generating, carry out frequency division for the pulse voltage that with described pulsewidth is T1 and process, and the pulse voltage DRIVER1 behind the frequency division exports to output circuit;
Described second drives circuit for generating, carry out frequency division for the pulse voltage that with described pulsewidth is T2 and process, and the pulse voltage DRIVER2 behind the frequency division exports to output circuit;
Described output circuit is used for the pulse voltage DRIVER1 of described the first driving circuit for generating output and the pulse voltage DRIVER2 of described the second driving circuit for generating output are exported processing, exports total driving pulse voltage DRIVER.
2. the pulse-width modulation circuit for direct current interruption according to claim 1, it is characterized in that, described the first pulse generating circuit comprises: the 3rd resistance R 3, the six resistance R 6, the ten resistance R 10, the 14 resistance R 14, the 15 resistance R 15, the 17 resistance R 17, the 50 resistance R 50, the 3rd capacitor C 3, the first amplifier N1 and the first diode V10;
Described the 14 resistance R 14 1 termination DC input voitage V1, the other end links to each other with described the 15 resistance R 15; The positive input terminal of described the first amplifier N1 of described the 15 resistance R 15 another terminations;
Described the 50 resistance R 50 1 termination DC input voitage, the other end links to each other with described the 17 resistance R 17; The negative input end of described the first amplifier N1 of described the 17 resistance R 17 another terminations;
Described the tenth resistance R 10 1 ends link to each other other end ground connection with described the 14 resistance R 14 other ends;
Described the 3rd capacitor C 3 one ends link to each other other end ground connection with described the 50 resistance R 50 other ends;
Described the 3rd resistance R 3 one ends link to each other the positive input terminal of described the first amplifier N1 of another termination with the first diode V10 is anodal; Described the first diode V10 negative pole links to each other with the output of described the first amplifier N1;
Between the positive input terminal and output of 6 parallel connections of described the 6th resistance R and described the first amplifier N1;
The power access end of described the first amplifier N1 and described DC input voitage V1 join.
3. the pulse-width modulation circuit for direct current interruption according to claim 2, it is characterized in that described the second pulse generating circuit comprises: the 16 resistance R 16, the second triode Q2, the 8th resistance R 8, the 12 resistance R 12, the first capacitor C 1, the first triode Q1, the 19 resistance R 19, the 20 resistance R 20, the 21 resistance R 21, the 4th capacitor C 4, the 5th capacitor C 5, the 4th voltage-stabiliser tube V40, the 23 resistance R 23, the 22 resistance R 22, the 24 resistance R 24, the 25 resistance R 25, the second amplifier N2;
Described the 16 resistance R 16 1 ends link to each other with the output of described the first amplifier N1, and the other end links to each other with the base stage of described the second triode Q2;
The grounded emitter of described the second triode Q2, collector electrode link to each other with an end of described the 8th resistance R 8 and described the 12 resistance R 12 respectively;
Between the emitter and collector electrode of 1 parallel connection of described the first capacitor C and described the second triode Q2;
The other end of described the 8th resistance R 8 links to each other with the emitter of described the first triode;
The other end of described the 12 resistance R 12 links to each other with the base stage of described the first triode;
The collector electrode of described the first triode links to each other with an end of described the 19 resistance;
The other end of described the 19 resistance respectively with described the 21 resistance R 21, described the 4th capacitor C 4, the negative pole of described the 4th voltage-stabiliser tube V40 links to each other with an end of described the 23 resistance R 23;
The other end of described the 21 resistance R 21 respectively with described the 5th capacitor C 5, an end of described the 25 resistance R 25 links to each other; The other end ground connection of described the 5th capacitor C 5; The negative input end of the described second amplifier N2 of another termination of described the 25 resistance R 25 links to each other;
Described the 4th capacitor C 4 other end ground connection;
The plus earth of described the 4th voltage-stabiliser tube V40;
The other end of described the 23 resistance R 23 links to each other with an end of described the 22 resistance R 22 and described the 24 resistance R 24 respectively;
The other end ground connection of described the 22 resistance R 22;
The other end of described the 24 resistance R 24 links to each other with the positive input terminal of described the second amplifier N2;
Described the 20 resistance R 20 is connected in parallel between the positive input terminal and output of described the second amplifier N2.
4. the pulse-width modulation circuit for direct current interruption according to claim 3, it is characterized in that described first drives circuit for generating comprises: the 4th resistance R 4, the 11 resistance R 11, the first resistance R 1, the 5th resistance R 5, the second resistance R 2, the 9th resistance R 9, four high guaily unit N4, the second capacitor C 2, the second diode V20, the 13 resistance R 13, the 3rd diode V30, the 18 resistance R 18 and the 7th resistance R 7;
One end of described the 4th resistance R 4 links to each other with second source V2, and the other end links to each other with described the 11 resistance R 11, described the first resistance R 1, described the second capacitor C 2 respectively;
Described the 11 resistance R 11 other end ground connection;
Described the first resistance R 1 other end links to each other with described the second resistance R 2, described the 5th resistance R 5 respectively; Described the 5th resistance R 5 other ends link to each other with the positive input terminal of described four high guaily unit N4; Described the second resistance R 2 other ends link to each other with described the 7th resistance R 7 one ends; Described the 7th resistance R 7 other ends of stating link to each other with described four high guaily unit N4 output;
Described the second capacitor C 2 other ends link to each other with described the 9th resistance R 9, described the second diode V20 positive pole, described the 18 resistance R 18 respectively; The other end of described the 9th resistance R 9 links to each other with described four high guaily unit N4 negative input end; Described the second diode V20 negative pole links to each other with described the 13 resistance R 13 1 ends; The other end of described the 18 resistance R 18 links to each other with described the 3rd diode V30 negative pole; The other end of described the 13 resistance R 13 is anodal with described the 3rd diode V30, an end of described the 7th resistance R 7 links to each other, and the pulse voltage DRIVER1 behind the output frequency division.
5. the pulse-width modulation circuit for direct current interruption according to claim 4, it is characterized in that described second drives circuit for generating comprises: the 32 resistance R 32, the 36 resistance R 36, the 30 resistance R 30, the 33 resistance R 33, the 31 resistance R 31, the 35 resistance R 35, the 3rd amplifier N3, the 8th capacitor C 8, the 8th diode V80, the 37 resistance R 37, the 9th diode V90, the 38 resistance R 38 and the 34 resistance R 34;
One end of described the 32 resistance R 32 links to each other with second source V2, and the other end links to each other with described the 36 resistance R 36, described the 30 resistance R 30, described the 8th capacitor C 8 respectively;
Institute's the 36 resistance R 36 other end ground connection;
Described the 30 resistance R 30 other ends link to each other with described the 31 resistance R 31, described the 33 resistance R 33 respectively; Described the 33 resistance R 33 other ends link to each other with the positive input terminal of described the 3rd amplifier N3; Described the 31 resistance R 31 other ends link to each other with described the 34 resistance R 34 1 ends; Described the 34 resistance R 34 other ends of stating link to each other with described the 3rd amplifier N3 output;
Described the 8th capacitor C 8 other ends link to each other with described the 35 resistance R 35, described the 8th diode V80 positive pole, described the 38 resistance R 38 respectively; The other end of described the 35 resistance R 35 links to each other with described the 3rd amplifier N3 negative input end; Described the 8th diode V80 negative pole links to each other with described the 37 resistance R 37 1 ends; The other end of described the 38 resistance R 38 links to each other with described the 9th diode V90 negative pole; The other end of described the 37 resistance R 37 is anodal with described the 9th diode V90, an end of described the 34 resistance R 34 links to each other, and the pulse voltage DRIVER2 behind the output frequency division.
6. the pulse-width modulation circuit for direct current interruption according to claim 5, it is characterized in that described second drives circuit for generating also comprises: the 26 resistance R 26, the 27 resistance R 27, the 28 resistance R 28, the 29 resistance R 29, the 3rd triode Q3, the 4th triode Q4, the 6th capacitor C 6, the 7th capacitor C 7 and the 7th voltage-stabiliser tube V70;
Described the 28 resistance R 28 resistance link to each other with the output of described the second amplifier N2, and the other end links to each other with described the 4th triode Q4 base stage;
Described the 4th triode Q4 collector electrode links to each other with an end of described the 26 resistance R 26, described the 27 resistance R 27 respectively; Grounded emitter;
Described the 26 resistance R 26 another termination power VCC;
Described the 3rd triode Q3 base stage of described the 27 resistance R 27 another terminations;
Described the 3rd triode Q3 emitter meets described power supply VCC, and collector electrode links to each other with an end of described the 29 resistance R 29; The other end of described the 29 resistance R 29 links to each other with described the 3rd amplifier N3 power access end;
An end links to each other with the other end of described the 29 resistance R 29 after described the 6th capacitor C 6, the 7th capacitor C 7 and the 7th voltage-stabiliser tube V70 parallel connection; Other end ground connection.
7. the described pulse-width modulation circuit for direct current interruption of any one in 6 according to claim 1 is characterized in that described output circuit comprises: the 5th diode V50 and the 6th diode V60;
Pulse voltage DRIVER1 behind the anodal input of described the 5th diode V50 frequency division;
Pulse voltage DRIVER2 behind the anodal input of described the 6th diode V60 frequency division;
Described the 5th diode V50 negative pole is exported total driving pulse voltage DRIVER with after described the 6th diode V60 negative pole is in parallel.
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| CN201110240130.9A CN102957336B (en) | 2011-08-19 | 2011-08-19 | Pulse width modulation circuit for direct-current broken circuit |
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| CN201110240130.9A CN102957336B (en) | 2011-08-19 | 2011-08-19 | Pulse width modulation circuit for direct-current broken circuit |
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| CN102957336B CN102957336B (en) | 2015-01-21 |
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Cited By (1)
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| CN104682486A (en) * | 2013-11-29 | 2015-06-03 | 西门子公司 | Frequency generation for a resonance converter |
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| CN101237207A (en) * | 2007-02-01 | 2008-08-06 | 三洋电机株式会社 | Integrated circuit for driving motor |
| CN101127286A (en) * | 2007-07-17 | 2008-02-20 | 西安交通大学 | Permanent magnetic machine controller based on pulse modulation technology |
| CN102111134A (en) * | 2009-12-25 | 2011-06-29 | 产晶集成电路股份有限公司 | Drive device of pulse width modulation step wave and sine wave |
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| CN102957336B (en) | 2015-01-21 |
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