CN102956442A

CN102956442A - Integrated circuit (IC) wafer edge processing method

Info

Publication number: CN102956442A
Application number: CN2012104795475A
Authority: CN
Inventors: 吾勇军; 陈锋; 方强
Original assignee: WANXIANG SILICON-PEAK ELECTRINICS Co Ltd
Current assignee: WANXIANG SILICON-PEAK ELECTRINICS Co Ltd
Priority date: 2012-11-23
Filing date: 2012-11-23
Publication date: 2013-03-06

Abstract

The invention relates to an integrated circuit (IC) wafer edge processing method which comprises the following steps that first the IC wafer is divided into a removed layer and a reserved layer; then the edge of the removed layer is chamfered into a shape, the edge of the reserved layer is chamfered into another shape, and the shape which is chamfered on the edge of the reserved layer is symmetric relative to a plane which is arranged at half thickness of the reserved layer and is in parallel with the surface of the wafer; and a chamfer angle on the edge of the wafer, which is formed by the chamfer angle on the edge of the removed layer and that on the edge of the reserved layer is asymmetric corresponding to the plane which is arranged at half thickness of the wafer and is in parallel with the surface of the wafer. Due to the adoption of the IC wafer edge processing method, the phenomena of side breakage and dark fringe chips caused by stress in the processing and follow-up procedures of the wafer are reduced, the finished product rate is improved, and the cost is reduced.

Description

A kind of IC level silicon wafer edge processing method

Technical field

The present invention relates to a kind of IC level silicon wafer edge processing method.

Background technology

At present, to cut into silicon chip through the IC of round as a ball processing grade silicon rod, because the silicon chip edge surface ratio is more coarse, exist corner angle, mao mao to sting, collapse the defectives such as limit, even also crack and other defect can appear, cause the silicon chip edge mechanical strength to reduce, also have particle contaminant, therefore just need to be with the silicon chip edge chamfering to eliminate described defective.The processing of existing IC level silicon wafer edge is generally symmetrical chamfering, but after the diffusion layer of IC level silicon wafer one side was removed, edge chamfer became asymmetric chamfering, if continue to adopt the method chamfering of symmetrical chamfering, because its stress is large, easily cause collapsing limit, dark line fragment.

Summary of the invention

The purpose of this invention is to provide and after diffusion layer is removed, to prevent from adding a kind of IC level silicon wafer edge processing method that man-hour occurs collapsing limit and dark line fragment.

The technical scheme that the present invention takes is: a kind of IC level silicon wafer edge processing method, it is characterized in that first the IC level silicon wafer being divided into removal layer and retaining layer two parts, then the edge chamfer that will remove layer becomes a kind of shape, the edge chamfer of retaining layer is become another shape, and the formed shape of retaining layer edge chamfer is with respect to being positioned at retaining layer one half thickness place and being parallel to the plane symmetry of silicon chip surface; To remove silicon chip edge chamfering that layer edge chamfer and formed retaining layer edge chamfer consist of asymmetric corresponding to being positioned at silicon chip one half thickness place and being parallel to the plane of silicon chip surface by formed.

Described IC level silicon wafer edge processing method, the machined parameters that it is necessary and numerical value are: the summit of silicon chip edge chamfering be the retaining layer edge chamfer terminal and perpendicular to the distance of the straight line of silicon chip surface in 130 ± 100 μ m scopes, the summit of silicon chip edge chamfering be remove layer edge chamfer terminal with silicon chip surface intersection point and perpendicular to the vertical range of the straight line of silicon chip surface in 500 ± 100 μ m scopes, the extended line of silicon chip edge chamfering and the angle of silicon chip surface are in 30 ± 2 ° of scopes.

Adopt the present invention, because the cutting loss layer that the IC level silicon wafer is removed respectively silicon chip surface through two-sided lapping is namely removed layer, after namely removing layer through a side diffusion layer of diffusion technology and removal again, the silicon chip of this moment only comprises retaining layer, at this moment silicon chip edge chamfering is exactly the retaining layer edge chamfer, and the retaining layer edge chamfer is with respect to being positioned at retaining layer one half thickness place and being parallel to the plane symmetry of silicon chip surface, therefore, the retaining layer edge chamfer is a kind of symmetrical chamfering, so, the reason of stress causes in the processing of silicon chip and subsequent handling collapses the limit, dark line fragment phenomenon reduces, and has improved rate of finished products, has reduced cost.

Description of drawings

Fig. 1 is schematic diagram of the present invention.

Sequence number among the figure represents: remove layer 1, removal layer 25, retaining layer 6, removal layer 37, remove a layer edge chamfer 1, retaining layer edge chamfer 9 and remove a layer edge chamfer 2 10.

Embodiment

The invention will be further described below in conjunction with specific embodiment.

With reference to Fig. 1, silicon single crystal bar is in advance round as a ball, then perpendicular to the cutting of monocrystal rod axis, obtain disc-shaped IC level silicon wafer, thickness is 590 ± 10 μ m, this IC level silicon wafer is divided into removes layer 1, removes layer 25, removes layer 37 and retaining layer 6; To remove layer 1, remove layer 25, remove layer 37 chamfering and become a kind of shape, and such as the oblique chamfering that usually adopts among the figure, namely remove layer edge chamfer 1 and remove a layer edge chamfer 2 10; Retaining layer 6 edge chamfers are become another kind of shape, and such as the R type chamfering among the figure, namely the retaining layer edge chamfer 9; And formed retaining layer edge chamfer 9 is with respect to being positioned at retaining layer 6 one half thickness places and being parallel to the plane symmetry of silicon chip surface; By formed remove layer edge chamfer 1 and remove silicon chip edge chamfering that layer edge chamfer 2 10 and formed retaining layer edge chamfer 9 consist of asymmetric corresponding to being positioned at silicon chip one half thickness place and being parallel to the plane of silicon chip surface.Wherein, the machined parameters and the numerical value that adopt the mould identical with described silicon chip edge chamfer shape to process simultaneously to remove layer edge chamfer 1 and remove layer edge chamfer 2 10 and retaining layer edge chamfer 9. necessity are: the summit of silicon chip edge be retaining layer edge chamfer 9 ends (removing layer edge chamfer 2 10 tops) and perpendicular to the straight line of silicon chip surface apart from B in 130 ± 100 μ m scopes, the summit of silicon chip edge chamfering to " cross to remove the terminal intersection point with silicon chip surface of layer edge chamfer 8; and perpendicular to silicon chip surface " the distance A of straight line in 500 ± 100 μ m scopes, the extended line of silicon chip edge chamfering and the angle theta of silicon chip surface are in 30 ± 2 ° of scopes.

In above-mentioned, owing to adopting the IC level silicon wafer of the processing of the asymmetric edge of IC level silicon wafer processing method, remove respectively the cutting loss layer of silicon chip surface through two-sided lapping and namely remove layer removal layer 1, remove layer 37, after namely removing layer 25 through a side diffusion layer of diffusion technology and removal again, the silicon chip of this moment only comprises retaining layer 6, at this moment silicon chip edge chamfering is exactly retaining layer edge chamfer 9, and retaining layer edge chamfer 9 is with respect to being positioned at retaining layer 6 one half thickness places and being parallel to the plane symmetry of silicon chip surface, therefore, retaining layer edge chamfer 9 is a kind of symmetrical chamferings, so, the reason of stress causes in the processing of silicon chip and subsequent handling collapses the limit, dark line fragment phenomenon reduces, improve rate of finished products, reduced cost.

Claims

1. IC level silicon wafer edge processing method, it is characterized in that first the IC level silicon wafer being divided into removal layer and retaining layer two parts, then the edge chamfer that will remove layer becomes a kind of shape, the edge chamfer of retaining layer is become another shape, and the formed shape of retaining layer edge chamfer is with respect to being positioned at retaining layer one half thickness place and being parallel to the plane symmetry of silicon chip surface; To remove silicon chip edge chamfering that layer edge chamfer and formed retaining layer edge chamfer consist of asymmetric corresponding to being positioned at silicon chip one half thickness place and being parallel to the plane of silicon chip surface by formed.

2. IC level silicon wafer according to claim 1 edge processing method, it is characterized in that machined parameters and numerical value that it is necessary are: the summit of silicon chip edge chamfering be the retaining layer edge chamfer terminal and perpendicular to the distance of the straight line of silicon chip surface in 130 ± 100 μ m scopes, the summit of silicon chip edge chamfering be remove layer edge chamfer terminal with silicon chip surface intersection point and perpendicular to the vertical range of the straight line of silicon chip surface in 500 ± 100 μ m scopes, the extended line of silicon chip edge chamfering and the angle of silicon chip surface are in 30 ± 2 ° of scopes.