CN102956271B - 基于宽i/o dram的2.5d/3d系统芯片的dram修复架构 - Google Patents

基于宽i/o dram的2.5d/3d系统芯片的dram修复架构 Download PDF

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CN102956271B
CN102956271B CN201210291516.7A CN201210291516A CN102956271B CN 102956271 B CN102956271 B CN 102956271B CN 201210291516 A CN201210291516 A CN 201210291516A CN 102956271 B CN102956271 B CN 102956271B
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controller
dynamic ram
repair
reparation
dice
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CN102956271A (zh
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桑迪·库马·戈埃尔
黄智强
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

本发明涉及基于宽I/O？DRAM的2.5D/3D系统芯片的DRAM修复架构。2.5D或3D修复架构包括逻辑管芯和存储器管芯。在2.5D架构中，逻辑管芯和存储器管芯安装在中介层上。在3D架构中，存储器管芯安装在逻辑管芯上。逻辑具有被处理器测试外壳包裹的控制逻辑。处理器测试外壳启动控制逻辑的测试部件。控制逻辑进一步包括宽输入/输出控制器、内置修复分析器(BIRA)以及修复控制器。利用修复架构的方法提供了修复存储器设备的故障列和行的步骤。

Description

基于宽I/O DRAM的2.5D/3D系统芯片的DRAM修复架构
本申请要求于2011年8月17日提交的标题为“DRAMRepairArchitectureAndMethodForWideIODRAMBased2.5D/3DSystemChips”的美国临时专利申请第61/524,548号的优先权。
技术领域
本公开总体上涉及电子电路领域。具体地，本公开包括2.5D/3D系统芯片中动态随机存取存储器(DRAM)的修复过程和架构。
背景技术
传统的二维(2D)电脑芯片、处理器和随机存取存储器(RAM)设置在同一个平面内且通过封装衬底相互连接。
但是，随着电子工业的演变，如今已经推出第三维-宽输入/输出DRAM并通过中介层(2.5D)将其连接在处理器(3D)的顶部或靠近处理器。因此，第三维的放置方法降低了两个零件间的互连电容。
发明内容
在一个实施例中，设备包括宽幅输入/输出控制器、内置修复分析器(BIRA)和修复控制器。宽幅输入/输出控制器通过物理层与DRAM通信。内置修复分析器收集来自宽幅输入/输出控制器的通讯故障数据并分析该故障数据以确定DRAM通道中DRAM的故障列和行。修复控制器生成修复DRAM的故障列和行的指令。
该设备进一步包括：修复定序器，用于按顺序排列所生成的修复指令。
该设备进一步包括：通用输入/输出(GPIO)管脚，被配置成接收来自修复控制器的修复指令。
其中，修复控制器是eFUSE修复控制器，修复定序器是eFUSE修复定序器。
该设备进一步包括：控制逻辑，被配置为片上系统(SOC)。
在另一个实施例中，在中介层上安装逻辑管芯和存储器管芯。存储器管芯包括DRAM通道。逻辑具有被处理器测试外壳包裹的控制逻辑。处理器测试外壳能够启动控制逻辑的测试部件。控制逻辑进一步包括宽幅输入/输出控制器、BIRA和修复控制器。宽幅输入/输出控制器通过物理层与DRAM通道通信。BIRA收集来自宽幅输入/输出控制的通信故障数据并分析该故障数据以确定DRAM通道中DRAM的故障列和行。修复控制器生成修复DRAM的故障列和行的指令。
在另一个实施例中，在逻辑管芯上安装有存储器管芯。存储器管芯具有DRAM通道。逻辑具有被处理器测试外壳包裹的控制逻辑。处理器测试外壳能够启动控制逻辑的测试部件。控制逻辑进一步包括宽幅输入/输出控制器、BIRA和修复控制器。宽幅输入/输出控制器通过物理层与DRAM通信。BIRA收集来自宽幅输入/输出控制器的通信故障数据且分析该故障数据以确定DRAM通道中DRAM的故障列和行。修复控制器生成修复DRAM的故障列和行的指令。
该设备进一步包括：修复定序器，用于按顺序排列所生成的修复指令。
该设备进一步包括：通用输入/输出(GPIO)管脚，被配置成接收来自修复控制器的修复指令。
其中，修复控制器是eFUSE修复控制器，修复定序器是eFUSE修复定序器。
该设备进一步包括中介层和封装衬底，其中，存储器管芯安装在中介层上，中介层设置在封装衬底上。
其中，逻辑管芯进一步安装在中介层上。
其中，存储器管芯安装在逻辑管芯上。
该设备进一步包括封装衬底，其中，逻辑管芯安装在封装衬底上。
其中，控制逻辑是片上系统，并且逻辑管芯进一步包括：边界扫描测试外壳，被配置成包裹处理器测试外壳，边界扫描测试外壳被配置成启动电路板的测试部件，其中，处理器测试外壳是电气和电子工程师协会(IEEE)标准1500测试外壳且边界扫描测试外壳是电气和电子工程师协会标准1149.1测试外壳。
在另一个实施例中，提供一种方法。该方法收集和分析通信故障数据且生成修复DRAM的故障列和行的指令。该方法包括以下步骤：宽幅输入/输出控制器通过物理层与DRAM通信；BIRA收集来自宽幅输入/输出控制器的通信故障数据；BIRA分析通信故障数据以确定DRAM通道中DRAM的故障列和行；以及生成修复DRAM的故障列和行的指令。
其中，使用修复控制器生成修复指令。
该方法进一步包括使用修复定序器按顺序排列所生成的修复指令。
该方法进一步包括：使用通用输入/输出(GPIO)管脚接收来自修复控制器的修复指令。
其中，修复控制器是eFUSE修复控制器，修复定序器是eFUSE修复定序器。
其中，DRAM通道设置在存储器管芯中，存储器管芯设置在中介层上。
附图说明
图1示出了3D系统实施例。
图2示出了2.5D系统实施例。
图3详细描述了单个宽输入/输出DRAM管芯的修复架构的实施方式。
图4示出了构成宽输入/输出DRAM晶体的修复架构的一部分的逻辑到数据适配器和测试外壳指令寄存器的结构图。
图5示出了构成宽输入/输出堆叠的DRAM晶体的修复架构的处理器的实施方式。
图6示出了收集和分析通信故障数据且生成修复指令的方法。
具体实施方式
本公开的一个方面包括堆叠管芯的修复架构。堆叠管芯包括宽幅输入/输出DRAM和其他逻辑管芯。这样的修复架构能够启动各自的管芯修复以及管芯间的互连修复。一些修复架构的实施例符合2.5D/3D管芯的板级集成(board-levelintegration)的电气和电子工程师协会(IEEE)1149.1号“标准测试存取口及边界扫描架构”。IEEE1149.1的行业标准名称是联合测试行动小组(JTAG)。
当重新使用片上系统(SOC)修复基础结构和修复方式时，实施例会对单位面积成本最小化。但是其他实施例与宽I/ODRAM边界扫描控制连接并无需使用测试访问端口(TAP)控制器进行注册。
后面的多个部分中均详细描述了下列实施例。此外，采用已知的互补金属氧化物半导体(CMOS)晶体管的集成电路(IC)技术，在单晶硅半导体衬底上形成构成下列实施例的每个功能块的电路部件。
参考附图描述本公开的实施例。在描述实施例的所有附图中，通常，相同的参考数字用于指代相同的部件，因此本文不再赘述。
参看根据本公开的实施例构造和操作的如图1所示的3D芯片系统1000的实施例。3D芯片系统是其内部部件以三维(长、宽和高)形式相互连接的系统。如图1所示，在3D芯片系统1000中，通过微凸块1250将宽I/ODRAM1300堆叠在处理器1200的顶部。类似地，通过C4凸块(焊料凸块1150将处理器1200堆叠在封装衬底1100上。采用球栅阵列(BGA)1050实现对封装衬底1100的表面安装。如下所述，3D芯片系统1000中可以使用本公开的修复实施例。
同样地，如图2所示，结合根据本公开的实施例构造和操作的2.5D芯片系统2000，可以使用修复实施例。2.5D芯片系统是其内部部件(如，处理器2200和DRAM2300)通过中介层2400以三维的形式连接到封装衬底2100的系统。如图2所示，通过微凸块2250，部件处理器2200和DRAM2300堆叠在中介层2400的顶部。同样地，通过C4凸块2150，中介层2400堆叠在封装衬底2100上。采用球栅阵列2050实现对封装衬底2100的表面安装。如下所述，2.5D芯片系统2000中可以使用本公开的修复实施例。
图3示出了根据本公开的实施例构造和操作的单个宽输入/输出DRAM通道的修复(DFT)架构。在2.5D实施例中，逻辑管芯3200和DRAM管芯3300安装在中介层3400上。本领域技术人员应理解，此处描述的原理也可应用到3D实施例。
在本实施例中，逻辑管芯3200包括用处理器测试外壳(wrapper)3110包裹的处理器3500。处理器测试外壳3110是IEEE标准号1500测试外壳。处理器测试外壳3110也能包裹至少一个测试外壳寄存器3120A-B，测试外壳指令寄存器(WIR)3130和逻辑到数据适配器3140。
处理器3500包括片上系统(SOC)，宽输入/输出控制器和物理层(PHY)。图5中更为详细地描述了处理器3500。
处理器测试外壳3110能够为嵌入式内核和相关电路启动修复再用和集成。处理器测试外壳3110先解决模拟电路问题，然后集中提高片上系统的数字方面的高效修复。此外，处理器测试外壳3110具有串行和并行测试访问机制(TAM)以及一组丰富的用于修复内核、片上系统互连、和电路的指令。此外，处理器测试外壳3110包括能够启动内核隔离和保护的部件。
在一些实施例中，测试外壳指令寄存器3130是IEEE1500号测试外壳指令寄存器。图4示出了根据本公开的实施例构造和操作的测试外壳指令寄存器3130和逻辑到数据适配器3140的实施方式。
重新参看图3，逻辑管芯3200进一步包括边界扫描包装3150。在一些实施例中，边界扫描测试外壳3150是启动板的部件修复的IEEE标准1149.1号测试外壳架构和访问机制。边界扫描测试外壳3150包裹处理器测试外壳3110、边界寄存器3160、边界扫描测试外壳指令寄存器3170以及任意的输入/输出焊盘3180。边界扫描测试外壳指令寄存器3170是IEEE1149.1号测试外壳指令寄存器。
由逻辑/处理器管芯3200上的控制逻辑3200控制通道选择/旁路逻辑3330和边界扫描寄存器3320。
控制逻辑3200由测试外壳指令寄存器3130控制或由顶层边界扫描测试外壳指令寄存器3170直接控制。
本领域技术人员应该理解，逻辑管芯管脚连接到中介层3100或具有边界扫描逻辑的衬底。
为了实现已知合格管芯(KGD，KnownGoodDie)修复，将逻辑测试管脚(未示出)连接到探针焊盘，且为了FT/KGS修复，将逻辑测试管脚(未示出)连接到C4凸块。
DRAM管芯3300包括DRAM3310、DRAM边界扫描寄存器3320、DRAM通道选择/旁路逻辑3330、以及输入/输出焊盘3340。DRAM通道选择/旁路逻辑3330执行为逻辑管芯3200和DRAM管芯3300之间的接口。更应该了解，可以选择单独通道用于逻辑管芯3200和DRAM管芯3300之间的互连修复。
DRAM管芯3300中每个管芯具有四个DRAM通道3310A-D，且每个通道中有四个区(bank)。每个通道3310均具有各自的边界扫描信号，而在所有的通道中只分享一个SSEN信号(全局扫描启动)。此外，DRAM管芯3300也可以包括输入/输出焊盘3340。
图5示出了根据本公开的实施例构造和操作的构成宽输入/输出堆叠DRAM管芯的修复架构的一部分的处理器3500的实施方式。本领域技术人员应理解，本文所述原理也可以应用到2.55D和3D实施例中。
如上所述，处理器3500包括片上系统3502、每个DRAM通道3310的宽输入/输出控制器3512和物理层(PHY)3514。如图5所示，处理器3500进一步包括互连结构(fabric)3510、片上内置修复分析器(BIRA)3506、修复控制器3516、修复数据寄存器3508、eFUSE修复定序器3518、和通用输入/输出(GPIO)管脚3520。下面描述了如何使用这些部件。
使用宽输入/输出控制器3512A-D，片上内置修复分析器3606能够收集每个DRAM通道3310A-D的故障数据。在一些实施例中，宽I/O控制器3512具有存储器内置自测(MBIST)能力。
一些实施例中包括一个以上的片上内置修复分析器3606。而其他实施例中包括每个宽输入/输出控制器3512A-D的内置修复分析器3506A-D。
修复控制器3516是eFUSE修复控制器。eFUSE修复控制器3516允许电脑芯片进行动态的实时重组。通过使用eFUSE修复控制器3516，可以改变正在运行中的修复数据寄存器3508和修复定序器3518以及片上电路。在一些实施例中，修复定序器3518是eFUSE修复定序器。
此外，内置修复分析器3606能够读取和修复行/列信息且生成相应的ATE的指令。eFUSE修复定序器3518通过配置的通用输入/输出管脚3520向DRAM管芯发送指令。
因此，上文描述的修复架构实施例不依赖于任何特定电路的实施方式，并且可以生成任意的修复指令。
图6示出了利用本文所述的修复架构的方法6000。在步骤块6002中，方法6000使用宽输入/输出控制器通过物理层与DRAM通道通信。在一些实施例中，DRAM通道可能位于封装衬底上的中介层上的存储器芯片中。利用本文所述的各种修复架构实施例进行方法6000。在步骤块6004中，方法6000使用内置修复分析器(BIRA)收集来自宽输入/输出控制器的通信故障数据。在步骤块6006中，方法6000分析通信故障数据以确定DRAM通道中的故障DRAM列和行。使用BIRA进行步骤6006的分析。在步骤块6008中，方法6000生成修复故障DRAM列和行的修复指令。在一些实施例中，使用修复控制器执行生成修复指令的步骤。在步骤块6010中，方法6000按顺序排列生成的修复指令。在一些实施例中，使用修复定序器进行步骤块6010的排列。在一些实施例中，修复控制器是eFUSE修复控制器，而在一些实施例中，修复定序器是eFUSE修复定序器。在一些实施例中，方法6000也包括使用GPIO接收来自修复控制器的修复指令。
上文关于实施例的描述有助于本领域的技术人员实践本发明。本领域的技术人员应理解，这些实施例的各种修改，在不使用本发明的权力的情况下，本文界定的通用原理也可以应用于其他实施例中。因此，本公开并不仅限于已示出的实施例，而在符合已公开的原理和新特征的情况下，允许更大的范围。

Claims (19)

1.一种动态随机存取存储器修复设备，包括：
多个宽输入/输出控制器，被配置成通过物理层与对应的动态随机存取存储器通道进行通信，所述宽输入/输出控制器与所述动态随机存取存储器通道一一对应；
内置修复分析器(BIRA)，被配置成收集来自所述宽输入/输出控制器的通信故障数据，并且进一步被配置成分析所述故障数据以确定所述动态随机存取存储器通道中的动态随机存取存储器的故障列和行；以及
修复控制器，被配置成生成修复所述动态随机存取存储器的故障列和行的指令；
所述动态随机存取存储器通道设置在存储器管芯中，所述存储器管芯设置在中介层上。
2.根据权利要求1所述的设备，进一步包括：
修复定序器，用于按顺序排列所生成的修复指令。
3.根据权利要求2所述的设备，进一步包括：
通用输入/输出(GPIO)管脚，被配置成接收来自所述修复控制器的修复指令。
4.根据权利要求3所述的设备，其中，所述修复控制器是eFUSE修复控制器，所述修复定序器是eFUSE修复定序器。
5.根据权利要求4所述的设备，进一步包括：
控制逻辑器，被配置为片上系统(SOC)。
6.一种动态随机存取存储器修复设备，包括：
存储器管芯，包括动态随机存取存储器通道；
逻辑管芯，包括被处理器测试外壳包裹的控制逻辑器，所述处理器测试外壳被配置成启动所述控制逻辑器的测试部件；所述控制逻辑器进一步包括：
多个宽输入/输出控制器，被配置成通过物理层与对应的所述动态随机存取存储器通道进行通信，所述宽输入/输出控制器与所述动态随机存取存储器通道一一对应；
内置修复分析器(BIRA)，被配置成收集来自所述宽输入/输出控制器的通信故障数据，并且进一步被配置成分析所述故障数据以确定所述动态随机存取存储器通道中的动态随机存取存储器的故障列和行；
修复控制器，被配置成生成修复所述动态随机存取存储器的故障列和行的指令；
中介层，所述存储器管芯安装在所述中介层上。
7.根据权利要求6所述的设备，进一步包括：
修复定序器，用于按顺序排列所生成的修复指令。
8.根据权利要求7所述的设备，进一步包括：
通用输入/输出(GPIO)管脚，被配置成接收来自所述修复控制器的修复指令。
9.根据权利要求7所述的设备，其中，所述修复控制器是eFUSE修复控制器，所述修复定序器是eFUSE修复定序器。
10.根据权利要求6所述的设备，进一步包括封装衬底，其中，所述中介层设置在所述封装衬底上。
11.根据权利要求10所述的设备，其中，所述逻辑管芯进一步安装在所述中介层上。
12.根据权利要求6所述的设备，其中，所述存储器管芯安装在所述逻辑管芯上。
13.根据权利要求12所述的设备，进一步包括封装衬底，其中，所述逻辑管芯安装在所述封装衬底上。
14.根据权利要求6所述的设备，其中，所述控制逻辑器是片上系统，并且所述逻辑管芯进一步包括：
边界扫描测试外壳，被配置成包裹所述处理器测试外壳，所述边界扫描测试外壳被配置成启动电路板的测试部件，其中，所述处理器测试外壳是电气和电子工程师协会(IEEE)标准1500测试外壳且所述边界扫描测试外壳是电气和电子工程师协会标准1149.1测试外壳。
15.一种动态随机存取存储器修复方法，包括：
使用多个宽输入/输出控制器通过物理层与对应的动态随机存取存储器通道进行通信，所述宽输入/输出控制器与所述动态随机存取存储器通道一一对应；
使用内置修复分析器(BIRA)收集来自所述宽输入/输出控制器的通信故障数据；
使用所述内置修复分析器(BIRA)分析所述通信故障数据，以确定所述动态随机存取存储器通道中的动态随机存取存储器的故障列和行；以及
生成修复指令，以修复所述动态随机存取存储器的故障列和行；
所述动态随机存取存储器通道设置在存储器管芯中，所述存储器管芯设置在中介层上。
16.根据权利要求15所述的方法，其中，使用修复控制器生成所述修复指令。
17.根据权利要求16所述的方法，进一步包括使用修复定序器按顺序排列所生成的修复指令。
18.根据权利要求17所述的方法，进一步包括：使用通用输入/输出(GPIO)管脚接收来自所述修复控制器的修复指令。
19.根据权利要求18所述的方法，其中，所述修复控制器是eFUSE修复控制器，所述修复定序器是eFUSE修复定序器。
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