CN102955865A - 芯片物理版图的黑盒逻辑验证方法 - Google Patents
芯片物理版图的黑盒逻辑验证方法 Download PDFInfo
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- CN102955865A CN102955865A CN2011102390376A CN201110239037A CN102955865A CN 102955865 A CN102955865 A CN 102955865A CN 2011102390376 A CN2011102390376 A CN 2011102390376A CN 201110239037 A CN201110239037 A CN 201110239037A CN 102955865 A CN102955865 A CN 102955865A
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104424056A (zh) * | 2013-08-19 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | 版图数据的层次检查方法 |
CN106815384A (zh) * | 2015-12-02 | 2017-06-09 | 北京华大九天软件有限公司 | 一种lef库与gds库障碍图层对比检查的方法 |
CN112257382A (zh) * | 2020-10-29 | 2021-01-22 | 海光信息技术股份有限公司 | 用于芯片设计的物理验证方法、系统、设备以及存储介质 |
CN117391038A (zh) * | 2023-10-23 | 2024-01-12 | 北京市合芯数字科技有限公司 | 芯片版图的金属栈空间信息划分方法及芯片 |
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- 2011-08-19 CN CN201110239037.6A patent/CN102955865B/zh active Active
Patent Citations (7)
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US20060225017A1 (en) * | 2005-03-16 | 2006-10-05 | Nec Corporation | Integrated circuit layout design system, and method thereof, and program |
US20060259883A1 (en) * | 2005-05-10 | 2006-11-16 | Texas Instruments Inc. | Distributed element generator, method of generating distributed elements and an electronic design automation tool employing the same |
CN101162476A (zh) * | 2006-10-13 | 2008-04-16 | 上海华虹Nec电子有限公司 | 实现黑盒子lvs的方法 |
JP2009146054A (ja) * | 2007-12-12 | 2009-07-02 | Toshiba Corp | 半導体集積回路のレイアウト作成装置及びレイアウト作成方法 |
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US20110119645A1 (en) * | 2009-11-17 | 2011-05-19 | Fujitsu Semiconductor Limited | Design verification device |
CN102117350A (zh) * | 2009-12-31 | 2011-07-06 | 中国科学院微电子研究所 | 多线网之间物理短路位置的自动定位方法 |
Non-Patent Citations (1)
Title |
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于涛等: "基于Calibre工具的SoC芯片的物理验证", 《科学技术与工程》 * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104424056A (zh) * | 2013-08-19 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | 版图数据的层次检查方法 |
CN104424056B (zh) * | 2013-08-19 | 2017-12-05 | 上海华虹宏力半导体制造有限公司 | 版图数据的层次检查方法 |
CN106815384A (zh) * | 2015-12-02 | 2017-06-09 | 北京华大九天软件有限公司 | 一种lef库与gds库障碍图层对比检查的方法 |
CN112257382A (zh) * | 2020-10-29 | 2021-01-22 | 海光信息技术股份有限公司 | 用于芯片设计的物理验证方法、系统、设备以及存储介质 |
CN112257382B (zh) * | 2020-10-29 | 2023-07-21 | 海光信息技术股份有限公司 | 用于芯片设计的物理验证方法、系统、设备以及存储介质 |
CN117391038A (zh) * | 2023-10-23 | 2024-01-12 | 北京市合芯数字科技有限公司 | 芯片版图的金属栈空间信息划分方法及芯片 |
CN117391038B (zh) * | 2023-10-23 | 2024-05-14 | 北京市合芯数字科技有限公司 | 芯片版图的金属栈空间信息划分方法及芯片 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140103 |
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