CN102955314A - TFT (Thin Film Transistor) array substrate, preparation method and display device - Google Patents
TFT (Thin Film Transistor) array substrate, preparation method and display device Download PDFInfo
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- CN102955314A CN102955314A CN2012103967690A CN201210396769A CN102955314A CN 102955314 A CN102955314 A CN 102955314A CN 2012103967690 A CN2012103967690 A CN 2012103967690A CN 201210396769 A CN201210396769 A CN 201210396769A CN 102955314 A CN102955314 A CN 102955314A
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Abstract
The invention discloses a TFT (Thin Film Transistor) array substrate, a preparation method and a display device. On the basis of a conventional TFT structure, a second grid above a semiconductor layer is added on a passivation layer of the TFT; when the TFT works and after the newly added second grid is powered on, a current channel is formed in the semiconductor layer below the second grid, however a current channel is also formed in the semiconductor layer after an original first grid of the TFT is powered on, i.e. two current channels are formed in the semiconductor layer, therefore, on the premise that the grid scanning signal strength of a grid line is not increased, the overall electrification current quantity of the TFT semiconductor layer is increased; and moreover since the newly added second grid is arranged above the semiconductor layer, the area occupied by the whole TFT structure in a pixel unit is not increased, and thus the aperture opening ratio of the pixel unit is not reduced.
Description
Technical field
The present invention relates to the display technique field, relate in particular to a kind of thin film transistor (TFT) tft array substrate, its preparation method and display device.
Background technology
At present, along with the development of lcd technology, more and more higher to the electric conduction flow requirement of the TFT switch in the liquid crystal panel.As depicted in figs. 1 and 2, the TFT of tft array substrate 5 forms by being successively set on grid 1, semiconductor layer 3, the source electrode 4 on the substrate and draining in existing liquid crystal panel, wherein, grid 1 is electrical connected with grid line 8, grid 1 is by gate insulation layer 2 and semiconductor layer 3 isolation, source electrode 4 is electrical connected with data line 9, and drain electrode 5 is electrical connected by the via hole on the passivation layer 6 and pixel electrode 7, source electrode 4 with drain 5 relative and put the formation channel structure.
Its principle of work is: when grid line 8 loads scanning gate signal, grid 1 energising with its electric connection, semiconductor above grid 3 can become the conductor state from the semiconductor state like this, the electric charge of semiconductor 3 can move along gate electrode insulation surface, shown in Fig. 3 a, namely 2 surfaces of the gate insulation layer in semiconductor layer 3 form a current channel a, the magnitude of current that this current channel a can pass through is called electric conduction flow (Ion), current channel a can make electric signal that data line 9 is loaded into source electrode 45 flow on the pixel electrode 7 by draining, and makes pixel cell be in opening.And when grid line 8 did not load scanning gate signal, shown in Fig. 3 b, the electric signal that semiconductor layer 3 interior no current passage a, data line 9 are loaded into source electrode 4 can not flow on the pixel electrode 7 by source electrode 4, made pixel cell be in closed condition.
Can find out from above-mentioned TFT principle of work, grid line 8 is larger at the scanning gate signal that grid 1 loads, the electric conduction flow of the current channel a that forms at semiconductor layer 3 is also just larger, and the control pixel electrode 7 that the electric signal that data line 9 loads just can be good is realized the high picture quality that shows.But, when practical operation, being subject to the restriction of display panel power consumption, the voltage that applies scanning gate signal at grid 1 often can not be excessive.So, in order to improve the electric conduction flow of the current channel a that semiconductor layer 3 forms, just need to adopt change TFT structure to enlarge the mode of entire area, the problem that certainly will bring like this pixel cell aperture opening ratio to descend.
Therefore, how in the situation that guarantee the pixel cell aperture opening ratio, increase the electric conduction flow of TFT semiconductor layer, be the technical matters that those skilled in the art need solution badly as far as possible.
Summary of the invention
The embodiment of the invention provides a kind of tft array substrate, its preparation method and display device, in the situation that guarantee the pixel cell aperture opening ratio, increases the electric conduction flow of TFT semiconductor layer in order to realize as far as possible.
A kind of thin film transistor (TFT) tft array substrate that the embodiment of the invention provides, comprise: be successively set on first grid, gate insulation layer, semiconductor layer, source electrode, drain electrode and passivation layer on the substrate, also comprise: be arranged on the described passivation layer and be positioned at the second grid of described semiconductor layer top.
A kind of display device that the embodiment of the invention provides comprises the tft array substrate that the embodiment of the invention provides.
The preparation method of a kind of tft array substrate that the embodiment of the invention provides comprises:
The first grid that forms grid line and be electrical connected with described grid line at substrate;
Form the gate insulation layer that covers described first grid and grid line;
Forming semiconductor layer on the described gate insulation layer and above being positioned at described grid;
Form source electrode and the drain electrode of relatively putting at described semiconductor layer;
Form the passivation layer that covers described source electrode and drain electrode;
Form the pixel electrode that is electrical connected with described drain electrode and the second grid that is electrical connected with described grid line at described passivation layer.
The beneficial effect of the embodiment of the invention comprises:
A kind of tft array substrate that the embodiment of the invention provides, its preparation method and display device, on the basis of existing TFT structure, increase the second grid that is positioned at above the semiconductor layer at the passivation layer of TFT, when TFT works, after the newly-increased second grid energising, can form a current channel in the semiconductor layer thereunder, and also can in semiconductor layer, form a current channel after the original first grid energising of TFT, namely in semiconductor layer, can form two current channels, like this, do not increasing under the scanning gate signal intensity prerequisite of grid line, promoting the electric conduction flow of TFT semiconductor layer integral body; And, because the second grid that should increase newly is arranged on the top of semiconductor layer, can not increase the size that whole TFT structure takies pixel cell, therefore can not reduce the aperture opening ratio of pixel cell.
Description of drawings
Fig. 1 is the vertical view of tft array substrate in the prior art;
Fig. 2 is the sectional drawing of A-A among Fig. 1;
Fig. 3 a and Fig. 3 b are the fundamental diagram of TFT;
The vertical view of the tft array substrate that Fig. 4 provides for the embodiment of the invention;
Fig. 5 is the sectional drawing of A-A among Fig. 4;
The fundamental diagram of the tft array substrate that Fig. 6 a and Fig. 6 b provide for the embodiment of the invention;
Fig. 7 is the sectional drawing of B-B among Fig. 4;
The preparation method's of the tft array substrate that Fig. 8 provides for the embodiment of the invention process flow diagram.
Embodiment
Below in conjunction with accompanying drawing, the embodiment of tft array substrate, its preparation method and the display device that the embodiment of the invention is provided is described in detail.
Each layer film and area size shape do not reflect the true ratio of array base palte in the accompanying drawing, and purpose is signal explanation content of the present invention just.
A kind of thin film transistor (TFT) tft array substrate that the embodiment of the invention provides, as shown in Figure 4 and Figure 5, comprise: be successively set on first grid 1 on the substrate, gate insulation layer 2, semiconductor layer 3, source electrode 4, drain electrode 5 and passivation layer 6, also comprise: be arranged on the passivation layer 6 and be positioned at the second grid 10 of semiconductor layer 3 tops.
In the specific implementation, semiconductor layer 3 can adopt the preparation of a-Si or metal oxide materials, when choosing metal oxide and prepare semiconductor layer, because the contact resistance of metal oxide is less, does not then generally re-use ohmic contact layer and reduces contact resistance; When choosing a-Si and prepare semiconductor layer, between semiconductor layer and source-drain electrode, also need to arrange ohmic contact layer.
The above-mentioned tft array substrate that the embodiment of the invention provides is on the basis of existing TFT structure, increase the second grid 10 that is positioned at above the semiconductor layer 3 at the passivation layer 6 of TFT, when TFT works, shown in Fig. 6 a, after newly-increased second grid 10 energisings, can form a current channel b in the semiconductor layer 3 thereunder, and also can in semiconductor layer 3, form a current channel a after original first grid 1 energising of TFT, namely in semiconductor layer, can form two current channel a and b, after these two current channel stacks, can not increase under the scanning gate signal intensity prerequisite of grid line 1, promote the electric conduction flow of TFT semiconductor layer 3 integral body; And, because the second grid 10 that should increase newly is arranged on the top of semiconductor layer 3, can not increase the size that whole TFT structure takies pixel cell, therefore can not reduce the aperture opening ratio of pixel cell.Fig. 6 b is the schematic diagram of TFT when closing.
Particularly, because in the above-mentioned tft array substrate that the embodiment of the invention provides, need to be to first grid 1 and 10 while of second grid on-load voltage unblanking TFT switch, just can reach the effect that increases current lead-through amount in the semiconductor layer 3, therefore, the second grid line 10 and the first grid line 1 should guarantee to be electrical connected with same grid line 8, particularly, because second grid 10 is arranged on the passivation layer 6, therefore, as shown in Figure 7, second grid 10 generally is electrical connected with corresponding grid line 8 by via hole, specifically forms the via hole that this penetrates passivation layer 6 and gate insulation layer 2 when formation passivation layer 6 figure.
Further, because newly-increased second grid 10 is positioned at semiconductor layer 3 tops, the second grid 10 that namely should increase newly can not take the open area of existing pixel cell, therefore, newly-increased second grid 10 can example such as the metal material preparation identical with first grid 1, also can example prepare such as the transparent conductive material identical with pixel electrode, do not do restriction at this.
Further, second grid 10 newly-increased in above-mentioned TFT structure can arrange with layer with the pixel electrode 7 that is positioned at the tft array substrate on the passivation layer 6, like this, can form by a composition technique figure of second grid 10 and pixel electrode 7, can not increase the step of preparation process of existing tft array substrate, only need to change the mask plate pattern of existing preparation passivation layer and pixel electrode, both can realize the above-mentioned TFT structure that the invention process provides, cost of manufacture that on the whole can tft array substrate.
The above-mentioned tft array substrate structure that the embodiment of the invention provides can be applied to such as senior super dimension field switch (ADS, Advanced Super Dimension Switch), plane conversion (IPS, In Plane Switching) or twisted-nematic (TN, Twisted Nematic) in the array base palte of type, also can be applied to not do restriction at this in the organic electroluminescence device (OLED).
Based on same inventive concept, the embodiment of the invention also provides a kind of display device, comprises the above-mentioned tft array substrate that the embodiment of the invention provides, and the enforcement of this display device can referring to the embodiment of above-mentioned tft array substrate, repeat part and repeat no more.
In the specific implementation, this display device can for: liquid crystal panel, Electronic Paper, oled panel, LCD TV, liquid crystal display, digital album (digital photo frame), mobile phone, panel computer etc. have product or the parts of any Presentation Function.
Based on same inventive concept, the embodiment of the invention also provides a kind of preparation method of above-mentioned tft array substrate, as shown in Figure 8, specifically comprises the steps:
S101, the first grid that forms grid line and be electrical connected with grid line at substrate;
S102, formation cover the gate insulation layer of first grid and grid line;
S103, forming semiconductor layer on the gate insulation layer and above being positioned at grid;
S104, form source electrode and the drain electrode of relatively putting at semiconductor layer;
Further, when forming source electrode and drain electrode, also form the data line that is electrical connected with source electrode;
Above-mentioned steps S101 ~ S104 is same as the prior art, and the concrete material of its concrete composition technique and each member is not describing in detail at this, and following step S105 ~ S106 is difference with the prior art point of the present invention:
S105, formation cover the passivation layer of source electrode and drain electrode; Wherein, to the passivation layer composition time, need to form the via hole that connects drain electrode and pixel electrode at passivation layer; Further, also need to be connected the via hole that connects second grid and grid line with gate insulation layer at passivation layer, to guarantee the electrical connection of second grid and grid line.
S106, form the pixel electrode that is electrical connected with drain electrode and the second grid that is electrical connected with grid line at passivation layer;
Particularly, this pixel electrode and second grid can be the transparent conductive materials such as tin indium oxide ITO or zinc-tin oxide IZO.
A kind of tft array substrate that the embodiment of the invention provides, its preparation method and display device, on the basis of existing TFT structure, increase the second grid that is positioned at above the semiconductor layer at the passivation layer of TFT, when TFT works, after the newly-increased second grid energising, can form a current channel in the semiconductor layer thereunder, and also can in semiconductor layer, form a current channel after the original first grid energising of TFT, namely in semiconductor layer, can form two current channels, like this, do not increasing under the scanning gate signal intensity prerequisite of grid line, promoting the electric conduction flow of TFT semiconductor layer integral body; And, because the second grid that should increase newly is arranged on the top of semiconductor layer, can not increase the size that whole TFT structure takies pixel cell, therefore can not reduce the aperture opening ratio of pixel cell.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (11)
1. thin film transistor (TFT) tft array substrate, comprise: be successively set on first grid, gate insulation layer, semiconductor layer, source electrode, drain electrode and passivation layer on the substrate, it is characterized in that, also comprise: be arranged on the described passivation layer and be positioned at the second grid of described semiconductor layer top.
2. tft array substrate as claimed in claim 1 is characterized in that, described second grid is electrical connected by grid line corresponding in via hole and the described tft array substrate.
3. tft array substrate as claimed in claim 1 or 2 is characterized in that, described second grid is transparent conductive material or metal material.
4. tft array substrate as claimed in claim 3 is characterized in that, described second grid arranges with layer with the pixel electrode that is positioned at the tft array substrate on the described passivation layer.
5. tft array substrate as claimed in claim 1 is characterized in that, also is provided with ohmic contact layer between described semiconductor layer and the source-drain electrode.
6. a display device is characterized in that, comprises each described tft array substrate such as claim 1-5.
7. the preparation method such as each described tft array substrate of claim 1-5 is characterized in that, comprising:
The first grid that forms grid line and be electrical connected with described grid line at substrate;
Form the gate insulation layer that covers described first grid and grid line;
Forming semiconductor layer on the described gate insulation layer and above being positioned at described grid;
Form source electrode and the drain electrode of relatively putting at described semiconductor layer;
Form the passivation layer that covers described source electrode and drain electrode;
Form the pixel electrode that is electrical connected with described drain electrode and the second grid that is electrical connected with described grid line at described passivation layer.
8. preparation method as claimed in claim 7 is characterized in that, described passivation layer has the via hole that is connected described second grid and grid line with described gate insulation layer.
9. preparation method as claimed in claim 7 is characterized in that, described passivation layer has the via hole that connects described drain electrode and described pixel electrode.
10. preparation method as claimed in claim 7 is characterized in that, described pixel electrode and described second grid are tin indium oxide ITO or zinc-tin oxide IZO.
11. such as each described preparation method of claim 7-10, it is characterized in that, when forming source electrode and drain electrode, also form the data line that is electrical connected with described source electrode.
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| CN2012103967690A CN102955314A (en) | 2012-10-18 | 2012-10-18 | TFT (Thin Film Transistor) array substrate, preparation method and display device |
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Cited By (3)
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| CN103296033A (en) * | 2013-05-28 | 2013-09-11 | 京东方科技集团股份有限公司 | Array substrate and production method thereof |
| CN104503174A (en) * | 2014-12-24 | 2015-04-08 | 合肥京东方光电科技有限公司 | GOA circuit module, testing method of GOA circuit module, display panel and display device |
| WO2017012164A1 (en) * | 2015-07-20 | 2017-01-26 | 深圳市华星光电技术有限公司 | Boa type liquid crystal display panel and manufacturing method thereof |
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| TW200905347A (en) * | 2007-07-31 | 2009-02-01 | Chi Mei Optoelectronics Corp | Dual-gate thin film transistor, pixel structure, and liquid crystal display panel and apparatus |
| CN202487578U (en) * | 2012-03-27 | 2012-10-10 | 京东方科技集团股份有限公司 | Thin film transistor and array substrate and display device |
| CN202816958U (en) * | 2012-10-18 | 2013-03-20 | 京东方科技集团股份有限公司 | Thin film transistor TFT array substrate and display device |
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| JPH0553147A (en) * | 1991-08-23 | 1993-03-05 | Nec Corp | Liquid crystal display device and production thereof |
| TW200905347A (en) * | 2007-07-31 | 2009-02-01 | Chi Mei Optoelectronics Corp | Dual-gate thin film transistor, pixel structure, and liquid crystal display panel and apparatus |
| CN202487578U (en) * | 2012-03-27 | 2012-10-10 | 京东方科技集团股份有限公司 | Thin film transistor and array substrate and display device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103296033A (en) * | 2013-05-28 | 2013-09-11 | 京东方科技集团股份有限公司 | Array substrate and production method thereof |
| CN103296033B (en) * | 2013-05-28 | 2016-05-11 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof |
| US9865622B2 (en) | 2013-05-28 | 2018-01-09 | Boe Technology Group Co., Ltd. | Array substrate and a method for manufacturing the same |
| CN104503174A (en) * | 2014-12-24 | 2015-04-08 | 合肥京东方光电科技有限公司 | GOA circuit module, testing method of GOA circuit module, display panel and display device |
| CN104503174B (en) * | 2014-12-24 | 2017-10-10 | 合肥京东方光电科技有限公司 | GOA circuit modules and its method of testing, display panel and display device |
| WO2017012164A1 (en) * | 2015-07-20 | 2017-01-26 | 深圳市华星光电技术有限公司 | Boa type liquid crystal display panel and manufacturing method thereof |
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Application publication date: 20130306 |