CN205609532U - Thin film transistor and array substrate , display device - Google Patents
Thin film transistor and array substrate , display device Download PDFInfo
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- CN205609532U CN205609532U CN201620450032.6U CN201620450032U CN205609532U CN 205609532 U CN205609532 U CN 205609532U CN 201620450032 U CN201620450032 U CN 201620450032U CN 205609532 U CN205609532 U CN 205609532U
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Abstract
The utility model discloses a thin film transistor and array substrate, display device belongs to and shows technical field. Thin film transistor includes: the substrate base plate is formed with the grid on the substrate base plate, it is formed with the gate insulation layer on the substrate base plate of grid to be formed with, be formed with active layer and source -drain electrode metal pattern on being formed with the substrate base plate on gate insulation layer, the active layer includes the polycrystalline silicon pattern and is located the non -crystalline silicon pattern on the polycrystalline silicon pattern, wherein, source -drain electrode metal pattern includes source electrode and drain electrode, and the source electrode contacts with polycrystalline silicon pattern and non -crystalline silicon pattern respectively, and the drain electrode contacts with polycrystalline silicon pattern and non -crystalline silicon pattern respectively. The utility model provides a thin film transistor's on -state current less, the lower problem of chargeability has reached increase thin film transistor's on -state current, improves the effect of chargeability. The utility model is used for array substrate.
Description
Technical field
This utility model relates to Display Technique field, particularly to a kind of thin film transistor (TFT) and array base palte, shows
Showing device.
Background technology
In display industry, the pixel cell of display device is formed with thin film transistor (TFT) (English: Thin Film
Transistor；Being called for short: TFT), this TFT can drive pixel cell to realize image to show.
In correlation technique, TFT can be that a-Si (Chinese: non-crystalline silicon) TFT, a-Si TFT includes: substrate
Substrate and the grid, gate insulation layer, active layer and the source-drain electrode metal pattern that are sequentially formed on underlay substrate,
Wherein, active layer include use a-Si material formed a-Si layer, source-drain electrode metal pattern includes: source electrode and
Drain electrode, source electrode contacts with a-Si layer respectively with drain electrode, and drain electrode also contacts with the pixel electrode in pixel cell,
Grid can control the opening and closing of TFT, and when TFT opens, the electric current on source electrode can pass sequentially through
A-Si layer and drain electrode writing pixel electrode, to charge to pixel electrode.
During realizing this utility model, inventor finds that correlation technique at least there is problems in that
Owing to source electrode contacts with amorphous silicon layer respectively with drain electrode, when charging to pixel electrode, the source electrode of TFT
On electric current need to get to drain electrode by a-Si layer, and the electron mobility of a-Si is less, therefore, a-Si
The ON state current of TFT is less, and charge rate is relatively low.
Utility model content
Less in order to solve the ON state current of TFT, that charge rate is relatively low problem, this utility model provides one
Thin film transistor (TFT) and array base palte, display device.Described technical scheme is as follows:
First aspect, it is provided that a kind of thin film transistor (TFT), described thin film transistor (TFT) includes: underlay substrate,
It is formed with grid on described underlay substrate；
It is formed on the underlay substrate of described grid and is formed with gate insulation layer；
It is formed on the underlay substrate of described gate insulation layer and is formed with active layer and source-drain electrode metal pattern, described
Active layer includes poly-silicon pattern and the amorphous silicon pattern being positioned on described poly-silicon pattern；
Wherein, described source-drain electrode metal pattern includes source electrode and drain electrode, described source electrode respectively with described polysilicon
Pattern contacts with described amorphous silicon pattern, described drain electrode respectively with described poly-silicon pattern and described non-crystalline silicon figure
Case contacts.
Alternatively, described active layer also includes: be positioned on described amorphous silicon pattern and described poly-silicon pattern
Ohmic contact pattern,
Described ohmic contact pattern includes: source contact pattern and drain contact pattern, described source contact figure
Case does not contacts with described drain contact pattern, and described source contact pattern respectively with described source electrode, described many
Crystal silicon pattern contacts with described amorphous silicon pattern, described drain contact pattern respectively with described drain electrode, described many
Crystal silicon pattern contacts with described amorphous silicon pattern.
Alternatively, described ohmic contact pattern respectively with described amorphous silicon pattern and described poly-silicon pattern part
Contact；
The orthographic projection on described underlay substrate of the described amorphous silicon pattern is positioned at described poly-silicon pattern at described lining
In orthographic projection region on substrate；
The orthographic projection on described underlay substrate of the described ohmic contact pattern and described source-drain electrode metal pattern are in institute
State the orthographic projection on underlay substrate to overlap；
The orthographic projection on described underlay substrate of the described poly-silicon pattern and described grid are on described underlay substrate
Orthographic projection overlap.
Alternatively, the center of described amorphous silicon pattern orthographic projection on described underlay substrate and described polysilicon
The center superposition of pattern orthographic projection on described underlay substrate.
Alternatively, the formation material of described ohmic contact pattern includes: n+ non-crystalline silicon.
Second aspect, it is provided that a kind of array base palte, described array base palte includes: the thin film described in first aspect
Transistor.
Alternatively, it is formed on the underlay substrate of described thin film transistor (TFT) and is formed with passivation layer, described passivation layer
On be formed with via；
Being formed on the underlay substrate of described passivation layer and be formed with pixel electrode, described pixel electrode is by described
Via and the drain contact of described thin film transistor (TFT).
The third aspect, it is provided that a kind of display device, described display device includes the array base described in second aspect
Plate.
The technical scheme that this utility model provides has the benefit that
The thin film transistor (TFT) of this utility model offer and array base palte, display device, thin film transistor (TFT) includes:
Underlay substrate, underlay substrate is formed grid, is formed on the underlay substrate of grid and is formed with gate insulation layer,
Being formed on the underlay substrate of gate insulation layer and be formed with active layer and source-drain electrode metal pattern, active layer includes many
Crystal silicon pattern and the amorphous silicon pattern being positioned on poly-silicon pattern, source-drain electrode metal pattern includes source electrode and drain electrode,
Source electrode contacts with poly-silicon pattern and amorphous silicon pattern respectively, drain electrode respectively with poly-silicon pattern and non-crystalline silicon figure
Case contacts.Owing to source electrode contacts with poly-silicon pattern and amorphous silicon pattern respectively, drain electrode respectively with polysilicon figure
Case contacts with amorphous silicon pattern, and when thin film transistor (TFT) is opened, the electric current on source electrode can pass through polysilicon figure
Case arrives drain electrode, and the electron mobility of poly-silicon pattern is higher, therefore, it can increase thin film transistor (TFT)
ON state current, improves charge rate, solves the ON state current of thin film transistor (TFT) in correlation technique less, charging
The problem that rate is relatively low, has reached to increase the ON state current of thin film transistor (TFT), has improved the effect of charge rate.
It should be appreciated that it is only exemplary that above general description and details hereinafter describe, can not
Limit this utility model.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme in this utility model embodiment, embodiment will be described below
The accompanying drawing used required in is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Some embodiments of utility model, for those of ordinary skill in the art, are not paying creative work
On the premise of, it is also possible to other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is the structural representation of a kind of thin film transistor (TFT) that this utility model embodiment provides；
Fig. 2 is the structural representation of the another kind of thin film transistor (TFT) that this utility model embodiment provides；
Fig. 3 is the structural representation of a kind of array base palte that this utility model embodiment provides.
Accompanying drawing herein is merged in description and constitutes the part of this specification, it is shown that meet this practicality
Novel embodiment, and be used for explaining principle of the present utility model together with description.
Detailed description of the invention
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing pair
This utility model is described in further detail, it is clear that described embodiment is only this utility model one
Partly embodiment rather than whole embodiments.Based on the embodiment in this utility model, this area is common
All other embodiments that technical staff is obtained under not making creative work premise, broadly fall into this reality
By novel protected scope.
Refer to Fig. 1, a kind of thin film transistor (TFT) 00 structure that it illustrates this utility model embodiment provides is shown
Being intended to, see Fig. 1, this thin film transistor (TFT) 00 includes: underlay substrate 001.Underlay substrate 001 can be
Transparency carrier, it can be specifically the leaded light using glass, quartz, transparent resin etc. to have certain robustness
And the substrate that nonmetallic materials are made.
Grid 002 it is formed with on underlay substrate 001；It is formed on the underlay substrate 001 of grid 002 and is formed
Gate insulation is (English: Gate Insulator；It is called for short: GI) layer 003；It is formed with the substrate of gate insulation layer 003
Being formed with active layer 004 and source-drain electrode metal pattern 005 on substrate 001, active layer 004 includes polysilicon (English
Literary composition: p-Si) pattern 0041 and the amorphous silicon pattern 0042 being positioned on poly-silicon pattern 0041.
Wherein, source-drain electrode metal pattern 005 includes source electrode 0051 and drain electrode 0052, source electrode 0051 respectively with
Poly-silicon pattern 0041 contacts with amorphous silicon pattern 0042, drain electrode 0052 respectively with poly-silicon pattern 0041
Contact with amorphous silicon pattern 0042.
In sum, this utility model embodiment provide thin film transistor (TFT), due to source electrode respectively with polysilicon
Pattern contacts with amorphous silicon pattern, and drain electrode contacts with poly-silicon pattern and amorphous silicon pattern respectively, brilliant at thin film
When body pipe is opened, the electric current on source electrode can be arrived by poly-silicon pattern and drain, and the electricity of poly-silicon pattern
Transport factor is higher, therefore, it can increase the ON state current of thin film transistor (TFT), improves charge rate, solve
In correlation technique, the ON state current of thin film transistor (TFT) is less, the problem that charge rate is relatively low, has reached increase thin film
The ON state current of transistor, improves the effect of charge rate.
Refer to Fig. 2, it illustrates another kind of thin film transistor (TFT) 00 structure that this utility model embodiment provides
Schematic diagram, sees Fig. 2, and this thin film transistor (TFT) 00 includes: underlay substrate 001.Underlay substrate 001 is permissible
For transparency carrier, it can be specifically to use glass, quartz, transparent resin etc. to have leading of certain robustness
The substrate that light and nonmetallic materials are made.
Grid 002 it is formed with on underlay substrate 001；It is formed on the underlay substrate 001 of grid 002 and is formed
Gate insulation layer 003；It is formed on the underlay substrate 001 of gate insulation layer 003 and is formed with active layer 004 and source and drain
Pole metal pattern 005, active layer 004 includes poly-silicon pattern 0041 and is positioned on poly-silicon pattern 0041
Amorphous silicon pattern 0042.
Wherein, source-drain electrode metal pattern 005 includes source electrode 0051 and drain electrode 0052, source electrode 0051 respectively with
Poly-silicon pattern 0041 contacts with amorphous silicon pattern 0042, drain electrode 0052 respectively with poly-silicon pattern 0041
Contact with amorphous silicon pattern 0042.
Further, please continue to refer to Fig. 2, active layer 004 can also include: is positioned at amorphous silicon pattern 0042
With the ohmic contact pattern 0043 on poly-silicon pattern 0041.The formation material of this ohmic contact pattern 0043
Including: n+ non-crystalline silicon is (English: n+a-Si), and this ohmic contact pattern 0043 includes: source contact figure
Case 00431 and drain contact pattern 00432, this source contact pattern 00431 is corresponding with source electrode 0051, and
This source contact pattern 00431 respectively with source electrode 0051, poly-silicon pattern 0041 and amorphous silicon pattern 0042
Contact, this drain contact pattern 00432 with drain 0052 corresponding, and drain contact pattern 00432 respectively with
Drain electrode 0052, poly-silicon pattern 0041 contact with amorphous silicon pattern 0042.
Alternatively, as in figure 2 it is shown, ohmic contact pattern 0043 respectively with amorphous silicon pattern 0042 and polycrystalline
Silicon pattern 0041 part contact, that is to say, a part for ohmic contact pattern 0043 and amorphous silicon pattern 0042
Contact, another part contacts with poly-silicon pattern 0041, and this is not construed as limiting by this utility model embodiment.
Alternatively, the amorphous silicon pattern 0042 orthographic projection on underlay substrate 001 is positioned at poly-silicon pattern 0041
In orthographic projection region on underlay substrate 001, so can be so that ohmic contact pattern 0043 be respectively with non-
Crystal silicon pattern 0042 and poly-silicon pattern 0041 part contact.
Alternatively, the ohmic contact pattern 0043 orthographic projection on underlay substrate 001 and source-drain electrode metal pattern
005 orthographic projection on underlay substrate 001 overlaps；Poly-silicon pattern 0041 on underlay substrate 001 just
Projection overlaps with the grid 002 orthographic projection on underlay substrate 001.
Alternatively, the center of the amorphous silicon pattern 0042 orthographic projection on underlay substrate 001 and poly-silicon pattern
The center superposition of 0041 orthographic projection on underlay substrate 001.
Alternatively, in this utility model embodiment, grid 002 and the formation of source-drain electrode metal pattern 005
Material can be all metal material, its be specifically as follows metal Mo (Chinese: molybdenum), Ni metal (Chinese:
Copper), metal Al (Chinese: aluminum) and alloy material thereof, the formation material of gate insulation layer 003 can be two
The mixing material of silicon oxide, silicon nitride or silicon dioxide and silicon nitride, this utility model embodiment is at this not
Repeat again.
In the thin film transistor (TFT) 00 shown in Fig. 2, grid 002 can control the unlatching of thin film transistor (TFT) 00
And closedown, when thin film transistor (TFT) 00 is opened, the electric current on source electrode 0051 is mainly by source contact pattern
00431, poly-silicon pattern 0041, drain contact pattern 00432 arrive drain electrode 0052, at thin film transistor (TFT)
00 close time, drain electrode 0052 on electric current mainly by drain contact pattern 00432, amorphous silicon pattern 0042,
Source contact pattern 00431 arrives source electrode 0051, and the electron mobility of poly-silicon pattern 0041 is higher, non-
The electron mobility of crystal silicon pattern 0042 is relatively low, so, due to when thin film transistor (TFT) 00 is opened,
Electric current on source electrode 0051 arrives drain electrode 0052 by poly-silicon pattern 0041, at thin film transistor (TFT) 00
During closedown, the electric current in drain electrode 0052 arrives source electrode 0051 by amorphous silicon pattern 0042, therefore,
The ON state current of thin film transistor (TFT) 00 can be increased, reduce the off-state current of thin film transistor (TFT) 00.
In sum, this utility model embodiment provide thin film transistor (TFT), due to source electrode respectively with polysilicon
Pattern contacts with amorphous silicon pattern, and drain electrode contacts with poly-silicon pattern and amorphous silicon pattern respectively, brilliant at thin film
When body pipe is opened, the electric current on source electrode can be arrived by poly-silicon pattern and drain, and the electricity of poly-silicon pattern
Transport factor is higher, therefore, it can increase the ON state current of thin film transistor (TFT), improves charge rate, solve
In correlation technique, the ON state current of thin film transistor (TFT) is less, the problem that charge rate is relatively low, has reached increase thin film
The ON state current of transistor, improves the effect of charge rate.
TFT in correlation technique also includes that low temperature polycrystalline silicon is (English: Low Temperature Poly-silicon；
Be called for short: LTPS) TFT, LTPS-TFT include: underlay substrate and be sequentially formed on underlay substrate grid,
Gate insulation layer, active layer and source-drain electrode metal pattern, wherein, active layer is for using low-temperature polysilicon silicon technology shape
The polysilicon active layer become, source-drain electrode metal pattern includes: source electrode and drain electrode, and source electrode and drain electrode are respectively with many
Crystal silicon active layer contacts, due to the electron mobility of polysilicon higher (more than the Radix Achyranthis Bidentatae of typically a-Si),
Therefore, the ON state current of LTPS-TFT is relatively big, and charge rate is higher, but LTPS-TFT exists off-state current
Bigger problem, affects the service behaviour of LTPS-TFT, and uses the thin film that this utility model embodiment provides
Transistor, source electrode contacts with poly-silicon pattern and amorphous silicon pattern respectively, drain electrode respectively with poly-silicon pattern and
Amorphous silicon pattern contacts, and when thin film transistor (TFT) cuts out, the electric current in drain electrode can be arrived by amorphous silicon pattern
Reach source electrode, the electric charge in drain electrode is discharged, and the electron mobility of amorphous silicon pattern is relatively low, therefore,
The off-state current of thin film transistor (TFT) can be reduced.
In correlation technique, in order to ensure the charge rate of a-Si TFT, generally the size of a-Si TFT is arranged
Relatively big, so, have a strong impact on the aperture opening ratio of pixel cell, limited high-resolution and narrow frame produces
Product are developed, the thin film transistor (TFT) that this utility model embodiment provides, can be at the aperture opening ratio ensureing pixel cell
On the premise of, improve the charge rate of thin film transistor (TFT), therefore, it can be applicable to high-resolution and narrow frame
The exploitation of product.
Refer to Fig. 3, it illustrates the structural representation of a kind of array base palte 0 that this utility model embodiment provides
Figure, this array base palte 0 includes: thin film transistor (TFT) as shown in Figure 1 or 2.
Further, it is formed on the underlay substrate 001 of thin film transistor (TFT) and is formed with passivation layer 01, passivation layer
Via (not marking in Fig. 3) it is formed with on 01；It is formed on the underlay substrate 001 of passivation layer 01 and is formed
Pixel electrode 02, pixel electrode 02 is contacted with the drain electrode 0052 of thin film transistor (TFT) by via.
Alternatively, array base palte 0 can also include: grid line (not shown in Fig. 3), data wire (Fig. 3
Not shown in) and public electrode wire 03, grid line can be connected with the grid 002 of thin film transistor (TFT), data wire
Can be connected with the source electrode 0051 of thin film transistor (TFT), public electrode wire can be connected with public electrode, and this is public
Electrode can be arranged on array base palte 0, and grid line, public electrode wire 03 and grid 002 may be located at same
One layer, and can be by being formed with a patterning processes, this is not construed as limiting by this utility model embodiment.
Wherein, passivation layer 01 can use earth silicon material or silicon nitride material to be fabricated by, pixel electricity
Pole 02 can use tin indium oxide (English: Indium tin oxide；It is called for short: ITO) material or Indium sesquioxide.
Zinc is (English: Indium zinc oxide；It is called for short: IZO) material is fabricated by, and illustratively, can use
The methods such as magnetron sputtering, thermal evaporation or PECVD form passivation layer 01, then by a patterning processes
Passivation layer 01 is formed via, uses the methods such as magnetron sputtering, thermal evaporation or PECVD in shape afterwards
Become to have deposition one layer on the underlay substrate 001 of passivation layer 01 to have certain thickness ITO material, obtain ITO
Material layers, then carries out process by a patterning processes to ITO material layers and obtains pixel electrode 02, this reality
Do not repeat them here by new embodiment.
In sum, the array base palte that this utility model embodiment provides, owing to the source electrode of thin film transistor (TFT) divides
Not contacting with poly-silicon pattern and amorphous silicon pattern, drain electrode contacts with poly-silicon pattern and amorphous silicon pattern respectively,
When thin film transistor (TFT) is opened, the electric current on source electrode can be arrived by poly-silicon pattern and drain, and polysilicon
The electron mobility of pattern is higher, therefore, it can increase the ON state current of thin film transistor (TFT), improves charge rate,
Solve the ON state current of thin film transistor (TFT) in correlation technique less, the problem that charge rate is relatively low, reach to increase
The ON state current of big thin film transistor (TFT), improves the effect of charge rate.
This utility model embodiment additionally provides a kind of display device, and this display device includes the battle array shown in Fig. 3
Row substrate, this display device can be: liquid crystal panel, Electronic Paper, mobile phone, panel computer, television set,
Any product with display function or the parts such as display, notebook computer, DPF, navigator.
In sum, the display device that this utility model embodiment provides includes array base palte, due to array base
The source electrode of the thin film transistor (TFT) of plate contacts with poly-silicon pattern and amorphous silicon pattern respectively, drain electrode respectively with polycrystalline
Silicon pattern contacts with amorphous silicon pattern, and when thin film transistor (TFT) is opened, the electric current on source electrode can pass through polycrystalline
Silicon pattern arrives drain electrode, and the electron mobility of poly-silicon pattern is higher, therefore, it can increase film crystal
The ON state current of pipe, improves charge rate, solves the ON state current of thin film transistor (TFT) in correlation technique less,
The problem that charge rate is relatively low, has reached to increase the ON state current of thin film transistor (TFT), has improved the effect of charge rate.
The foregoing is only preferred embodiment of the present utility model, not in order to limit this utility model, all
Within spirit of the present utility model and principle, any modification, equivalent substitution and improvement etc. made, all should wrap
Within being contained in protection domain of the present utility model.
Claims (8)
1. a thin film transistor (TFT), it is characterised in that described thin film transistor (TFT) includes: underlay substrate,
It is formed with grid on described underlay substrate；
It is formed on the underlay substrate of described grid and is formed with gate insulation layer；
It is formed on the underlay substrate of described gate insulation layer and is formed with active layer and source-drain electrode metal pattern, described
Active layer includes poly-silicon pattern and the amorphous silicon pattern being positioned on described poly-silicon pattern；
Wherein, described source-drain electrode metal pattern includes source electrode and drain electrode, described source electrode respectively with described polysilicon
Pattern contacts with described amorphous silicon pattern, described drain electrode respectively with described poly-silicon pattern and described non-crystalline silicon figure
Case contacts.
Thin film transistor (TFT) the most according to claim 1, it is characterised in that described active layer also includes:
It is positioned at the ohmic contact pattern on described amorphous silicon pattern and described poly-silicon pattern,
Described ohmic contact pattern includes: source contact pattern and drain contact pattern, described source contact figure
Case does not contacts with described drain contact pattern, and described source contact pattern respectively with described source electrode, described many
Crystal silicon pattern contacts with described amorphous silicon pattern, described drain contact pattern respectively with described drain electrode, described many
Crystal silicon pattern contacts with described amorphous silicon pattern.
Thin film transistor (TFT) the most according to claim 2, it is characterised in that
Described ohmic contact pattern respectively with described amorphous silicon pattern and described poly-silicon pattern part contact；
The orthographic projection on described underlay substrate of the described amorphous silicon pattern is positioned at described poly-silicon pattern at described lining
In orthographic projection region on substrate；
The orthographic projection on described underlay substrate of the described ohmic contact pattern and described source-drain electrode metal pattern are in institute
State the orthographic projection on underlay substrate to overlap；
The orthographic projection on described underlay substrate of the described poly-silicon pattern and described grid are on described underlay substrate
Orthographic projection overlap.
Thin film transistor (TFT) the most according to claim 3, it is characterised in that
The center of described amorphous silicon pattern orthographic projection on described underlay substrate and described poly-silicon pattern are in institute
State the center superposition of orthographic projection on underlay substrate.
5. according to the arbitrary described thin film transistor (TFT) of claim 2 to 4, it is characterised in that
The formation material of described ohmic contact pattern includes: n+ non-crystalline silicon.
6. an array base palte, it is characterised in that described array base palte includes: claim 1 to 5 is arbitrary
Described thin film transistor (TFT).
Array base palte the most according to claim 6, it is characterised in that
It is formed on the underlay substrate of described thin film transistor (TFT) and is formed with passivation layer, described passivation layer is formed
Via；
Being formed on the underlay substrate of described passivation layer and be formed with pixel electrode, described pixel electrode is by described
Via and the drain contact of described thin film transistor (TFT).
8. a display device, it is characterised in that described display device includes described in claim 6 or 7
Array base palte.
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| CN201620450032.6U CN205609532U (en) | 2016-05-17 | 2016-05-17 | Thin film transistor and array substrate , display device |
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| CN201620450032.6U CN205609532U (en) | 2016-05-17 | 2016-05-17 | Thin film transistor and array substrate , display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105845737A (en) * | 2016-05-17 | 2016-08-10 | 京东方科技集团股份有限公司 | Thin film transistor, manufacture method thereof, array substrate and display device |
| CN107221503A (en) * | 2017-06-02 | 2017-09-29 | 京东方科技集团股份有限公司 | A kind of preparation method of thin film transistor (TFT), thin film transistor (TFT) and display base plate |
| CN109411547A (en) * | 2018-10-31 | 2019-03-01 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT) and preparation method, display base plate and preparation method, display device |
| CN112713138A (en) * | 2020-12-28 | 2021-04-27 | 上海天马有机发光显示技术有限公司 | Flexible substrate and display panel |
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2016
- 2016-05-17 CN CN201620450032.6U patent/CN205609532U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105845737A (en) * | 2016-05-17 | 2016-08-10 | 京东方科技集团股份有限公司 | Thin film transistor, manufacture method thereof, array substrate and display device |
| US20180197998A1 (en) | 2016-05-17 | 2018-07-12 | Boe Technology Group Co., Ltd. | Thin film transistor, array substrate, and display apparatus, and fabrication methods thereof |
| US10269984B2 (en) | 2016-05-17 | 2019-04-23 | Beijing Boe Display Technology Co., Ltd. | Thin film transistor, array substrate, and display apparatus, and fabrication methods thereof |
| CN105845737B (en) * | 2016-05-17 | 2019-07-02 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and its manufacturing method, array substrate, display device |
| CN107221503A (en) * | 2017-06-02 | 2017-09-29 | 京东方科技集团股份有限公司 | A kind of preparation method of thin film transistor (TFT), thin film transistor (TFT) and display base plate |
| CN109411547A (en) * | 2018-10-31 | 2019-03-01 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT) and preparation method, display base plate and preparation method, display device |
| CN112713138A (en) * | 2020-12-28 | 2021-04-27 | 上海天马有机发光显示技术有限公司 | Flexible substrate and display panel |
| CN112713138B (en) * | 2020-12-28 | 2024-05-17 | 武汉天马微电子有限公司 | Flexible substrate and display panel |
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