CN102955127A

CN102955127A - Debugging method for large-scale field programmable gate array (FPGA) design

Info

Publication number: CN102955127A
Application number: CN2011102549857A
Authority: CN
Inventors: 龚永鑫
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2011-08-31
Filing date: 2011-08-31
Publication date: 2013-03-06
Anticipated expiration: 2031-08-31
Also published as: CN102955127B

Abstract

The invention provides a debugging method for large-scale field programmable gate array (FPGA) design, and mainly aims to provide a relatively general debugging method. By the debugging method, the time of debugging an FPGA prototype is saved, and the efficiency of debugging the FPGA prototype is improved. The main theory is that a redundant control logic is designed; and a main machine end configures a corresponding register of the control logic through operation of a universal asynchronous receiver/transmitter (UART), so that an external test pin is selectively connected to a signal to be tested in a certain FPGA chip. By the method, the structure is simple; the method is easy to implement; the external test pin can test a plurality of inner signals to be tested of the FPGA chips; and during test, the inner signals to be tested of certain FPGA chips can be freely selected, and the signals are not required to be grouped in advance.

Description

A kind of adjustment method for large-scale F PGA design

Technical field

The present invention relates to the FPGA design field, relate in particular to the adjustment method in a kind of FPGA design.

Background technology

In recent years, along with the scale of FPGA design is increasing, the scale of fpga chip is also increasing, and the impact on project process in the debugging on the FPGA prototype has seemed most important.For example, in a WLAN (wireless local area network) FPGA design, debugging occupies very large ratio, so the debugging of accelerating on the FPGA prototype can the Effective Raise project process.

Now, about the debugging on the FPGA prototype, some debugging acid and methods relatively more commonly used are also arranged on the market, such as, directly the modification code arrives the external testing pin with the signal assign of needs, Embedded logic analyser, FPGA Editor guides to the external testing pin with internal signal, the dynamic probes that Agilent is released etc.

Some method need to re-start FPGA placement-and-routing, can cause the huge waste of time cost.

Some method need to be with the BRAM resource of FPGA inside, and the data acquisition storage depth is limited, sometimes needs the signal time observed longer in the debugging of large-scale F PGA design, and these class methods also have its limitation.

Also have certain methods can realize in the test of a pin to a plurality of inner measured signals, but need to set in advance grouping, can not realize a pin to the selection of any one inside measured signal, need in addition the separately software cooperation of producer, testing cost is more expensive.

This invention can realize not re-starting FPGA placement-and-routing, and main frame is tested a plurality of inner measured signals by external testing pin of UART interface operation steering logic realization, and does not need to pre-set grouping.

Summary of the invention

The invention provides a kind of adjustment method that is applicable in the large-scale F PGA design, fundamental purpose is the debugging efficiency that improves on the FPGA prototype, reduces testing cost, and can realize that an external testing pin is to the selection of any one inside measured signal.Cardinal principle is that steering logic that main frame passes through UART interface operation FPGA inside realizes being connected of inner measured signal and external testing pin.

At first, set in advance inner measured signal, suppose to have 2 ^NIndividual signal to be observed, in advance this 2 ^NIndividual signal is made as inner measured signal and is connected to the steering logic of FPGA inside, and N is the integer more than or equal to 1; The steering logic of FPGA inside be input as 2 ^NIndividual inner measured signal, the external testing pin of FPGA is received in the output of FPGA, the case of external test pin is X altogether, the steering logic of FPGA is carried out register configuration by UART, each register bit wide is N, which inner measured signal X external testing pin of configurable X register control is connected to, and final, the external testing pin is connected to inner measured signal.

The advantage of the method:

Do not need to re-start FPGA placement-and-routing, reduce time cost.

Can realize that an external testing pin to the selection of any one inside measured signal, does not need to pre-set grouping.

Description of drawings

Accompanying drawing 1 is the hardware connection layout for the adjustment method of large-scale F PGA design.

Accompanying drawing 2 is this adjustment method FPGA inner control logic schematic diagrams.

Embodiment

Below in conjunction with accompanying drawing, specify the present invention.

The invention provides a kind of adjustment method that is applicable in the large-scale F PGA design, fundamental purpose is the debugging efficiency that improves on the FPGA prototype, reduces testing cost, and can realize that an external testing pin is to the selection of any one inside measured signal.Cardinal principle is that the steering logic by main frame UART interface operation FPGA inside realizes being connected of inner measured signal and external testing pin.

At first, need to set in advance inner measured signal, suppose to have 2 ^NIndividually want the signal observed, so need to be when design in advance this 2 ^NIndividual signal is made as the steering logic that inner measured signal is connected to FPGA inside.

Steering logic is input as 2 ^NIndividual inner measured signal, export and receive the external testing pin, suppose that the external testing pin is received in output individual for X altogether, steering logic is similar to and is equivalent to 1 MUX selector switch that can carry out by UART register configuration, one total configurable register X is individual, and each register bit wide is N.Can be found out by accompanying drawing 1 and accompanying drawing 2, a configurable X register (sel_0～sel_X-1) is by main frame UART configuration, control X external testing pin (out[0]～out[X-1]) be connected to which inner measured signal (test[0]～test[2 ^N-1]), the inner realization of concrete FPGA is equivalent to a large MUX selector switch, after sel_n is made as a fixed value, external testing pin out[n] be connected to inner measured signal test[sel_n], for example: when sel_0 is made as fixed value 5, be out[0 so] be connected to test[5].Hence one can see that, and the method external testing pin (out[0]～out[X-1]) can be connected to any one of inner measured signal.

Claims

1. an adjustment method that is used for large-scale F PGA design is characterized in that, main frame realizes that by UART interface operation steering logic step is as follows in being connected of inner measured signal and external testing pin:

Set inner measured signal, suppose to have 2 ^NIndividual signal to be observed, in advance this 2 ^NIndividual signal is made as inner measured signal and is connected to the steering logic of FPGA inside, and N is the integer more than or equal to 1; The steering logic of FPGA inside be input as 2 ^NIndividual inner measured signal, the external testing pin of FPGA is received in the output of FPGA, the case of external test pin is X altogether, the steering logic of FPGA is carried out register configuration by UART, which inner measured signal X external testing pin of configurable X register control is connected to, finally, the external testing pin is connected to inner measured signal.