CN102905468A - 一种具有单一反射结构的印刷电路板及利用其的发光二极管封装制造方法 - Google Patents
一种具有单一反射结构的印刷电路板及利用其的发光二极管封装制造方法 Download PDFInfo
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- CN102905468A CN102905468A CN2012102665689A CN201210266568A CN102905468A CN 102905468 A CN102905468 A CN 102905468A CN 2012102665689 A CN2012102665689 A CN 2012102665689A CN 201210266568 A CN201210266568 A CN 201210266568A CN 102905468 A CN102905468 A CN 102905468A
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- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
Abstract
本发明涉及一种具有单一反射结构的印刷电路板及利用其的发光二极管封装制造方法,其中,在一个封装内使用一个以上芯片来构成发光二极管封装的情况下,在芯片之间构成单一反射构造物,从而防止芯片之间的光的再吸收,其包括:印刷电路板;配线图形形成用物质层,其形成在所述印刷电路板上,并且在其之间形成有绝缘层;坝,其形成在以所述印刷电路板的芯片安装区域为中心的其周围的配线图形形成用物质层上;光再吸收防止用坝,其形成在装载有所述芯片安装区域内的发光二极管芯片的区域之间的配线图形形成用物质层上。
Description
技术领域
本发明涉及发光二极管封装,具体涉及具有单一反射结构的印刷电路板及利用其的发光二极管封装制造方法,其中,在一个封装内使用一个以上芯片来构成LED封装的情况下,在芯片之间构成单一反射构造物,从而能够防止芯片之间的光的再吸收。
背景技术
发光二极管利用半导体的p-n接合结构来制造出注入的少数载体(电子或空穴),并且其作为通过所述少数载体的再结合进行发光的电子部件。
如上所述的发光二极管使用在各种领域,最近由于发光二极管的寿命为半永久性且不存在有害物质环境管制(RoHS、ELV、PFOS等)物质,因此被瞩目为将代替荧光灯的部件。
通常地,单一的发光二极管单元在引线框架上用例如Ag接合发光二极管芯片,并且在将半导体芯片的N片和P片进行引线接合之后,通过环氧树脂的模压进行封装。
如上所述构成的单一的发光二极管封装为了散热而以如下方式使用,即在散热板上装载的状态下设置于印刷电路基板上而使用,或者在利用例如表面安装技术(SMT)等来安装在印刷电路板上的状态下粘贴在散热板上而使用。
另外,例如,使用于LCD背光灯等的发光二极管阵列单元中,将如上所述构成的多个单一发光二极管封装按照阵列形状利用例如表面安装技术(SMT)等来设置在印刷电路板上。
并且,如上所述构成的发光二极管的阵列为了散热而粘贴在散热板上而使用。
如上所示,现有技术中,为了制造发光二极管单元,将与引线框架的制造、散热板的制造、发光二极管的制造、印刷电路板的制造、发光二极管封装的安装等具有各自不同特性的制造工艺进行集合。
换句话说,一个制造企业很难单独制造出发光二极管单元,应该通过各自不同企业的协作才可以制造。因此,存在如下问题:发光二极管单元的制造工艺复杂,并且增加发光二极管单元的制造费用。
另外,现有技术中,将发光二极管芯片安装在引线框架后进行封装,并且由于将所述发光二极管封装安装在印刷电路板上,因此,具有如下问题:在整体上发光二极管单元的厚度会更加厚,从而采用如上所述的发光二极管单元的电子产品的薄型化会受到障碍。
特别是,现有技术中,为了发光二极管的散热,通过将发光二极管芯片安装在引线框架进行封装之后,以散热板作为媒介将所述发光二极管封装设置在印刷电路板上,或者将发光二极管封装安装在印刷电路板后,将印刷电路板结合在散热板上。
由此,发光二极管单元的整体厚度会更加厚,从而存在采用如上所述的发光二极管单元的电子产品的薄型化会受到障碍的问题。
如上所述的现有技术的发光二极管单元有限于提高发光的光的波长变换效率,从而很难提高光功率或者亮度、显色性。
为了解决如上所述的问题,从而提出了如下结构:在散热基底的发光二极管芯片安装区域形成具有反射面的反射槽,并且装载发光二极管。
但是,在如上所述的发光二极管封装的情况下,如果在反射槽内安装有一个以上的发光二极管芯片时,则发生如下问题:由于邻接的发光二极管芯片之间的光的再吸收,从而降低光功率。
图1是表示如下问题:由于板上芯片(COB,Chip On Board)和热沉芯片(COH,Chip On Heat-sink)方式的发光二极管封装中的芯片之间的光的再吸收而降低光功率,图2是表示如下问题:由于金属芯片(COM,Chip On Metal)方式的发光二极管封装的芯片之间的光的再吸收而降低光功率。
图1是表示板上芯片(Chip On Board)和热沉芯片(Chip On Heat-sink)方式的发光二极管封装结构,其中,印刷电路板是通常作为FR4或者金属印刷电路板10而使用的FR4印刷电路板(使用板上芯片方式的印刷电路板)及金属印刷电路板(使用热沉芯片方式的印刷电路板),并且使用由50~100?的绝缘层(Adhesive Layer)11和1/2盎司(大约17?)或者1盎司(大约34?)的Cu层构成的产品。
另外,Ni、Ag层作为镀金层,其用于通过板上芯片及热沉芯片方法进行发光二极管封装,为了进行引线接合(wire bonding),从而形成Ag层,但是在Cu层上不能直接镀Ag,因此通过镀金等方法形成Ni层,其作为用于镀Ag的缓冲层。
通过如上所述工艺形成配线图形形成用的物质层12、13、14,并且形成一定高度的坝(DAM)16,所述坝16用于防止在涂覆荧光体或者硅酮时产生的扩散等现象,并且装载有发光二极管芯片15a、15b。
在如上所述的结构中,在发光二极管芯片15a和与此相邻的其他发光二极管15b之间产生光的再吸收,从而降低光功率。
并且,图2是表示金属芯片(COM,Chip On Metal)方式的发光二极管封装结构,金属芯片方式是在金属圆板(或者已表面处理的金属圆板)20上直接装载发光二极管芯片的方式,发光二极管芯片25a、25b、25c、25d、25e直接装载在金属圆板20表面,并且通过单独的印刷电路板制造工艺及Ni、Ag镀金工艺等制造出具有电性的图形层21、22、23、24后,通过热压(Hot Press)工艺等对金属圆板和通过所述工艺制造的印刷电路板进行层压,从而制造出金属芯片方式的金属印刷电路板。
通过所述工艺形成的金属芯片方式的金属印刷电路板的图形层具有如下结构:利用具有优秀导电性的Cu、Ni、Ag等物质来形成第一、二、三配线图形形成用物质层22、23、24,并且形成一定高度的坝(DAM)26,所述坝26用于防止在涂覆荧光体或硅酮时产生的扩散等现象,并且发光二极管芯片25a、25b、25c、25d、25e装载在金属圆板20表面。
在如上所述的结构中,在发光二极管芯片25a、25b、25c、25d、25e之间产生光的再吸收,从而降低光功率。
发明内容
本发明用于解决如上所述的现有技术的发光二极管封装的问题,其目的在于提供一种具有单一反射结构的印刷电路板及利用其的发光二极管封装制造方法,其中,在一个封装内使用一个以上芯片来构成发光二极管封装的情况下,在芯片之间构成单一反射构造物,从而能够防止芯片之间的光的再吸收。
本发明的目的在于提供一种具有单一反射结构的印刷电路板及利用其的发光二极管封装制造方法,其中,在一个封装内利用一个以上的发光二极管芯片来构成发光二极管封装的情况下,在各个发光二极管芯片之间设置印刷或者排出或者构造物等,从而防止发光二极管芯片之间的光的再吸收,进而提高光功率。
本发明的目的在于提供一种具有单一反射结构的印刷电路板及利用其的发光二极管封装制造方法,其中,通过板上芯片(Chip On Board)和热沉芯片(Chip On Heat-sink)方式或者金属芯片(ChipOn metal)方式对印刷电路板电路进行加工及制造,并且使用白墨水来在芯片和芯片之间印刷用于单一反射的坝,从而防止发光二极管之间的光的再吸收,进而提高光功率。
本发明的目的在于提供一种具有单一反射结构的印刷电路板及利用其的发光二极管封装制造方法,其中,通过如下方式进行在各个发光二极管芯片之间设置用于单一反射的结构的工艺:在使用白墨水的印刷方式或者涂覆坝形成用物质后对其进行硬化的方式或者直接形成反射构造物的方式中选择适合于封装结构及进行工艺方式的方式,从而提高工艺的效率性。
本发明的目的不限于以上提及的目的,并且所属领域的技术人员从以下记载的内容中会明确地理解没有提及的其他目的。
根据用于实现如上所述目的的本发明的具有单一反射结构的印刷电路板,其包括:印刷电路板或者金属印刷电路板;配线图形形成用物质层,其形成在所述印刷电路板或者金属印刷电路板上,并且在其之间形成有绝缘层;坝,其形成在所述印刷电路板或者金属印刷电路板上以芯片安装区域为中心的其周围的配线图形形成用物质层上;光再吸收防止用坝,其形成在装载有所述芯片安装区域内的发光二极管芯片的区域之间的配线图形形成用物质层上。
在此,所述印刷电路板通过板上芯片(Chip On Board)或者热沉芯片(Chip On Heat-sink)方式在一个封装内装载一个以上的发光二极管芯片。
根据用于实现其他目的的本发明的具有单一反射结构的印刷电路板,其包括:金属圆板;配线图形,其层压于所述金属圆板上;电气性的图形层将通过单独的印刷电路板制造工艺及Ni、Ag镀金工艺制造的印刷电路板和金属圆板(或者已表面处理的金属圆板)通过热压(HotPress)工艺等进行层压,从而制造出金属芯片方式的金属印刷电路板。
并且还包括:坝,其形成在以所述金属圆板的芯片安装区域为中心的其周围的配线图形上;光再吸收防止用坝,其形成在装载有所述芯片安装区域内的发光二极管芯片的区域之间的所述金属圆板的表面。
在此,所述印刷电路板通过金属芯片(Chip On Metal)方式在一个封装内装载有多个发光二极管芯片。
并且,通过如下方式形成所述光再吸收防止用坝:使用白墨水来反复进行印刷的方式,或者涂覆坝形成用物质并对其进行硬化,或者对反射构造物进行层压的方式。
根据用于实现其他目的的本发明的一种利用具有单一反射结构的印刷电路板的发光二极管封装制造方法,其包括如下步骤:在金属圆板上形成配线图形形成用物质层,在所述物质层之间形成有绝缘层;将坝及光再吸收防止用坝分别形成在以所述金属圆板的芯片安装区域为中心的其周围的配线图形形成用物质层上及装载有所述芯片安装区域内的发光二极管芯片的区域之间的配线图形形成用物质层上;将发光二极管芯片接合在所述芯片安装区域之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管芯片的电极与焊垫进行电连接的引线接合工艺。
在此,通过如下方式形成所述坝(DAM)及光再吸收防止用坝:使用白墨水来多次反复进行印刷操作,或者利用分配器来排出坝形成用物质并对其进行硬化,或者对反射构造物进行层压。
根据用于实现其他目的的本发明的一种利用具有单一反射结构的印刷电路板的发光二极管封装制造方法,其包括如下步骤:在装载有发光二极管芯片的区域之间的所述金属圆板的表面使用白墨水并通过反复的印刷操作来形成光再吸收防止用坝;在印刷电路板上形成配线图形,并且在印刷电路板表面上使用白墨水并通过反复的印刷操作来以芯片安装区域为中心在其周围的配线图形层上形成坝;将形成有配线图形层及坝的印刷电路板层压于形成有所述光再吸收防止用坝的金属圆板上;将发光二极管芯片接合于所述芯片安装区域之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管的电极与焊垫进行电连接的引线接合工艺。
根据用于实现其他目的的本发明的一种利用具有单一反射结构的印刷电路板的发光二极管封装制造方法,其包括如下步骤:在印刷电路板上形成配线图形层,并且在印刷电路板表面使用白墨水并通过反复的印刷操作来以芯片安装区域为中心在其周围的配线图形上形成坝;将形成有配线图形层及坝的印刷电路板层压于金属圆板上;在安装有发光二极管芯片的金属圆板表面利用分配器来排出坝形成用物质并对其进行硬化,从而形成光再吸收防止用坝;将发光二极管芯片接合于所述芯片安装区域之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管芯片的电极与焊垫进行电连接的引线接合工艺。
根据用于实现其他目的的本发明的一种利用具有单一反射结构的印刷电路板的发光二极管封装制造方法,其包括如下步骤:在印刷电路板上形成配线图形层,并且将形成有配线图形层的印刷电路板层压于金属圆板上;在安装有发光二极管芯片的金属圆板表面及印刷电路板上面利用分配器来排出坝形成用物质并对其进行硬化,从而以芯片安装区域为中心在其周围的配线图形上形成坝及在金属圆板表面形成光再吸收防止用坝;将发光二极管芯片接合于所述芯片安装区域之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管芯片的电极与焊垫进行电连接的引线接合工艺。
在此,在所述坝及在金属圆板表面形成光再吸收防止用坝的步骤中,在坝形成区域直接对反射构造物进行层压而形成。
根据如上所述的具有单一反射结构的印刷电路板及利用其的发光二极管封装制造方法具有如下效果:
第一、在一个封装内使用一个以上芯片来构成发光二极管封装的情况下,在芯片之间构成单一反射构造物,从而防止芯片之间的光的再吸收。
第二、在芯片和芯片之间对用于单一反射的坝进行印刷,从而防止发光二极管芯片之间的光的再吸收,进而提高光功率。
第三、通过如下方式进行在各个发光二极管芯片之间设置用于单一反射的结构的工艺:在使用白墨水的印刷方式或者涂覆坝形成用物质后对其进行硬化的方式或者直接对反射构造物进行层压的方式中选择适合于封装结构及进行工艺方式的方式,从而提高工艺的效率性。
第四、在通过板上芯片(Chip On Board)或者热沉芯片(Chip On Heat-sink)方式或者金属芯片(Chip On Metal)方式对印刷电路板电路进行加工及制造的工艺中可选择性地适用形成单一反射构造物的工艺,从而确保工艺的容易性。
附图说明
图1是板上芯片(Chip On Board)和热沉芯片(Chip On Heat-sink)方式的发光二极管封装的构成图。
图2是金属芯片(Chip On Metal)方式的发光二极管封装的构成图。
图3是根据本发明的一个实施例的板上芯片(Chip On Board)和热沉芯片(Chip On Heat-sink)方式的发光二极管封装的构成图。
图4是根据本发明的另一个实施例的金属芯片(Chip On Metal)方式的发光二极管封装的构成图。
图5a和图5b是根据本发明的一个实施例的板上芯片(Chip On Board)和热沉芯片(Chip On Heat-sink)方式的发光二极管封装的平面构成图及进行工艺的流程图。
图6a至图6e是根据本发明的另一个实施例的金属芯片(Chip On Metal)方式的发光二极管封装平面构成图及进行工艺的流程图。
具体实施方式
以下,对根据本发明的具有单一反射结构的印刷电路板及利用其的发光二极管封装制造方法的优选实施例进行详细说明。
通过以下各个实施例的详细说明会更清楚地理解根据本发明的具有单一反射结构的印刷电路板及利用其的发光二极管制造方法的特征及优点。
图3是根据本发明的一个实施例的板上芯片(Chip On Board)和热沉芯片(Chip On Heat-sink)方式的发光二极管封装的构成图,图4是根据本发明的另一个实施例的金属芯片(Chip On Metal)方式的发光二极管封装的构成图。
在一个封装内使用一个以上芯片来构成发光二极管封装的情况下,在芯片之间构成单一反射构造物,从而防止芯片之间光的再吸收,进而提高光功率。
在以下说明中意味着,金属圆板使用通过表面处理提高反射、光泽特性的金属,并且金属的表面处理中,在铝板上进行涂层、喷镀、层压、溅射工艺中任何一个工艺,从而提高反射、光泽特性。
如图3所示,根据本发明的一个实施例的板上芯片(Chip On Board)和热沉芯片(Chip On Heat-sink)方式的发光二极管封装中,印刷电路板是通常作为FR4或者金属印刷电路板10而使用的FR4印刷电路板(使用板上芯片方式的印刷电路板)及金属印刷电路板(使用热沉芯片方式的印刷电路板),并且使用由50~100?的绝缘层(AdhesiveLayer)11和1/2盎司(大约17?)或者1盎司(大约34?)的Cu层构成的产品。
换句话说,在印刷电路板或者金属印刷电路板30上使用50~100?的绝缘层(Adhesive Layer)并利用具有优秀的导电性的Cu、Ni、Ag等物质来形成第一、二、三配线图形形成用物质层32、33、34,并且以芯片安装区域为中心在周围形成一定高度的坝(DAM)36a、36b,所述坝36a、36b用于防止涂覆荧光体或者硅酮时产生的扩散等现象,并且形成在装载有芯片安装区域内的芯片的区域之间形成的光再吸收防止用坝36c,并且装载发光二极管芯片35a、35b。
在此,通过如下方式形成所述光再吸收防止用坝36c:使用白墨水来反复进行印刷的方式,或者涂覆坝形成用物质并对其进行硬化,或者直接对反射构造物进行层压的方式。
在如上所述的结构中,在发光二极管芯片35a和与此相邻的其他发光二极管芯片35b之间形成光再吸收防止用坝36c,从而防止发光二极管芯片35a和与此相邻的其他发光二极管芯片35b之间的光再吸收,从而提高光功率。
并且,如图4所示,根据本发明的另一个实施例的的金属芯片(ChipOn Metal)方式的发光二极管封装,其包括:金属圆板(或者已表面处理的金属圆板)40;配线图形42、43、44,其层压于所述金属圆板40上;一定高度的坝(DAM)46a、46b,其形成在以所述金属圆板40的芯片安装区域为中心的其周围的配线图形上,并且用于防止在涂覆荧光体或者硅酮时产生的扩散等现象;光再吸收防止用坝46c,其形成在装载有所述芯片安装区域内的发光二极管芯片45a、45b、45c、45d、45e的区域之间的所述金属圆板的表面。
在如上所述的结构中,在发光二极管芯片45a、45b、45c、45d、45e之间形成光再吸收防止用坝46c,从而防止发光二极管芯片45a、45b、45c、45d、45e之间的光的再吸收,进而提高光功率。
在此,通过如下方式形成光再吸收防止用坝46c:使用白墨水来反复进行印刷的方式,或者涂覆坝形成用物质并对其进行硬化,或者直接对反射构造物进行层压的方式。
如下是根据如上所述的本发明的利用具有单一反射结构的印刷电路板的发光二极管封装制造方法。
图5a和图5b是根据本发明的一个实施例的板上芯片(Chip On Board)和热沉芯片(Chip On Heat-sink)方式的发光二极管封装的平面构成图及进行工艺的流程图。
首先,如图5a所示,根据本发明的一个实施例的板上芯片(Chip OnBoard)和热沉芯片(Chip On Heat-sink)方式的发光二极管封装结构中,印刷电路板是通常作为FR4或者金属印刷电路板10而使用的FR4印刷电路板(使用板上芯片方式的印刷电路板)及金属印刷电路板(使用热沉芯片方式的印刷电路板),并且使用由50~100?的绝缘层(Adhesive Layer)11和1/2盎司(大约17?)或者1盎司(大约34?)的Cu层构成的产品。
另外,Ni、Ag层作为镀金层,其用于通过板上芯片及热沉芯片方法进行发光二极管封装,为了进行引线接合,需要形成Ag层,但是在Cu层上不能直接镀Ag,因此通过镀金等方法形成Ni层,其作为用于镀Ag的缓冲层。
通过如上所述工艺形成配线图形形成用的物质层,并且形成一定高度的坝(DAM),所述坝用于防止在涂覆荧光体或者硅酮时产生的扩散等现象,并且装载有发光二极管芯片。
换句话说,在印刷电路板或者金属印刷电路板上利用具有优秀的导电性的Cu、Ni、Ag等物质来形成第一、二、三配线图形形成用物质层,并且形成一定高度的坝(DAM)及光再吸收防止用坝,所述坝以芯片安装区域为中心形成在周围,并且用于防止在涂覆荧光体或者硅酮时产生的扩散等现象,所述光再吸收防止用坝形成在装载有芯片安装区域内的芯片的区域之间,并且在芯片安装区域装载发光二极管芯片。
首先,板上芯片(Chip On Board)和热沉芯片(Chip On Heat-sink)方式是通过通常使用的印刷电路板制造工艺制造印刷电路板(S501)。
即,印刷电路板或者金属印刷电路板是通常使用的FR4印刷电路板(使用板上芯片方式的印刷电路板)及金属印刷电路板(使用热沉芯片方式的印刷电路板),并且使用由50~100?的绝缘层(Adhesive Layer)和1/2盎司(大约17?)或者1盎司(大约34?)的Cu层构成的产品,从而通过作为印刷电路板制造工艺的露光、蚀刻等工艺制造出作为板上芯片和热沉芯片而使用的印刷电路板。
并且,Ni、Ag层作为镀金层,其用于通过板上芯片及热沉芯片方法进行发光二极管封装,为了进行引线接合,需要形成Ag层,但是在Cu层上不能直接镀Ag,因此通过镀金等方法形成Ni层,其作为用于镀Ag的缓冲层。
换句话说,将Ni作为第二配线图形形成用物质层而使用,以便解决如下问题:在作为第一配线图形形成用物质层而使用的Cu层上很难直接涂覆作为第三配线图形形成用物质层而使用的Ag。
并且,作为第三配线图形形成用物质层而使用的Ag用于改善反射率,并且能够确保进行引线接合工艺时的工艺容易性。
并且,在形成作为第一配线图形形成用物质层而使用的Cu层的工艺中,形成掩模层,并且通过溅射工艺可选择性地形成在所需的区域。
接着,形成一定高度的坝(DAM)及光再吸收防止用坝,所述坝以芯片安装区域为中心形成在周围,并且用于防止在涂覆荧光体或者硅酮时产生的扩散等现象,所述光再吸收防止用坝形成在装载有芯片安装区域内的芯片的区域之间。
坝(DAM)及光再吸收防止用坝的形成工艺中,其包括如下方法:使用白墨水来多次反复进行印刷操作(S502),或者利用分配器来排出坝形成用物质并对其进行硬化(S503、),或者对反射构造物进行层压(S504),并且可选择性地适用坝(DAM)形成工艺,以便适合于产品的特性。
在此,坝(DAM)形成在以印刷电路板或者金属印刷电路板的芯片安装区域为中心的其周围的配线图形形成用物质层上,并且光再吸收防止用坝形成在装载有芯片安装区域内的发光二极管芯片的区域之间的配线图形形成用物质层上。
接着,将发光二极管芯片接合在所述芯片安装区域之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管芯片的电极与焊垫进行电连接的引线接合工艺(S505)。
如下是根据本发明的另一个实施例的金属芯片(Chip On Metal)方式的发光二极管封装结构及制造工艺。
图6a至图6e是根据本发明的另一个实施例的金属芯片(Chip On Metal)方式的发光二极管封装平面构成图及工艺进行流程图。
如图6a所示,根据本发明的另一个实施例的金属芯片(Chip On Metal)方式的发光二极管封装中,将金属圆板(或者已表面处理的金属圆板)和印刷电路板通过热压(Hot Press)工艺进行层压,所述印刷电路板通过单独的印刷电路板制造工艺及Ni、Ag镀金工艺等制造,从而制造出金属芯片方式的金属印刷电路板。
通过所述工艺形成的金属芯片方式的金属印刷电路板的图形层构成为,利用具有优秀的导电性的Cu、Ni、Ag等物质来形成第一、二、三配线图形形成用物质层,并且形成一定高度的坝(DAM)及光再吸收防止用坝,所述坝以芯片安装区域为中心形成在周围,并且用于防止在涂覆荧光体或者硅酮时产生的扩散等现象,所述光再吸收防止用坝形成在装载有芯片安装区域内的芯片的区域之间,并且将发光二极管芯片装载在金属圆板表面。
如图6b所示,根据金属芯片(Chip On Metal)方式的一个实施例的工艺中,首先,在金属圆板表面利用白墨水并通过多次反复的印刷操作来形成光再吸收防止用坝(S601)。
接着,在印刷电路板上利用具有优秀的导电性的Cu、Ni、Ag等物质来形成第一、二、三配线图形形成用物质层,并且通过溅射形成配线图形层,并且在印刷电路板表面利用白墨水并通过多次反复的印刷操作来形成一定高度的坝(DAM),所述坝以芯片安装区域为中心形成在周围,并且用于防止在涂覆荧光体或者硅酮时产生的扩散等现象(S602)。
并且,将形成有配线图形层及坝的印刷电路板层压于形成有所述光再吸收防止用坝的金属圆板上,从而制造出金属芯片方式的印刷电路板(S603)。
接着,将发光二极管芯片接合在所述芯片安装区域之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管芯片的电极与焊垫进行电连接的引线接合工艺(S604)。
并且,如图6c所示,根据金属芯片(Chip On Metal)方式的另一个实施例的工艺中,首先,准备金属圆板(S611),并且在印刷电路板上利用具有优秀的导电性的Cu、Ni、Ag等物质来形成第一、二、三配线图形形成用物质层,并且对其进行图形化后形成配线图形层,并且在印刷电路板表面利用白墨水并通过多次反复的印刷操作来以芯片安装区域为中心在周围形成一定高度的坝(DAM),所述坝用于防止在涂覆荧光体或者硅酮时产生的扩散等现象(S612)。
接着,将形成有配线图形层及坝的印刷电路板层压于金属圆板上,从而制造出金属芯片方式的印刷电路板(S613)。
并且,在安装有发光二极管芯片的金属圆板表面利用分配器来排出坝形成用物质并对其进行硬化,从而形成光再吸收防止用坝(S614)。
接着,将发光二极管芯片接合在所述芯片安装区间之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管芯片的电极与焊垫进行电连接的引线接合工艺(S615)。
并且,如图6d所示,根据金属芯片(Chip On Metal)方式的另一个实施例的工艺中,首先,准备金属圆板(S621),并且在印刷电路板上利用具有优秀的导电性的Cu、Ni、Ag等物质来形成第一、二、三配线图形形成用物质层,并且对其进行图形化后形成配线图形层(S622)。
接着,将形成有配线图形层的印刷电路板层压于金属圆板上,从而制造出金属芯片方式的印刷电路板(S623)。
并且,在安装有发光二极管芯片的金属圆板表面及印刷电路板上面利用分配器来排出坝形成用物质并对其进行硬化,从而在印刷电路板上面以芯片安装区域为中心在周围形成一定高度的坝(DAM),所述坝用于防止在涂覆荧光体或者硅酮时产生的扩散等现象,并且在金属圆板表面形成光再吸收防止用坝(S624)。
接着,将发光二极管芯片接合在所述芯片安装区域之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管芯片的电极与焊垫进行电连接的引线接合工艺(S625)。
并且,如图6e所示,根据金属芯片(Chip On Metal)方式的另一个实施例的工艺中,首先,准备金属圆板(S631),并且在印刷电路板上利用具有优秀的导电性的Cu、Ni、Ag等物质来形成第一、二、三配线图形形成用物质层,并且对其进行图形化后形成配线图形层(S632)。
接着,将形成有配线图形层的印刷电路板层压于金属圆板上,从而制造出金属芯片方式的印刷电路板(S633)。
并且,在安装有发光二极管芯片的金属圆板表面及印刷电路板上面利用分配器来排出坝形成用物质并对其进行硬化,从而在印刷电路板上面以芯片安装区域为中心在周围形成一定高度的坝(DAM),所述坝用于防止在涂覆荧光体或者硅酮时产生的扩散等现象,并且在金属圆板表面形成光再吸收防止用坝(S634)。
在此,在形成坝及光再吸收防止用坝的工艺时,在利用分配器的方式之外,可根据工艺进行的状况在坝形成区域直接对反射构造物进行层压而形成(S635)。
接着,将发光二极管芯片接合在所述芯片安装区域之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管芯片的电极与焊垫进行电连接的引线接合工艺(S636)。
根据如上所述的本发明的具有单一反射结构的印刷电路板及利用其的发光二极管封装制造方法,其中,在一个封装内使用一个以上芯片来构成LED封装的情况下,在芯片之间构成单一反射构造物,从而能够防止芯片之间的光的再吸收。
由此,防止发光二极管之间的光的再吸收,从而提高光功率,并且都可适用于板上芯片(Chip On Board)和热沉芯片(Chip On Heat-sink)方式或者金属芯片(Chip On metal)方式的印刷电路板,从而提高工艺的效率性。
如上说明所示,可理解成在不脱离本发明的本质特性的范围内,本发明体现为变形的形状。
因此,示出的实施例应理解为说明性的观点,而不是限定性的观点,并且本发明的范围显示在权利要求范围,而不是所述的说明,并且在与其等同的范围内的所有不同点应理解成包括在本发明中。
Claims (13)
1.一种具有单一反射结构的印刷电路板,其包括:
印刷电路板;
配线图形形成用物质层,其形成在所述印刷电路板上,并且在其之间形成有绝缘层;
坝,其形成在以所述印刷电路板的芯片安装区域为中心的其周围的配线图形形成用物质层上;
光再吸收防止用坝,其形成在装载有所述芯片安装区域内的发光二极管芯片的区域之间的配线图形形成用物质层上。
2.根据权利要求1所述的具有单一反射结构的印刷电路板,其特征在于:
所述印刷电路板中,通过板上芯片(Chip On Board)或者热沉芯片(Chip On Heat-sink)方式在一个封装内装载一个以上的发光二极管芯片。
3.一种具有单一反射结构的印刷电路板,其特征在于,包括:
金属圆板;
配线图形,其层压于所述金属圆板上;
坝,其形成在以所述金属圆板的芯片安装区域为中心的其周围的配线图形上;
光再吸收防止用坝,其形成在装载有所述芯片安装区域内的发光二极管芯片的区域之间的所述金属圆板的表面。
4.根据权利要求3所述的具有单一反射结构的印刷电路板,其特征在于:
所述金属圆板使用通过表面处理提高反射、光泽特性的金属。
5.根据权利要求4所述的具有单一反射结构的印刷电路板,其特征在于:
金属的表面处理中,在铝板上进行涂层、喷镀、层压、溅射工艺中任何一个工艺,从而提高反射、光泽特性。
6.根据权利要求3所述的具有单一反射结构的印刷电路板,其特征在于:
所述印刷电路板中,通过金属芯片(Chip On Metal)方式在一个封装内装载有多个发光二极管芯片。
7.根据权利要求1或者3所述的具有单一反射结构的印刷电路板,其特征在于:
通过如下方式形成所述光再吸收防止用坝:使用白墨水来反复进行印刷的方式,或者涂覆坝形成用物质并对其进行硬化,或者直接对反射构造物进行层压的方式。
8.一种利用具有单一反射结构的印刷电路板的发光二极管封装制造方法,其包括如下步骤:
在金属圆板上形成配线图形形成用物质层,在所述物质层之间形成有绝缘层;
将坝及光再吸收防止用坝分别形成在以所述金属圆板的芯片安装区域为中心的其周围的配线图形形成用物质层上及装载有所述芯片安装区域内的发光二极管芯片的区域之间的配线图形形成用物质层上;
将发光二极管芯片接合在所述芯片安装区域之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管芯片的电极与焊垫进行电连接的引线接合工艺。
9.根据权利要求8所述的利用具有单一反射结构的印刷电路板的发光二极管封装制造方法,其特征在于:
通过如下方式形成所述坝(DAM)及光再吸收防止用坝:使用白墨水并多次反复进行印刷操作,或者利用分配器来排出坝形成用物质并对其进行硬化,或者对反射构造物进行层压。
10.一种利用具有单一反射结构的印刷电路板的发光二极管封装制造方法,其包括如下步骤:
在装载有发光二极管芯片的区域之间的所述金属圆板的表面使用白墨水并通过反复的印刷操作来形成光再吸收防止用坝;
在印刷电路板上形成配线图形,并且在印刷电路板表面上使用白墨水并通过反复的印刷操作来以芯片安装区域为中心在其周围的配线图形层上形成坝;
将形成有配线图形层及坝的印刷电路板层压于形成有所述光再吸收防止用坝的金属圆板上;
将发光二极管芯片接合于所述芯片安装区域之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管的电极与焊垫进行电连接的引线接合工艺。
11.一种利用具有单一反射结构的印刷电路板的发光二极管封装制造方法,其包括如下步骤:
在印刷电路板上形成配线图形层,并且在印刷电路板表面使用白墨水并通过反复的印刷操作来以芯片安装区域为中心在其周围的配线图形上形成坝;
将形成有配线图形层及坝的印刷电路板层压于金属圆板上;
在安装有发光二极管芯片的金属圆板表面利用分配器来排出坝形成用物质并对其进行硬化,从而形成光再吸收防止用坝;
将发光二极管芯片接合于所述芯片安装区域之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管芯片的电极与焊垫进行电连接的引线接合工艺。
12.一种利用具有单一反射结构的印刷电路板的发光二极管封装制造方法,其包括如下步骤:
在印刷电路板上形成配线图形层,并且将形成有配线图形层的印刷电路板层压于金属圆板上;
在安装有发光二极管芯片的金属圆板表面及印刷电路板上面利用分配器来排出坝形成用物质并对其进行硬化,从而以芯片安装区域为中心在其周围的配线图形上形成坝及在金属圆板表面形成光再吸收防止用坝;
将发光二极管芯片接合于所述芯片安装区域之间形成有光再吸收防止用坝的芯片安装区域,并且进行将发光二极管芯片的电极与焊垫进行电连接的引线接合工艺。
13.根据权利要求12所述的利用具有单一反射结构的印刷电路板的发光二极管封装制造方法,其特征在于:
在所述坝及在金属圆板表面形成光再吸收防止用坝的步骤中,在坝形成区域直接对反射构造物进行层压而形成。
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JP2016115710A (ja) * | 2014-12-11 | 2016-06-23 | シチズン電子株式会社 | Led照明装置 |
WO2017151730A1 (en) * | 2016-03-01 | 2017-09-08 | Exergy Dynamics, Inc. | Light emitting diode assemblies utilizing heat sharing from light-conditioning structures for enhanced energy efficiency |
DE102016205691A1 (de) * | 2016-04-06 | 2017-10-12 | Tridonic Jennersdorf Gmbh | LED-Modul in Chip-on-Board-Technologie |
KR20180055021A (ko) | 2016-11-15 | 2018-05-25 | 삼성디스플레이 주식회사 | 발광장치 및 그의 제조방법 |
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CN112614922A (zh) * | 2020-12-16 | 2021-04-06 | 松山湖材料实验室 | 具有反射杯结构的紫外集成光源及其制作方法 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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KR20100030389A (ko) * | 2008-09-10 | 2010-03-18 | 주식회사 코스모인 | 씨오엠(com) 형 발광다이오드 패키지, 이를 이용한 발광다이오드 모듈 및 그 제조방법 |
CN102148296A (zh) * | 2010-12-28 | 2011-08-10 | 广州市鸿利光电股份有限公司 | 一种led制作方法及led器件 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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KR20100030389A (ko) * | 2008-09-10 | 2010-03-18 | 주식회사 코스모인 | 씨오엠(com) 형 발광다이오드 패키지, 이를 이용한 발광다이오드 모듈 및 그 제조방법 |
CN102148296A (zh) * | 2010-12-28 | 2011-08-10 | 广州市鸿利光电股份有限公司 | 一种led制作方法及led器件 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110582848A (zh) * | 2017-05-02 | 2019-12-17 | 奥斯兰姆奥普托半导体有限责任公司 | 芯片模块的生产 |
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