CN102866318B - Test device for laminar packaging discrete device - Google Patents
Test device for laminar packaging discrete device Download PDFInfo
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- CN102866318B CN102866318B CN201210363300.7A CN201210363300A CN102866318B CN 102866318 B CN102866318 B CN 102866318B CN 201210363300 A CN201210363300 A CN 201210363300A CN 102866318 B CN102866318 B CN 102866318B
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Abstract
The invention discloses a test device for a laminar packaging discrete device, which comprises an electrode baseplate (1), a punching limiting plate (2) and a pressing plate (3), wherein the electrode baseplate (1) is positioned at the bottom layer, the punching limiting plate (2) is positioned on the upper surface of the electrode baseplate (1), and the pressing plate (3) is positioned on upper surface of the punching limiting plate (2). The test device has the characteristics of simple structure, strong generality, convenience in installation and the like. The test device reduces the cost of the test of a small scale of surface adhering components, enhances the test efficiency, reduces the test errors, and meanwhile accomplishes the detection on the number of to-be-detected devices. The test device solves the problem of test on a small scale of packaging discrete devices.
Description
Technical field
The present invention relates to discrete semiconductor testing field, particularly the batch-testing device of chip package discrete device.
Background technology
Discrete electronic devices and components many employings chip package form such as resistance, electric capacity, inductance of current use, be packaged into rectangle, there is pad at two ends.In order to ensure that the quality of discrete electronic devices and components just must carry out electric test to it, at present discrete device many employings automatic fraction collector of chip package and the mode of craft are tested.The test that but automatic fraction collector cost is high, volume large, complicated operation is not suitable for short run device.There is the problems such as efficiency is low, error is large in manual test, is not suitable for the test of short run device equally.
Summary of the invention
The technical problem to be solved in the present invention: a kind of chip package discrete semiconductor testing device is provided, solves a test difficult problem for short run chip package discrete device with lower cost, higher efficiency and lower test error.
Technical solution of the present invention:
A kind of chip package discrete semiconductor testing device, it comprises electrode plate, perforation limiting plate and pressing plate, and electrode plate is placed in bottom, and perforation limiting plate is positioned at electrode plate upper surface, and pressing plate is positioned at perforation limiting plate upper surface.
The spacing holding screw at spacing hole difference electrode insertion base plate four angles at perforation limiting plate and pressing plate four angles.
Electrode plate is furnished with positive electrode and negative electrode, on the right side of base plate, has spininess socket.
Perforation limiting plate has perforation, and the number of holes is greater than one, becomes matrix arrangement.
Pressing plate is two-layer structure, and upper strata is sheet metal, and lower floor is elastic caoutchouc.
Positive electrode on electrode plate and negative electrode composition electrode pair, the number of electrode pair is greater than 1, becomes matrix arrangement.
On electrode plate, each row positive electrode is connected on the first row contact pin of spininess socket, and on electrode plate, the negative electrode of every a line is connected on the second row contact pin of spininess socket.
Base plate lower floor elastic caoutchouc has protruding semisphere elastic caoutchouc particle, protruding semisphere elastic caoutchouc particle number is greater than one, becomes matrix arrangement,
The semisphere elastic caoutchouc particle one_to_one corresponding of the perforation of all one-tenth matrix arrangement, electrode and projection.
Beneficial effect of the present invention:
Chip package discrete semiconductor testing device disclosed by the invention is provided with the electrode of matrix arrangement, perforation and rubber bumps particle, and it is corresponding, measured device is by after spacing hole, neat falls on battery lead plate, then pressing plate is pressed, measured device is pushed down by the semisphere rubber grain of projection, make measured device pad and the complete reliable contacts of electrode, the object of perforation is to enable the pad of detected element insert in corresponding positive and negative electrode accurately, after detected element is inserted, the testing apparatus be connected with proving installation completes the test to measured device one by one by the mode scanned, realize the small-lot testing to chip package discrete device.Be not difficult to find out, compared to existing technology, the present invention has that structure is simple, highly versatile, the feature such as easy for installation, not only reduce the cost of Surface Mount components and parts small-lot testing, improve testing efficiency, decrease test error, complete the inspection of measured device quantity simultaneously, solve a difficult problem for short run chip package discrete semiconductor testing.
accompanying drawing illustrates:
Fig. 1 is the structural representation of proving installation of the present invention;
Fig. 2 is the diagrammatic cross-section of proving installation embodiment of the present invention;
Fig. 3 is the electrode plate schematic top plan view of proving installation embodiment of the present invention.
embodiment:
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in more detail.
Core concept of the present invention is: the electrode pair 9 of matrix arrangement, perforation 5 and the semisphere elastic caoutchouc particle 6 of projection are corresponding one by one, measured device 11 is by after perforation 5, neat falls on battery lead plate 1, measured device 11 is pushed down by the semisphere elastic caoutchouc particle 6 of projection, make pad and electrode pair 9 reliable contacts completely of measured device 11, the testing apparatus be connected with proving installation completes the test to measured device 11 one by one by the mode scanned, and realizes the small-lot testing to chip package discrete device.
As depicted in figs. 1 and 2, chip package discrete semiconductor testing device disclosed by the invention comprises electrode plate 1, perforation limiting plate 2, pressing plate 3, limited location holding screw 4 on electrode plate 1 four jiaos, perforation limiting plate 2 and pressing plate 3 four jiaos there is the spacing hole 7 with spacing holding screw 4 same diameter, perforation limiting plate 2 and pressing plate 3 pass spacing holding screw 4 by spacing hole 7, be stacked together with electrode plate 1, use the wing nut 10 on holding screw 4,3 blocks of plates are fixed together closely.Perforation limiting plate 2 perforation 5 by spacing for measured device 11 on electrode pair 9.Electrode pair 9, perforation 5 and semisphere elastic caoutchouc particle 6 position of projection are corresponding one by one, all adopt identical matrix arrangement mode.Socket 8 electrode plate 1 is equipped with, for realizing being electrically connected of electrode pair 9 and testing apparatus.Length breadth ratio measured device 11 length and width of perforation 5 are bigger, can ensure like this to fall into a measured device 11 in each perforation 5.The radius size of protruding semisphere elastic caoutchouc particle 6 and the wide identical of perforation 5, in order to ensure that measured device 11 can be pressed together on electrode plate 1 by pressing plate 3 closely.
As shown in Figure 3.Electrode pair 9 in the embodiment of the present invention on electrode plate 1 adopts the mode of 10 × 10 to arrange, and namely laterally with is longitudinally dispersed with 10 equidistant identical electrodes respectively to 9.Each electrode pair 9 is made up of a positive electrode 12 and a negative electrode 13.The positive electrode 12 of every file is connected by covering copper conductor, and 10 cover on the first row pin that copper conductor is connected to by the wire of electrode plate 1 bottom surface on socket 8.The negative electrode 13 often walked crosswise is connected with the copper conductor that covers on electrode plate 1 bottom surface by via hole, finally receives on the second row pin on socket 8.Such 100 electrode pairs are by these 20 ranks wires, and constitute a matrix, testing apparatus can complete the test of 100 components and parts by the mode of lining by line scan.The mode adopting this ranks alternately to connect, not only reduces the quantity connecting wire, also reduces the IO passage of testing apparatus, reduces testing cost.In the embodiment of the present invention, 0.5mm larger than the device length and width of 3216 packing forms, the spacing B between electrode 9 positive and negative electrode equal the distance between 0805 packaging two pad to the long A of electrode pair 9 and wide C respectively.Coordinate different perforation specification limiting plate 2 and pressing plate 3 can realize the test of the Surface Mount discrete device such as resistance, electric capacity, inductance from 3216 to 0805 all difference encapsulation, which reduces the replacing of electrode plate 1, reduce further testing cost, improve testing efficiency.
When implementing test, the electrode plate 1 that selection and measured device 11 size match, perforation limiting plate 2 and pressing plate 3, be sleeved on electrode plate 1 by perforation limiting plate 2 by the spacing hole 7 at 4 angles.Batch measured device 11 is placed on perforation limiting plate 2, then shakes whole device and guarantee to fall into a measured device 11 in each perforation 5, remove unnecessary device.Cover pressing plate 3, use the wing nut 10 on holding screw 4 to be fixed together closely by 3 blocks of plates, spininess socket connects testing apparatus on 8, the batch testing of measured device 11 can be completed by the sweep test of testing apparatus.
Claims (6)
1. a chip package discrete semiconductor testing device, it comprises electrode plate (1), perforation limiting plate (2) and pressing plate (3), electrode plate (1) is placed in bottom, perforation limiting plate (2) is positioned at electrode plate (1) upper surface, pressing plate (3) is positioned at perforation limiting plate (2) upper surface, it is characterized in that: pressing plate (3) is two-layer structure, upper strata is sheet metal, lower floor is elastic caoutchouc, pressing plate (3) lower floor elastic caoutchouc there is protruding semisphere elastic caoutchouc particle (6), protruding semisphere elastic caoutchouc particle (6) number is greater than one, become matrix arrangement.
2. a kind of chip package discrete semiconductor testing device according to claim 1, is characterized in that: the spacing holding screw (4) at spacing hole (7) difference electrode insertion base plate (1) four angle at perforation limiting plate (2) and pressing plate (3) four angles.
3. a kind of chip package discrete semiconductor testing device according to claim 1, is characterized in that: electrode plate (1) is furnished with positive electrode (12) and negative electrode (13), and there is spininess socket (8) on base plate (1) right side.
4. a kind of chip package discrete semiconductor testing device according to claim 1, is characterized in that: perforation limiting plate (2) has perforation (5), and perforation (5) quantity is greater than one, becomes matrix arrangement.
5. a kind of chip package discrete semiconductor testing device according to claim 3 is characterized in that: the positive electrode (12) on electrode plate (1) and negative electrode (13) composition electrode pair (9), and the number of electrode pair (9) is greater than 1, becomes matrix arrangement.
6. a kind of chip package discrete semiconductor testing device according to claim 3 is characterized in that: electrode plate (1) each row positive electrode (12) upper is connected on the first row contact pin of spininess socket (8), and the negative electrode (13) of the upper every a line of electrode plate (1) is connected on the second row contact pin of spininess socket (8).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210363300.7A CN102866318B (en) | 2012-09-26 | 2012-09-26 | Test device for laminar packaging discrete device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210363300.7A CN102866318B (en) | 2012-09-26 | 2012-09-26 | Test device for laminar packaging discrete device |
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| Publication Number | Publication Date |
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| CN102866318A CN102866318A (en) | 2013-01-09 |
| CN102866318B true CN102866318B (en) | 2015-07-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210363300.7A Active CN102866318B (en) | 2012-09-26 | 2012-09-26 | Test device for laminar packaging discrete device |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106556756B (en) * | 2016-10-20 | 2019-06-21 | 北方电子研究院安徽有限公司 | A kind of multidigit aging equipment of patch type capacitor and resistance |
| CN107907718A (en) * | 2017-12-18 | 2018-04-13 | 浙江杭可科技股份有限公司 | A kind of chip package semi-conductor discrete device fixture for testing |
| CN113049933A (en) * | 2019-12-27 | 2021-06-29 | 山东华光光电子股份有限公司 | Semiconductor laser aging clamp and aging method thereof |
Citations (5)
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|---|---|---|---|---|
| US6046598A (en) * | 1994-11-18 | 2000-04-04 | Fujitsu Limited | Test board and a test method using the same providing improved electrical connection |
| JP2000258495A (en) * | 1999-03-12 | 2000-09-22 | Oki Electric Ind Co Ltd | Semiconductor device testing device |
| CN2748923Y (en) * | 2004-11-30 | 2005-12-28 | 四川微迪数字技术有限公司 | Test tool set up for integrated circuit chip |
| CN2862043Y (en) * | 2005-11-15 | 2007-01-24 | 白锦添 | Step brazing type spheroid grid array movable testing seat |
| CN202794406U (en) * | 2012-09-26 | 2013-03-13 | 贵州航天计量测试技术研究所 | Chip encapsulation discrete device testing device |
-
2012
- 2012-09-26 CN CN201210363300.7A patent/CN102866318B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6046598A (en) * | 1994-11-18 | 2000-04-04 | Fujitsu Limited | Test board and a test method using the same providing improved electrical connection |
| JP2000258495A (en) * | 1999-03-12 | 2000-09-22 | Oki Electric Ind Co Ltd | Semiconductor device testing device |
| CN2748923Y (en) * | 2004-11-30 | 2005-12-28 | 四川微迪数字技术有限公司 | Test tool set up for integrated circuit chip |
| CN2862043Y (en) * | 2005-11-15 | 2007-01-24 | 白锦添 | Step brazing type spheroid grid array movable testing seat |
| CN202794406U (en) * | 2012-09-26 | 2013-03-13 | 贵州航天计量测试技术研究所 | Chip encapsulation discrete device testing device |
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| CN102866318A (en) | 2013-01-09 |
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