CN102842600A - Silicon-on-insulator silicon germanium heterojunction bipolar transistor (SOI SiGe HBT) planar integrated device and preparation method thereof - Google Patents

Silicon-on-insulator silicon germanium heterojunction bipolar transistor (SOI SiGe HBT) planar integrated device and preparation method thereof Download PDF

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CN102842600A
CN102842600A CN201210244397XA CN201210244397A CN102842600A CN 102842600 A CN102842600 A CN 102842600A CN 201210244397X A CN201210244397X A CN 201210244397XA CN 201210244397 A CN201210244397 A CN 201210244397A CN 102842600 A CN102842600 A CN 102842600A
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CN102842600B (en
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宋建军
胡辉勇
吕懿
张鹤鸣
宣荣喜
王斌
舒斌
郝跃
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Shaanxi Semiconductor Pioneer Technology Center Co ltd
Shaanxi Xi'an Electronic Large Assets Management Co ltd
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Xidian University
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Abstract

The invention discloses a silicon-on-insulator silicon germanium heterojunction bipolar transistor (SOI SiGe HBT0 planar integrated device and a preparation method thereof. The preparation method comprises following steps of continuously growing N-channel silicon (N-Si), P-channel silicon germanium (P-SiGe) and an N-channel silicon (N-Si) layer to deposit a dielectric layer to prepare shallow-trench isolation, photo-etching a collector region shallow-trench isolation area, preparing a collector region shallow-trench isolation, etching and depositing a dielectric layer, photo-etching a base-region shallow-trench isolation area, preparing a base-region shallow-trench isolation, photo-etching a collector region and injecting phosphorous ions to form a collector electrode contact region, photo-etching a base region and injecting boron ions to form a base electrode contact area, finally forming a SiGe HBT device, finally photo-etching a transmitting region lead hole, a base region lead holeand a collector region lead hole, metalizing, photo-etching leads, and forming an HBT integrated circuit with the thickness of the base region of 20 to 60nm. The technical method provided by the invention is compatible with the processing technique of the traditional CMOS integrated circuit, so that under the situation that the fund and the equipment investment are small, the SOI-based bipolar complementary metal-oxide semiconductor (BiCMOS) device and an integrated circuit are prepared, and the performance of the traditional analog and digital mixed integrated circuit is greatly improved.

Description

A kind of SOI SiGe HBT plane integrated device and preparation method
Technical field
The invention belongs to the semiconductor integrated circuit technical field, relate in particular to a kind of SOI SiGe HBT plane integrated device and preparation method.
Background technology
Integrated circuit is the foundation stone and the core of information-intensive society economic development.Mention when choosing in 20 engineering achievements the greatest in 20th century world the 5th electronic technology recently as U.S.'s engineering circle, " from the vacuum tube to the semiconductor, integrated circuit, become the foundation stone of contemporary every profession and trade intelligent work." best embody one of typical products of kownledge economy characteristic during integrated circuit.At present, be that basic electronics and information industry has become the big industry of the first in the world with the integrated circuit.Along with the development of integrated circuit technique, the clear and definite boundary between complete machine and the element is broken through, and integrated circuit not only becomes the basis of modern industry and science and technology, and is just creating the silicon culture of information age.
Because the good characteristic of Si material particularly can form exceedingly useful dielectric film---SiO easily 2Film and Si 3N 4Film, thus can utilize the Si material to realize the most cheap integrated circuit technology, developing so far, whole world number drops into technology with trillion dollars equipment, has made Si base technology form very powerful industry ability.Simultaneously, long-term scientific research drops into and also makes the understanding of people to Si and technology thereof, reaches very deep, thorough stage; Therefore in IC industry; The Si technology is a mainstream technology, and the Si IC products is a main product, accounts for more than 90% of IC industry.In the Si integrated circuit with bipolar transistor as the analog integrated circuit of basic structural unit in electronic system in occupation of consequence, along with the development of Si technology, the performance of Si bipolar transistor has also obtained significantly to improve.
But to the nineties in last century; The Si bipolar transistor is owing to the restriction of reasons such as voltage, base width, power density; The method of the scaled down that can not be more generally adopts by industrial quarters improves the performance of device and integrated circuit, has seriously restricted analog integrated circuit and with the further raising of its electronic system performance that is the basis.
In order further to improve the performance of device and integrated circuit, the researcher by novel semi-conducting material like GaAs, InP etc., to obtain to be suitable for the high speed device and the integrated circuit of wireless mobile communications development.Although GaAs and InP based compound device frequency excellent, its preparation technology is higher than Si complex process, cost, and the major diameter single crystal preparation is difficult, mechanical strength is low, and heat dispersion is bad, resembles SiO with Si difficult technique compatibility and shortage 2Such effects limit such as passivation layer its extensive use and development.
Summary of the invention
The object of the present invention is to provide a kind of SOI SiGe HBT plane integrated device to realize better device performance.
The object of the present invention is to provide a kind of SOI SiGe HBT plane integrated device, said integrated device adopts the non-polycrystalline of SOI, non-autoregistration bipolar transistor.
Further, said SiGe HBT device is prepared on the SOI substrate.
Further, the base of said SiGe HBT device is the strain SiGe material.
Further, said SiGe HBT device is a planar structure.
Neck one purpose of the present invention is to provide the preparation method of a kind of SOI SiGe HBT plane integrated device, it is characterized in that, comprises the steps:
The first step, to choose oxidated layer thickness be 150～400nm, and upper strata Si thickness is 100～150nm, and N type doping content is 1 * 10 16～1 * 10 17Cm -3The SOI substrate slice;
Second goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the N type Si epitaxial loayer of 50～100nm on substrate, and as collector region, this layer doping content is 1 * 10 16～1 * 10 17Cm -3
The 3rd goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the SiGe layer of 20～60nm on substrate, and as the base, this layer Ge component is 15～25%, and doping content is 5 * 10 18～5 * 10 19Cm -3
The 4th goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the N type Si layer of 100～200nm on substrate, and as the emitter region, this layer doping content is 1 * 10 17～5 * 10 17Cm -3
The 5th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200～300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100～200nm; Shallow trench isolation areas between lithographic device goes out the shallow slot that the degree of depth is 650～1100nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 6th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 200～300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100～200nm; Photoetching collector region shallow trench isolation areas goes out the shallow slot that the degree of depth is 180～300nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 7th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 200～300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100～200nm; Photoetching base shallow trench isolation areas goes out the shallow slot that the degree of depth is 105～205nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 8th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 300～500nm at substrate surface deposit one layer thickness 2Layer; The photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form collector contact area;
The 9th step, photoetching base region carry out p type impurity to this zone and inject, and making base stage contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form the base stage contact area, and to substrate under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation;
The tenth goes on foot, falls with wet etching the SiO on surface 2, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 300～500nm at substrate surface deposit one layer thickness 2Layer; Photoetching emitter, base stage and collector terminal hole form SiGe HBT device;
The 11 step, at substrate surface splash-proofing sputtering metal titanium (Ti), alloy forms silicide;
The 12 step, splash-proofing sputtering metal, the photoetching lead-in wire forms emitter, base stage and collector electrode metal lead-in wire, and constituting base thickness is 20～60nm, and collector region thickness is the SOI SiGe HBT integrated circuit of 150～250nm.
Further, base thickness confirms according to the thickness of the 3rd one-step growth SiGe, gets 20～60nm.
Further, collector region thickness decides according to the thickness of the Si epitaxial loayer of the first step SOI upper strata Si thickness and second one-step growth, gets 150～250nm.
Further, maximum temperature related among this preparation method is according to chemical vapor deposition (CVD) the technological temperature decision in second step, the 3rd step, the 4th step, the 5th step, the 6th step, the 7th step, the 8th step and the tenth step, maximum temperature is smaller or equal to 800 ℃.
Another object of the present invention is to provide a kind of preparation method of SOI SiGe HBT planar integrated circuit, comprise the steps:
Step 1, the implementation method of epitaxial material preparation is:
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO 2, thickness is 150nm, upper layer of material is that doping content is 1 * 10 16Cm -3N type Si, thickness is 100nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type epitaxy Si layer of 50nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 16Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe layer of 20nm on substrate, and as the base, this layer Ge component is 15%, and doping content is 5 * 10 18Cm -3
(1d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type Si layer of 100nm on substrate, and as the emitter region, this layer doping content is 1 * 10 17Cm -3
Step 2, the implementation method of device shallow-trench isolation preparation is:
(2a) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(2b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(2c) shallow trench isolation areas between the lithographic device goes out the shallow slot that the degree of depth is 650nm at the shallow trench isolation areas dry etching;
(2d) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the device shallow-trench isolation;
Step 3, the implementation method of collector electrode shallow-trench isolation preparation is:
(3a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(3c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 180nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the collector electrode shallow-trench isolation;
Step 4, the implementation method of base stage shallow-trench isolation preparation is:
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 105nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the base stage shallow-trench isolation;
Step 5, the implementation method of collector electrode and base stage preparation is:
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(5c) photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 1 * 10 19Cm -3, form collector electrode;
(5d) photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 1 * 10 19Cm -3, form base stage;
(5e) to substrate under 950 ℃ of temperature, annealing 120s, carry out impurity activation;
Step 6, the implementation method of lead-in wire preparation is:
(6a) fall surperficial SiO with wet etching 2Layer;
(6b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(6c) photoetching emitter, base stage and collector terminal hole form SiGe HBT device;
(6d) at substrate surface splash-proofing sputtering metal titanium (Ti), alloy forms silicide;
(6e) splash-proofing sputtering metal, the photoetching lead-in wire forms emitter, base stage and collector electrode metal lead-in wire, and constituting base thickness is 20nm, and collector region thickness is the SOI SiGe HBT integrated circuit of 150nm.
The present invention has following advantage:
1. the collector region thickness of the SOI SiGe HBT integrated device of the present invention's preparation is thin than traditional devices; Therefore; There is collector region effect extending transversely in this device, and can form two dimensional electric field at collector region, thereby has improved the reverse breakdown voltage and the Early voltage of this device; Under identical breakdown characteristics, have the characteristic frequency more excellent than traditional devices;
2. the SOI SiGe HBT integrated device of the present invention's preparation in the preparation process, adopts non-self-registered technology, is effectively keeping greatly reducing technology difficulty on the basis of device performance;
3. because process proposed by the invention and existing CMOS integrated circuit processing technology are compatible; And can be applicable in the middle of BiCMOS device and the integrated circuit manufacturing; Therefore, can under the very little situation of fund and equipment input, significantly improve the performance of integrated circuit;
4. to prepare the maximum temperature that relates in the SOI three polycrystal SiGe HBT integrated device processes be 800 ℃ in the present invention; Be lower than the technological temperature that causes the strain SiGe relaxation; Therefore this preparation method can keep the characteristic of strain SiGe effectively, improves the performance of device and integrated circuit.
Description of drawings
Fig. 1 is a process chart of realizing SOI SiGe HBT integrated device of the present invention and circuit preparation.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention provides a kind of SOI SiGe HBT plane integrated device, and said integrated device adopts the non-polycrystalline of SOI, non-autoregistration SiGe HBT.
As a prioritization scheme of the embodiment of the invention, said integrated device is prepared on the SOI substrate.
As a prioritization scheme of the embodiment of the invention, the base of said integrated device is the strain SiGe material.
As a prioritization scheme of the embodiment of the invention, said integrated device is a planar structure.
Following with reference to accompanying drawing 1, the technological process of SOI SiGe HBT integrated device of the present invention and circuit is described in further detail.
Embodiment 1: preparation base thickness is SOI SiGe HBT plane integrated device and the circuit methods of 20nm, and concrete steps are following:
Step 1, the epitaxial material preparation.
(1a) choose the SOI substrate slice, this substrate lower layer support material 1 is Si, and intermediate layer 2 is SiO 2, thickness is 150nm, upper layer of material 3 is 1 * 10 for doping content 16Cm -3N type Si, thickness is 100nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type epitaxy Si layer of 50nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 16Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe layer of 20nm on substrate, and as the base, this layer Ge component is 15%, and doping content is 5 * 10 18Cm -3
(1d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type Si layer 6 of 100nm on substrate, and as the emitter region, this layer doping content is 1 * 10 17Cm -3
Step 2, the preparation of device shallow-trench isolation.
(2a) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer 7;
(2b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer 8 of 100nm at substrate surface deposit one layer thickness;
(2c) shallow trench isolation areas between the lithographic device goes out the shallow slot that the degree of depth is 650nm at the shallow trench isolation areas dry etching;
(2d) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form device shallow-trench isolation 9.
Step 3, the preparation of collector electrode shallow-trench isolation.
(3a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer 10;
(3c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer 11 of 100nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot 12 that the degree of depth is 180nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form collector electrode shallow-trench isolation 12.
Step 4, the preparation of base stage shallow-trench isolation.
(4a) fall surperficial SiO with wet etching 2With the SiN layer,
(4b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer 13;
(4c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer 14 of 100nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 105nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form base stage shallow-trench isolation 15.
Step 5, collector electrode and base stage preparation.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer 16;
(5c) photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 1 * 10 19Cm -3, form collector electrode 17;
(5d) photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 1 * 10 19Cm -3, form base stage 18;
(5e) to substrate under 950 ℃ of temperature, annealing 120s, carry out impurity activation.
Step 6, the lead-in wire preparation.
(6a) fall surperficial SiO with wet etching 2Layer;
(6b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer 19;
(6c) photoetching emitter, base stage and collector terminal hole form SiGe HBT device 20;
(6d) at substrate surface splash-proofing sputtering metal titanium (Ti), alloy forms silicide;
(6e) splash-proofing sputtering metal, the photoetching lead-in wire forms emitter 21, base stage 22 and collector electrode 23 metal lead wires, and constituting base thickness is 20nm, and collector region thickness is the SOI SiGe HBT integrated circuit of 150nm.
Embodiment 2: preparation base thickness is SOI SiGe HBT plane integrated device and the circuit methods of 40nm, and concrete steps are following:
Step 1, the epitaxial material preparation.
(1a) choose the SOI substrate slice, this substrate lower layer support material 1 is Si, and intermediate layer 2 is SiO 2, thickness is 300nm, upper layer of material 3 is 5 * 10 for doping content 16Cm -3N type Si, thickness is 120nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the N type epitaxy Si layer 4 of 80nm on the Si material of upper strata, and as collector region, this layer doping content is 5 * 10 16Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the SiGe layer 5 of 40nm on substrate, and as the base, this layer Ge component is 20%, and doping content is 1 * 10 19Cm -3
(1d) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the N type Si layer 6 of 150nm on substrate, and as the emitter region, this layer doping content is 3 * 10 17Cm -3
Step 2, the preparation of device shallow-trench isolation.
(2a) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer 7;
(2b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer 8 of 150nm at substrate surface deposit one layer thickness;
(2c) shallow trench isolation areas between the lithographic device goes out the shallow slot that the degree of depth is 900nm at the shallow trench isolation areas dry etching;
(2d) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2, form device shallow-trench isolation 9.
Step 3, the preparation of collector electrode shallow-trench isolation.
(3a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer 10;
(3c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer 11 of 150nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot 12 that the degree of depth is 240nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2, form collector electrode shallow-trench isolation 12.
Step 4, the preparation of base stage shallow-trench isolation.
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer 13;
(4c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer 14 of 150nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 155nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2, form base stage shallow-trench isolation 15.
Step 5, collector electrode and base stage preparation.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 400nm at substrate surface deposit one layer thickness 2Layer 16;
(5c) photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 5 * 10 19Cm -3, form collector electrode 17;
(5d) photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 5 * 10 19Cm -3, form base stage 18;
(5e) to substrate under 1000 ℃ of temperature, annealing 60s, carry out impurity activation.
Step 6, the lead-in wire preparation.
(6a) fall surperficial SiO with wet etching 2Layer;
(6b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 400nm at substrate surface deposit one layer thickness 2Layer 19;
(6c) photoetching emitter, base stage and collector terminal hole form SiGe HBT device 20;
(6d) at substrate surface splash-proofing sputtering metal titanium (Ti), alloy forms silicide;
(6e) splash-proofing sputtering metal, the photoetching lead-in wire forms emitter 21, base stage 22 and collector electrode 23 metal lead wires, and constituting base thickness is 40nm, and collector region thickness is the SOI SiGe HBT integrated circuit of 200nm.
Embodiment 3: preparation base thickness is SOI SiGe HBT plane integrated device and the circuit methods of 60nm, and concrete steps are following:
Step 1, the epitaxial material preparation.
(1a) choose the SOI substrate slice, this substrate lower layer support material 1 is Si, and intermediate layer 2 is SiO 2, thickness is 400nm, upper layer of material 3 is 1 * 10 for doping content 17Cm -3N type Si, thickness is 150nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the N type epitaxy Si layer 4 of 100nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 17Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the SiGe layer 5 of 60nm on substrate, and as the base, this layer Ge component is 25%, and doping content is 5 * 10 19Cm -3
(1d) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the N type Si layer 6 of 200nm on substrate, and as the emitter region, this layer doping content is 5 * 10 17Cm -3
Step 2, the preparation of device shallow-trench isolation.
(2a) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer 7;
(2b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer 8 of 200nm at substrate surface deposit one layer thickness;
(2c) shallow trench isolation areas between the lithographic device goes out the shallow slot that the degree of depth is 1100nm at the shallow trench isolation areas dry etching;
(2d) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form device shallow-trench isolation 9.
Step 3, the preparation of collector electrode shallow-trench isolation.
(3a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer 10;
(3c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer 11 of 200nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot 12 that the degree of depth is 300nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form collector electrode shallow-trench isolation 12.
Step 4, the preparation of base stage shallow-trench isolation.
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer 13;
(4c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer 14 of 200nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 205nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form base stage shallow-trench isolation 15.
Step 5, collector electrode and base stage preparation.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 500nm at substrate surface deposit one layer thickness 2Layer 16;
(5c) photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 1 * 10 20Cm -3, form collector electrode 17;
(5d) photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 1 * 10 20Cm -3, form base stage 18;
(5e) to substrate under 1100 ℃ of temperature, annealing 15s, carry out impurity activation.
Step 6, the lead-in wire preparation.
(6a) fall surperficial SiO with wet etching 2Layer;
(6b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 500nm at substrate surface deposit one layer thickness 2Layer 19;
(6c) photoetching emitter, base stage and collector terminal hole form SiGe HBT device 20;
(6d) at substrate surface splash-proofing sputtering metal titanium (Ti), alloy forms silicide;
(6e) splash-proofing sputtering metal, the photoetching lead-in wire forms emitter 21, base stage 22 and collector electrode 23 metal lead wires, and constituting base thickness is 60nm, and collector region thickness is the SOI SiGe HBT integrated circuit of 250nm.
SOI SiGe HBT integrated device and preparation method that the embodiment of the invention provides have following advantage:
1. the collector region thickness of the SOI SiGe HBT integrated device of the present invention's preparation is thin than traditional devices; Therefore; There is collector region effect extending transversely in this device, and can form two dimensional electric field at collector region, thereby has improved the reverse breakdown voltage and the Early voltage of this device; Under identical breakdown characteristics, have the characteristic frequency more excellent than traditional devices;
2. the SOI SiGe HBT integrated device of the present invention's preparation in the preparation process, adopts non-self-registered technology, is effectively keeping greatly reducing technology difficulty on the basis of device performance;
3. because process proposed by the invention and existing CMOS integrated circuit processing technology are compatible; And can be applicable in the middle of BiCMOS device and the integrated circuit manufacturing; Therefore, can under the very little situation of fund and equipment input, significantly improve the performance of integrated circuit;
4. to prepare the maximum temperature that relates in the SOI three polycrystal SiGe HBT integrated device processes be 800 ℃ in the present invention; Be lower than the technological temperature that causes the strain SiGe relaxation; Therefore this preparation method can keep the characteristic of strain SiGe effectively, improves the performance of device and integrated circuit.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims (9)

1. a SOI SiGe HBT plane integrated device is characterized in that, said integrated device adopts non-polycrystalline SOI SiGe HBT.
2. SOI SiGe HBT integrated device according to claim 1 is characterized in that said integrated device is prepared on the SOI substrate.
3. SOI SiGe HBT integrated device according to claim 1 is characterized in that the base of said integrated device is the strain SiGe material.
4. SOI SiGe HBT integrated device according to claim 1 is characterized in that, it is a planar structure also.
5. the preparation method of a SOI SiGe HBT plane integrated device is characterized in that, comprises the steps:
The first step, to choose oxidated layer thickness be 150～400nm, and upper strata Si thickness is 100～150nm, and N type doping content is 1 * 10 16～1 * 10 17Cm -3The SOI substrate slice;
Second goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the N type Si epitaxial loayer of 50～100nm on substrate, and as collector region, this layer doping content is 1 * 10 16～1 * 10 17Cm -3
The 3rd goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the SiGe layer of 20～60nm on substrate, and as the base, this layer Ge component is 15～25%, and doping content is 5 * 10 18～5 * 10 19Cm -3
The 4th goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the N type Si layer of 100～200nm on substrate, and as the emitter region, this layer doping content is 1 * 10 17～5 * 10 17Cm -3
The 5th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200～300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100～200nm; Shallow trench isolation areas between lithographic device goes out the shallow slot that the degree of depth is 650～1100nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 6th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 200～300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100～200nm; Photoetching collector region shallow trench isolation areas goes out the shallow slot that the degree of depth is 180～300nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 7th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 200～300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100～200nm; Photoetching base shallow trench isolation areas goes out the shallow slot that the degree of depth is 105～205nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 8th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 300～500nm at substrate surface deposit one layer thickness 2Layer; The photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form collector contact area;
The 9th step, photoetching base region carry out p type impurity to this zone and inject, and making base stage contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form the base stage contact area, and to substrate under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation;
The tenth goes on foot, falls with wet etching the SiO on surface 2, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 300～500nm at substrate surface deposit one layer thickness 2Layer; Photoetching emitter, base stage and collector terminal hole form SiGe HBT device;
The 11 step, at substrate surface splash-proofing sputtering metal titanium (Ti), alloy forms silicide;
The 12 step, splash-proofing sputtering metal, the photoetching lead-in wire forms emitter, base stage and collector electrode metal lead-in wire, and constituting base thickness is 20～60nm, and collector region thickness is the SOI SiGe HBT integrated circuit of 150～250nm.
6. preparation method according to claim 5 is characterized in that base thickness is confirmed according to the thickness of the 3rd one-step growth SiGe, got 20～60nm.
7. preparation method according to claim 5 is characterized in that, collector region thickness decides according to the thickness of the Si epitaxial loayer of the first step SOI upper strata Si thickness and second one-step growth, gets 150～250nm.
8. preparation method according to claim 5; It is characterized in that; Maximum temperature related among this preparation method is according to chemical vapor deposition (CVD) the technological temperature decision in second step, the 3rd step, the 4th step, the 5th step, the 6th step, the 7th step, the 8th step and the tenth step, and maximum temperature is smaller or equal to 800 ℃.
9. the preparation method of a SOI SiGe HBT planar integrated circuit is characterized in that, comprises the steps:
Step 1, the implementation method of epitaxial material preparation is:
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO 2, thickness is 150nm, upper layer of material is that doping content is 1 * 10 16Cm -3N type Si, thickness is 100nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type epitaxy Si layer of 50nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 16Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe layer of 20nm on substrate, and as the base, this layer Ge component is 15%, and doping content is 5 * 10 18Cm -3
(1d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type Si layer of 100nm on substrate, and as the emitter region, this layer doping content is 1 * 10 17Cm -3
Step 2, the implementation method of device shallow-trench isolation preparation is:
(2a) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(2b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(2c) shallow trench isolation areas between the lithographic device goes out the shallow slot that the degree of depth is 650nm at the shallow trench isolation areas dry etching;
(2d) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the device shallow-trench isolation;
Step 3, the implementation method of collector electrode shallow-trench isolation preparation is:
(3a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(3c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 180nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the collector electrode shallow-trench isolation;
Step 4, the implementation method of base stage shallow-trench isolation preparation is:
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 105nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the base stage shallow-trench isolation;
Step 5, the implementation method of collector electrode and base stage preparation is:
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(5c) photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 1 * 10 19Cm -3, form collector electrode;
(5d) photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 1 * 10 19Cm -3, form base stage;
(5e) to substrate under 950 ℃ of temperature, annealing 120s, carry out impurity activation;
Step 6, the implementation method of lead-in wire preparation is:
(6a) fall surperficial SiO with wet etching 2Layer;
(6b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(6c) photoetching emitter, base stage and collector terminal hole form SiGe HBT device;
(6d) at substrate surface splash-proofing sputtering metal titanium (Ti), alloy forms silicide;
(6e) splash-proofing sputtering metal, the photoetching lead-in wire forms emitter, base stage and collector electrode metal lead-in wire, and constituting base thickness is 20nm, and collector region thickness is the SOI SiGe HBT integrated circuit of 150nm.
CN201210244397.XA 2012-07-16 2012-07-16 Silicon-on-insulator silicon germanium heterojunction bipolar transistor (SOI SiGe HBT) planar integrated device and preparation method thereof Active CN102842600B (en)

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K.BRUNNER,H.DOBLER,G.ABSTREITER: "Molecular beam epitaxy growth and thermal stability of Si1-xGex layers on extremely thin silicon-on-insulator substrates", 《THIN SOLID FILMS》 *
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钱伟，张进书，贾宏勇，林惠旺，钱佩信: "微波低噪声SiGe HBT的研制", 《半导体学报》 *

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