CN108110052A - Ge-Si heterojunction bipolar transistor and manufacturing method - Google Patents
Ge-Si heterojunction bipolar transistor and manufacturing method Download PDFInfo
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- CN108110052A CN108110052A CN201810087224.9A CN201810087224A CN108110052A CN 108110052 A CN108110052 A CN 108110052A CN 201810087224 A CN201810087224 A CN 201810087224A CN 108110052 A CN108110052 A CN 108110052A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 229
- 229920005591 polysilicon Polymers 0.000 claims abstract description 219
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 99
- 238000000034 method Methods 0.000 claims abstract description 50
- 230000012010 growth Effects 0.000 claims abstract description 39
- 230000008569 process Effects 0.000 claims abstract description 21
- 239000000203 mixture Substances 0.000 claims abstract description 18
- 238000000227 grinding Methods 0.000 claims abstract description 15
- 238000001039 wet etching Methods 0.000 claims abstract description 11
- 239000000126 substance Substances 0.000 claims abstract description 9
- 238000011049 filling Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 334
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 42
- 229910052710 silicon Inorganic materials 0.000 claims description 42
- 239000010703 silicon Substances 0.000 claims description 42
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 32
- 150000002500 ions Chemical class 0.000 claims description 26
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 22
- 229910052760 oxygen Inorganic materials 0.000 claims description 22
- 239000001301 oxygen Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 229910052732 germanium Inorganic materials 0.000 claims description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 12
- 238000011065 in-situ storage Methods 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000004151 rapid thermal annealing Methods 0.000 claims description 5
- 229910003978 SiClx Inorganic materials 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims 1
- 230000010355 oscillation Effects 0.000 abstract description 11
- 230000006872 improvement Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000009647 facial growth Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000032696 parturition Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910021483 silicon-carbon alloy Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
- H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
Abstract
The invention discloses a kind of Ge-Si heterojunction bipolar transistors, the base window definition that base region is formed after the base Windows media layer chemical wet etching by including the first polysilicon layer, the p-type germanium silicon epitaxial layer of composition base is formed using comprehensive non-selective epitaxial growth technique, by p-type germanium silicon epitaxial layer positioned at the polycrystalline structure of base window side and the first polysilicon layer contact composition outer base area polysilicon；The first side wall autoregistration that emitter window is formed at base window side by autoregistration defines, launch site polysilicon by the second polysilicon of filling and using the second dielectric layer at the top of base Windows media layer for stop layer progress polysilicon grinding after formed.The invention also discloses a kind of manufacturing methods of Ge-Si heterojunction bipolar transistor.The process costs that the present invention can reduce p-type germanium silicon epitaxial layer are lower, can reduce base resistance and be conducive to the diminution of the lateral dimension of entire device, can improve the maximum frequency of oscillation of device.
Description
Technical field
It is brilliant more particularly to a kind of germanium silicon (SiGe) heterogenous dual-pole the present invention relates to semiconductor integrated circuit manufacturing field
Body pipe (HBT)；The invention further relates to a kind of manufacturing methods of Ge-Si heterojunction bipolar transistor.
Background technology
The radio frequency applications requirement of hyperfrequency improves the characteristic frequency (f of Ge-Si heterojunction bipolar transistor (SiGe HBT)t)
With maximum frequency of oscillation (fmax).Characteristic frequency is also referred to as cutoff frequency, is frequency when current gain is 1；Maximum frequency of oscillation
Frequency when for power gain being 1.Reduce base resistance (RB) and base-collecting zone capacitance (CBC) f can be reducedmax。
In existing SiGe HBT, by taking NPN pipes as an example, generally use p-type polysilicon raises outer base area, emitter and outer base area
Between use inside wall autoregistration device architecture, can so reduce base resistance i.e. R simultaneouslyBIt is with base-collector capacitance
CBC, such germanium-silicon heterojunction bipolar triode device can obtain the f more than 300GHzmax, performance can and III-V
Device is suitable, is widely used in optic communication and Millimeter Wave Applications.
SiGe HBT devices use the germanium silicon-carbon alloy mixed with boron impurities of smaller bandwidth as base stage, due to emitter
There is band difference with base stage, it can be when ensureing same DC current amplification factor using higher base doping, so as to obtain
Higher fmax。
Base resistance RBIncluding external base resistance and intrinsic base region resistance, RBIt is to promote fmaxImportant parameter, to reduce
Base resistance will improve the doping concentration of base and reduce the width of emitter-window and side wall as far as possible.
Autoregistration SiGe HBT manufacture crafts can obtain very high characteristic frequency and maximum frequency of oscillation, but manufacture craft
Complexity is now described as follows the existing manufacture craft there are two types of main autoregistration SiGe HBT：
As shown in Figure 1A to Fig. 1 C, be the first existing Ge-Si heterojunction bipolar transistor each step of manufacturing method in
Device architecture schematic diagram；Existing first method needs to grow using selective germanium and silicon epitaxial, by taking NPN pipes as an example, specific steps
For：
As shown in Figure 1A, a silicon substrate 1 is provided, is also formed with p type buried layer 2 in Figure 1A in silicon substrate 1, forms shallow trench, N
The counterfeit buried regions 4 of type, filling oxide layer forms shallow trench field oxygen 5 in shallow trench, and shallow trench field oxygen 5 isolates active area, active
The collecting zone 3 of n-type doping is formed in area.
The first silicon oxide layer 6, p-type polysilicon layer 7, the second silicon oxide layer 8, the 3rd silicon nitride layer 9 and the 4th are formed afterwards
Silicon oxide layer；Photoetching is carried out afterwards and opens emitter window region, to the 4th silicon oxide layer in emitter window region, the 3rd nitrogen
SiClx layer 9, the second silicon oxide layer 8, p-type polysilicon layer 7 perform etching to form emitter window, and etching stopping is in the first silica
On layer 6.
Wet etching and the cleaning of silica are carried out afterwards, and the 4th silicon oxide layer is gone after the completion of the wet etching of silica
It removes, the first silicon oxide layer 6 is by lateral etching a distance, so that the silicon face in region shown in dotted line circle 10 in Figure 1A be exposed.
Afterwards, as shown in Figure 1B, making choice property germanium and silicon epitaxial is grown, and selective germanium and silicon epitaxial growth is only given birth in silicon face
It is long, it is not grown in non-silicon surface, p-type germanium silicon epitaxial layer 11 can be so formed in the region shown in dotted line circle 10.
Afterwards, as shown in Figure 1B, inside wall is formed in the side of emitter window, inside wall is by silicon oxide layer 12, nitridation
Silicon layer 13 and silicon oxide layer 14 carry out etching comprehensively and are formed after depositing.
Afterwards, as shown in Figure 1B, carry out polycrystalline silicon deposit and chemical wet etching forms launch site polysilicon 15；To p-type polycrystalline
Silicon layer 7 carries out chemical wet etching and forms outer base area polysilicon 7；P-type germanium silicon epitaxial layer 11 is used as base, outer base area polysilicon 7 and p-type
Germanium silicon epitaxial layer 11, which is connected, to be realized the extraction of base.
As shown in Fig. 2A to Fig. 2 C, be the first existing Ge-Si heterojunction bipolar transistor each step of manufacturing method in
Device architecture schematic diagram；Existing first method needs to grow using selective germanium and silicon epitaxial, by taking NPN pipes as an example, specific steps
For：
As shown in Figure 2 A, a silicon substrate 201 is provided, is also formed with p type buried layer 202 in Fig. 2A in silicon substrate 201, is formed shallow
Groove, the counterfeit buried regions 204 of N-type, filling oxide layer forms shallow trench field oxygen 205 in shallow trench, and shallow trench field oxygen 205 has isolated
Source region forms the collecting zone 203 of n-type doping in active area.
P-type germanium silicon epitaxial layer 206 is formed using comprehensive non-selective germanium and silicon epitaxial growth technique afterwards.
The first silicon oxide layer 207, the second silicon nitride layer 208 and the 3rd silicon oxide layer 209 are formed afterwards；Photoetching is carried out afterwards
Emitter window region is opened, to the 3rd silicon oxide layer 209 in emitter window region, the second silicon nitride layer 208 performs etching
Emitter window is formed, etching stopping is on the first silicon oxide layer 207.
Afterwards, inside wall 210 is formed in the side of emitter window, inside wall 210 carries out complete after being deposited by silicon oxide layer
Face etches to be formed.
Afterwards, as shown in Figure 2 B, the lamination of depositing polysilicon and silica 212, polysilicon 211 are N-type heavy doping；It carries out
Chemical wet etching forms launch site polysilicon 211.
Afterwards, side wall 213 is formed in the side of launch site polysilicon 211, side wall 213 carries out complete after being deposited by silicon oxide layer
Face etches to be formed.
Afterwards, as shown in Figure 2 C, the second silicon nitride layer 208 outside 211 region of launch site polysilicon, i.e. inside wall are removed
210 and side wall 213 outside the second silicon nitride layer 208；Removal, the first silicon oxide layer 207 of 208 bottom of the second silicon nitride layer,
The surface of p-type germanium silicon epitaxial layer 206 is exposed.
Afterwards, as shown in Figure 2 C, make choice the high boron-doping silicon epitaxy technique of type formed polysilicon and to the polysilicon into
Row chemical wet etching forms outer base area polysilicon 214.Silicon oxide layer 215 is formed at outside the region of outer base area polysilicon 214.
Afterwards, chemical wet etching is carried out to p-type germanium silicon epitaxial layer 206 and forms base, the base passes through outer base area polysilicon
214 draw.
Existing first method is fairly simple, but needs to do selective germanium and silicon epitaxial, that is, needs outside by selective germanium silicon
Epitaxial growth forms p-type germanium silicon epitaxial layer 11, in the case where lateral device dimensions gradually reduce, to obtain flawless p-type germanium
Silicon epitaxy layer 11 has challenge.
And existing second method uses the non-selective epitaxy technique growing P-type germanium silicon epitaxial layer 206 of germanium silicon, but most
Afterwards will be in the region beyond the side wall 210 and 213 of launch site polysilicon (EP) 211, selective grows highly doped polysilicon,
And difficult.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of Ge-Si heterojunction bipolar transistor, can improve device most
High oscillation frequency, while reduce technology difficulty.For this purpose, the present invention also provides a kind of manufacture of Ge-Si heterojunction bipolar transistor
Method.
In order to solve the above technical problems, Ge-Si heterojunction bipolar transistor provided by the invention is formed on silicon substrate, have
Source region is isolated by shallow trench field oxygen, and the Ge-Si heterojunction bipolar transistor includes：
Collecting zone, the first conductive type ion injection region composition being formed from the active area.
Counterfeit buried regions is formed from the first conduction type heavy doping ion of the shallow trench field oxygen bottom of the active area both sides
Injection region forms, the counterfeit buried regions and the collecting zone laterally contact contact；It is formed through at the top of the counterfeit buried regions described
The collecting zone is connected to the current collection being made of front metal layer by the deep hole contact of shallow trench field oxygen by the deep hole contact
Pole.
Base window, by being formed after base Windows media layer chemical wet etching, the base Windows media layer is included using complete
The superimposed layer of first medium layer, the first polysilicon layer and second dielectric layer that face growth technique is formed；The base window is located at
The width of the surface of the active area and the base window is less than or equal to the width of the active area and by the collecting zone
Surface be exposed.
P-type germanium silicon epitaxial layer, the p-type germanium silicon epitaxial layer are formed using comprehensive non-selective epitaxial growth technique, institute
It states p-type germanium silicon epitaxial layer and mono-crystalline structures and polycrystalline structure is divided by the base window autoregistration, positioned at the base window
The p-type germanium silicon epitaxial layer of the part on the surface of the interior active area is mono-crystalline structures；Positioned at the side of the base window
The part of the base Windows media layer surface outside face and the base window is polycrystalline structure.
Emitter window, is defined by the first side wall autoregistration, and the first side wall autoregistration is formed at the base window
Mouthful side the p-type germanium silicon epitaxial layer polycrystalline structure side, the emitter window is by the p-type germanium silicon of bottom
The surface of the mono-crystalline structures of epitaxial layer is exposed.
The second polysilicon layer formed using comprehensive polycrystalline silicon growth process, second polysilicon layer is by the launch site
Window is filled up completely and extends to the polycrystalline structure surface of the p-type germanium silicon epitaxial layer outside the emitter window；Described
Second medium layer as polysilicon grinding stop layer and define the height of launch site polysilicon, in the longitudinal direction positioned at described second
The polycrystalline structure of second polysilicon layer and the p-type germanium silicon epitaxial layer at the top of dielectric layer is all removed.
By residue the launch site polysilicon is formed in second polysilicon layer in the emitter window；The base
The polycrystalline structure of the p-type germanium silicon epitaxial layer of area's window side and first polysilicon layer are in contact and to form outer base area more
Crystal silicon；Isolated between the launch site polysilicon and the outer base area polysilicon by first side wall.
The launch site polysilicon is the first conduction type heavy doping, and the outer base area polysilicon is the second conduction type weight
Doping.
Launch site is formed from the of the mono-crystalline structures surface of the p-type germanium silicon epitaxial layer of the emitter window bottom
One conduction type doped region forms.
Intrinsic base region is formed from the mono-crystalline structures composition of the p-type germanium silicon epitaxial layer of the launch site bottom.
The mono-crystalline structures of the p-type germanium silicon epitaxial layer between the outer base area polysilicon and the intrinsic base region are overlapping
Outer base area, the width of the overlapping outer base area by the width adjusting of first side wall and with self-alignment structure described the
One side wall reduces the width of the overlapping outer base area, so as to reduce base resistance.
A further improvement is that the doping of the launch site polysilicon passes through after the completion of second polysilicon layer growth
It injects to be formed using comprehensive first conduction type heavy doping ion；Alternatively, the doping of the launch site polysilicon passes through in institute
State doping realization in situ in the second polysilicon layer growth course.
It is moved back a further improvement is that the doping of the launch site does fast speed heat by the impurity to the launch site polysilicon
Fire diffuses to form.
A further improvement is that the second dielectric layer is after the completion of the corresponding polysilicon grinding of the launch site polysilicon
It is removed, the doping of the outer base area polysilicon after the second dielectric layer is removed by carrying out the second conduction type weight
Doped ions inject to be formed, and launch site is more described in the second conduction type heavy doping ion injection of the outer base area polysilicon
It is protected by photoresist at the top of crystal silicon；Alternatively, the doping of the outer base area polysilicon in first polysilicon layer by giving birth to
Doping is realized in situ in growth process.
A further improvement is that the first medium layer is silicon oxide layer；The second dielectric layer is silicon nitride layer.
A further improvement is that also there is the 3rd medium between first polysilicon layer and the second dielectric layer
Layer, the 3rd dielectric layer are silicon oxide layer.
A further improvement is that the material of first side wall is silica.
In order to solve the above technical problems, the manufacturing method of Ge-Si heterojunction bipolar transistor provided by the invention is including as follows
Step：
Step 1: providing a silicon substrate, shallow trench is formed on the silicon substrate, the region that the shallow trench is surrounded
The silicon substrate forms active area.
Step 2: counterfeit buried regions is formed on the bottom that the first conduction type heavy doping ion of progress is infused in the shallow trench.
Step 3: filling oxide layer forms shallow trench field oxygen in the shallow trench.
Step 4: carry out the first conductive type ion injection forms collecting zone in the active area.
Step 5: first medium layer, the first polysilicon layer and second dielectric layer are sequentially formed simultaneously using overall growth process
Base Windows media layer is formed by the superposition of the first medium layer, first polysilicon layer and the second dielectric layer.
Step 6: it carries out lithographic definition and the base Windows media layer is performed etching to form base window；The base
Area's window is located at the surface of the active area and the width of the base window is less than or equal to the width of the active area and incites somebody to action
The surface of the collecting zone is exposed.
Step 7: p-type germanium silicon epitaxial layer is formed using comprehensive non-selective epitaxial growth technique；Outside the p-type germanium silicon
Prolong layer and mono-crystalline structures and polycrystalline structure are divided by the base window autoregistration, it is described active in the base window
The p-type germanium silicon epitaxial layer of the part on the surface in area is mono-crystalline structures；Positioned at the side of the base window and the base
The part of the base Windows media layer surface outside area's window is polycrystalline structure.
Step 8: the side autoregistration of the polycrystalline structure in the p-type germanium silicon epitaxial layer of the side of the base window
Form the first side wall, the first side wall autoregistration in the base window defines emitter window；The launch site window
The surface of the mono-crystalline structures of the p-type germanium silicon epitaxial layer of bottom is exposed mouth.
Step 9: forming the second polysilicon layer using comprehensive polycrystalline silicon growth process, second polysilicon layer is by described in
Emitter window is filled up completely and extends to the polycrystalline structure surface of the p-type germanium silicon epitaxial layer outside the emitter window.
Step 10: carrying out polysilicon grinding using the second dielectric layer as stop layer, the polysilicon grinding will be vertical
The polycrystalline structure for being located at second polysilicon layer at the top of the second dielectric layer and the p-type germanium silicon epitaxial layer upwards is all gone
It removes.
By residue the launch site polysilicon is formed in second polysilicon layer in the emitter window；The base
The polycrystalline structure of the p-type germanium silicon epitaxial layer of area's window side and first polysilicon layer are in contact and to form outer base area more
Crystal silicon；Isolated between the launch site polysilicon and the outer base area polysilicon by first side wall.
The launch site polysilicon is the first conduction type heavy doping, and the outer base area polysilicon is the second conduction type weight
Doping.
Step 11: forming launch site, the launch site is formed from the p-type germanium silicon of the emitter window bottom
The first conduction type doped region composition on the mono-crystalline structures surface of epitaxial layer.
Intrinsic base region is formed from the mono-crystalline structures composition of the p-type germanium silicon epitaxial layer of the launch site bottom.
The mono-crystalline structures of the p-type germanium silicon epitaxial layer between the outer base area polysilicon and the intrinsic base region are overlapping
Outer base area, the width of the overlapping outer base area by the width adjusting of first side wall and with self-alignment structure described the
One side wall reduces the width of the overlapping outer base area, so as to reduce base resistance.
Step 12: forming interlayer film, contact hole, deep hole contact and front metal layer, the front metal layer is carried out
It is graphical to form collector, base stage and emitter；The deep hole contact is located at the top of the counterfeit buried regions and passes through the shallow ridges
Slot field oxygen and the interlayer film and and top the collector contact；The base stage is by corresponding through the interlayer film
Contact hole and the outer base area polysilicon contact；The emitter is by passing through corresponding contact hole and the launch site polysilicon
Contact.
A further improvement is that the doping of the launch site polysilicon passes through second polysilicon layer in step 9
Doping is realized in situ in polysilicon growth process.
Alternatively, being formed in step 9 after second polysilicon layer, the second polysilicon layer surface is additionally included in
The step of forming four silicon oxide layers is injected using comprehensive first conduction type heavy doping ion to second polycrystalline afterwards
Silicon layer adulterates, and realizes the doping of the launch site polysilicon.
A further improvement is that in step 11, the doping of the launch site passes through to the miscellaneous of the launch site polysilicon
Matter is done rapid thermal annealing and is diffuseed to form.
A further improvement is that the doping of the outer base area polysilicon passes through the first polysilicon layer described in step 5
Doping is realized in situ in growth course.
Alternatively, after the completion of the polysilicon grinding of step 10, the second dielectric layer is removed, is protected using photoetching process
The top of the launch site polysilicon is protected, the second conduction type heavy doping ion is carried out and injects to form the outer base area polysilicon
Doping.
A further improvement is that the first medium layer is silicon oxide layer；The second dielectric layer is silicon nitride layer.
A further improvement is that also there is the 3rd medium between first polysilicon layer and the second dielectric layer
Layer, the 3rd dielectric layer are silicon oxide layer.
A further improvement is that the material of first side wall is silica, by first silicon oxide deposition afterwards to oxidation
Silicon carries out comprehensive anisotropic etching and forms first side wall.
A further improvement is that Ge-Si heterojunction bipolar transistor is managed for NPN, the first conduction type is N-type, and second is conductive
Type is p-type；Alternatively, Ge-Si heterojunction bipolar transistor is PNP pipe, the first conduction type is p-type, and the second conduction type is N
Type.
The present invention includes the first polysilicon layer, such energy by the setting of base window in base Windows media layer
It is enough to realize using comprehensive non-selective epitaxial growth technique formation p-type germanium silicon epitaxial layer and make p-type germanium silicon epitaxial layer autoregistration
Be divided into mono-crystalline structures and polycrystalline structure, the surface of the active area in base window is in the p-type germanium and silicon epitaxial of mono-crystalline structures
Layer can be used as base, and the p-type germanium silicon epitaxial layer in polycrystalline structure positioned at the side of base window then can be with the first polysilicon
Layer realizes self aligned contact, so as to form the deriving structure of base i.e. outer base area polysilicon well；Compared with existing logical
The p-type germanium silicon epitaxial layer of selective epitaxial formation is crossed, the process costs of p-type germanium silicon epitaxial layer of the invention are lower, and the P formed
The quality higher of type germanium silicon epitaxial layer, non-selective epitaxial growth technique is more ripe, can substantially reduce research and development difficulty.
The present invention defines emitter window also on the basis of base window by the first side wall autoregistration, by being filled in
In emitter window the second polysilicon layer composition launch site polysilicon, can so realize launch site polysilicon bottom region and
Position autoregistration between base, and the first side wall is as the interval between launch site polysilicon and outer base area polysilicon, due to
First side wall is that autoregistration is formed, therefore the thickness of the first side wall is not required photoetching to define, and not only process costs are low, but also can also
So that the thickness of the first side wall accomplishes minimum, so as to reduce the interval between launch site polysilicon and outer base area polysilicon, this
Sample can not only relative increase intrinsic base region area, moreover it is possible to reduce outside intrinsic base region be located at outer base area polysilicon and intrinsic base region
Between p-type germanium silicon epitaxial layer mono-crystalline structures composition overlapping outer base area width, so base resistance can be reduced, due to base
The reduction of area's resistance can improve the maximum frequency of oscillation of device, so the present invention can finally improve the maximum frequency of oscillation of device.
Further, since the emitter window of the present invention is that autoregistration is realized on the basis of base window, thus it is of the invention
The autoregistration between launch site polysilicon and base is realized, does not have photoetching set is inclined to ask between launch site polysilicon and base
Topic, is conducive to the diminution of the lateral dimension of entire device, so as to further improve the maximum frequency of oscillation of device.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Figure 1A-Fig. 1 C are the device architectures in each step of manufacturing method of the first existing Ge-Si heterojunction bipolar transistor
Schematic diagram；
Fig. 2A-Fig. 2 C are the device architectures in each step of manufacturing method of existing second of Ge-Si heterojunction bipolar transistor
Schematic diagram；
Fig. 3 is Ge-Si heterojunction bipolar transistor structure diagram of the embodiment of the present invention；
Fig. 4 A- Fig. 4 G are the Ge-Si heterojunction bipolar transistor structural representations in each step of manufacturing method of the embodiment of the present invention
Figure.
Specific embodiment
As shown in figure 3, it is Ge-Si heterojunction bipolar transistor structure diagram of the embodiment of the present invention；Germanium of the embodiment of the present invention
Si heterojunction bipolar transistor is formed on silicon substrate 101, and active area is isolated by shallow trench field oxygen 104, the Ge-Si heterojunction
Bipolar transistor includes：
Collecting zone 103, the first conductive type ion injection region composition being formed from the active area.
Counterfeit buried regions 102, the first conduction type for being formed from 104 bottom of shallow trench field oxygen of the active area both sides are heavily doped
Heteroion injection region forms, the counterfeit buried regions 102 and the laterally contact contact of the collecting zone 103；At counterfeit 102 top of buried regions
Be formed through the deep hole contact of shallow trench field oxygen 104, by the deep hole contact by the collecting zone 103 be connected to by
The collector of front metal layer composition.
With reference to shown in Fig. 4 B, base window 301, by being formed after 301 dielectric layer chemical wet etching of base window, the base
Window 301 dielectric layer in area's includes the first medium floor, the first polysilicon layer 105 and the second medium that are formed using overall growth process
The superimposed layer of layer 111；The base window 301 is located at the surface of the active area and the width of the base window 301 is small
It is exposed in the width equal to the active area and by the surface of the collecting zone 103.
P-type germanium silicon epitaxial layer 106, the p-type germanium silicon epitaxial layer 106 use comprehensive non-selective epitaxial growth technique shape
Into the p-type germanium silicon epitaxial layer 106 is divided into mono-crystalline structures and polycrystalline structure by 301 autoregistration of base window, positioned at institute
The p-type germanium silicon epitaxial layer 106 for stating the part on the surface of the active area in base window 301 is mono-crystalline structures；It is located at
The part of 301 dielectric layer surface of base window outside the side of the base window 301 and the base window 301 is
Polycrystalline structure.It please refers to Fig.4 simultaneously shown in C, positioned at the polycrystalline of the p-type germanium silicon epitaxial layer 106 of the side of the base window 301
Structure is marked with mark 106a.
With reference to shown in Fig. 4 D, emitter window 302 is defined, first side wall by 108 autoregistration of the first side wall
108 autoregistrations are formed at the side of the polycrystalline structure of the p-type germanium silicon epitaxial layer 106 of the side of the base window 301, institute
It states emitter window 302 surface of the mono-crystalline structures of the p-type germanium silicon epitaxial layer 106 of bottom is exposed.
With reference to shown in Fig. 4 E, the second polysilicon layer 109 for being formed using comprehensive polycrystalline silicon growth process, described second
The emitter window 302 is filled up completely and extends to the p-type germanium outside the emitter window 302 by polysilicon layer 109
The polycrystalline structure surface of silicon epitaxy layer 106；The second dielectric layer 111 as polysilicon grinding stop layer and define transmitting
The height of area's polysilicon 109, in the longitudinal direction second polysilicon layer 109 positioned at 111 top of the second dielectric layer and institute
The polycrystalline structure for stating p-type germanium silicon epitaxial layer 106 is all removed.
By residue the launch site polysilicon is formed in second polysilicon layer 109 in the emitter window 302
109；The polycrystalline structure 106a and first polysilicon layer of the p-type germanium silicon epitaxial layer 106 of 301 side of base window
105 are in contact and form outer base area polysilicon；By described between the launch site polysilicon 109 and the outer base area polysilicon
First side wall 108 is isolated.
The launch site polysilicon 109 is the first conduction type heavy doping, and the outer base area polysilicon is the second conductive-type
Type heavy doping.
Launch site 107 is formed from the monocrystalline knot of the p-type germanium silicon epitaxial layer 106 of 302 bottom of emitter window
The first conduction type doped region composition on structure surface.
Intrinsic base region is formed from the mono-crystalline structures group of the p-type germanium silicon epitaxial layer 106 of 107 bottom of launch site
Into.
The mono-crystalline structures of the p-type germanium silicon epitaxial layer 106 between the outer base area polysilicon and the intrinsic base region are
Overlapping outer base area, the width of the overlapping outer base area is by the width adjusting of first side wall 108 and with self-alignment structure
First side wall 108 reduce the width of the overlapping outer base area, so as to reduce base resistance.
In device of the embodiment of the present invention, the doping of the launch site polysilicon 109 passes through in second polysilicon layer 109
It injects to be formed using comprehensive first conduction type heavy doping ion after the completion of growth.Also can be in other embodiments：It is described
The doping of launch site polysilicon 109 is by the way that doping is realized in situ in 109 growth course of the second polysilicon layer.
In device of the embodiment of the present invention, the doping of the launch site 107 passes through the impurity to the launch site polysilicon 109
Rapid thermal annealing is done to diffuse to form.
In device of the embodiment of the present invention, the second dielectric layer 111 is in the 109 corresponding polysilicon of launch site polysilicon
It is removed after the completion of grinding, the doping of the outer base area polysilicon after the second dielectric layer 111 is removed by carrying out
Second conduction type heavy doping ion is injected to be formed, and is injected in the second conduction type heavy doping ion of the outer base area polysilicon
Described in the top of launch site polysilicon 109 protected by photoresist.Also can be in other embodiments：The outer base area polycrystalline
The doping of silicon is by the way that doping is realized in situ in 105 growth course of the first polysilicon layer.
Preferably, the first medium layer is silicon oxide layer；The second dielectric layer 111 is silicon nitride layer.Described
Also there is the 3rd dielectric layer 112, the 3rd dielectric layer 112 is oxygen between one polysilicon layer 105 and the second dielectric layer 111
SiClx layer.
The material of first side wall 108 is silica.
In present invention method, Ge-Si heterojunction bipolar transistor be NPN pipe, the first conduction type be N-type, second
Conduction type is p-type.Also can be in other embodiments method：Ge-Si heterojunction bipolar transistor is PNP pipe, the first conduction type
For p-type, the second conduction type is N-type.
Device of the embodiment of the present invention includes first by the setting of base window 301 in 301 dielectric layer of base window
Polysilicon layer 105 can so be realized and form p-type germanium silicon epitaxial layer 106 simultaneously using comprehensive non-selective epitaxial growth technique
Make p-type germanium silicon epitaxial layer 106 is self aligned to be divided into mono-crystalline structures and polycrystalline structure, the active area in base window 301
Surface can be used as base in the p-type germanium silicon epitaxial layer 106 of mono-crystalline structures, and positioned at the side of base window 301 in polycrystalline knot
The p-type germanium silicon epitaxial layer 106a of structure then can realize self aligned contact with the first polysilicon layer 105, so as to form base well
The deriving structure in area, that is, outer base area polysilicon；Compared with, the existing p-type germanium silicon epitaxial layer 106 formed by selective epitaxial, this
The process costs of the p-type germanium silicon epitaxial layer 106 of inventive embodiments device are lower, and the quality of the p-type germanium silicon epitaxial layer 106 formed
Higher, non-selective epitaxial growth technique is more ripe, can substantially reduce research and development difficulty.
Device of the embodiment of the present invention is set out also on the basis of base window 301 by 108 autoregistration of the first side wall definition
Area's window 302 is penetrated, launch site polysilicon 109 is formed by the second polysilicon layer 109 being filled in emitter window 302, so
It can realize the position autoregistration between 109 bottom section of launch site polysilicon and base, and the first side wall 108 is used as launch site
Interval between polysilicon 109 and outer base area polysilicon, since the first side wall 108 is that autoregistration is formed, therefore the first side wall 108
Thickness is not required photoetching to define, and not only process costs are low, but also the thickness of the first side wall 108 can also be caused to accomplish minimum, from
And the interval between launch site polysilicon 109 and outer base area polysilicon can be reduced, it so can not only relative increase intrinsic base region
Area, moreover it is possible to reduce the list of the p-type germanium silicon epitaxial layer 106 between outer base area polysilicon and intrinsic base region outside intrinsic base region
The width of the overlapping outer base area of crystal structure composition, so base resistance can be reduced, since base resistor reduction can improve device
Maximum frequency of oscillation, so device of the embodiment of the present invention can finally improve the maximum frequency of oscillation of device.
Further, since the emitter window 302 of device of the embodiment of the present invention is the autoregistration on the basis of base window 301
It realizes, therefore device of the embodiment of the present invention realizes the autoregistration between launch site polysilicon 109 and base, launch site polysilicon
There is no the problem of photoetching set is inclined between 109 and base, be conducive to the diminution of the lateral dimension of entire device, so as to further
Improve the maximum frequency of oscillation of device.
It is the Ge-Si heterojunction bipolar transistor in each step of manufacturing method of the embodiment of the present invention as shown in Fig. 4 A to Fig. 4 G
Structure diagram, the manufacturing method of Ge-Si heterojunction bipolar transistor of the embodiment of the present invention include the following steps：
Step 1: as shown in Figure 4 A, providing a silicon substrate 101, shallow trench is formed on the silicon substrate 101, it is described shallow
The silicon substrate 101 in the region that groove is surrounded forms active area.
Step 2: as shown in Figure 4 A, carry out the bottom shape that the first conduction type heavy doping ion is infused in the shallow trench
Into counterfeit buried regions 102.
Step 3: as shown in Figure 4 A, filling oxide layer forms shallow trench field oxygen 104 in the shallow trench.
Step 4: it as shown in Figure 4 B, carries out the first conductive type ion injection and forms collecting zone in the active area
103。
Step 5: as shown in Figure 4 B, first medium layer, the first polysilicon layer 105 are sequentially formed using overall growth process
With second dielectric layer 111 and by the folded of the first medium layer, first polysilicon layer 105 and the second dielectric layer 111
Add to form 301 dielectric layer of base window.
Preferably, the first medium layer is silicon oxide layer；The second dielectric layer 111 is silicon nitride layer.Described
Also there is the 3rd dielectric layer 112, the 3rd dielectric layer 112 is oxygen between one polysilicon layer 105 and the second dielectric layer 111
SiClx layer.
Step 6: it as shown in Figure 4 B, carries out lithographic definition and 301 dielectric layer of base window is performed etching to form base
Area's window 301；The width that the base window 301 is located at the surface of the active area and the base window 301 is less than etc.
In the active area width and the surface of the collecting zone 103 is exposed.
Step 7: as shown in Figure 4 C, p-type germanium silicon epitaxial layer 106 is formed using comprehensive non-selective epitaxial growth technique；
The p-type germanium silicon epitaxial layer 106 is divided into mono-crystalline structures and polycrystalline structure by 301 autoregistration of base window, positioned at described
The p-type germanium silicon epitaxial layer 106 of the part on the surface of the active area in base window 301 is mono-crystalline structures；Positioned at institute
It is more to state the part of 301 dielectric layer surface of base window outside the side and the base window 301 of base window 301
Crystal structure.The p-type germanium silicon epitaxial layer in polycrystalline structure positioned at the side of the base window 301 is individually with mark 106a
It marks.
Step 8: as shown in Figure 4 D, in the polycrystalline of the p-type germanium silicon epitaxial layer 106 of the side of the base window 301
The side autoregistration of structure forms the first side wall 108,108 autoregistration of the first side wall definition in the base window 301
Go out emitter window 302；The emitter window 302 is by the surface of the mono-crystalline structures of the p-type germanium silicon epitaxial layer 106 of bottom
It is exposed.
Preferably, the material of first side wall 108 is silica, by first carrying out silicon oxide deposition as shown in Figure 4 C
108 the step of, afterwards carries out silica 108 comprehensive anisotropic etching and forms first side wall 108.
Step 9: as shown in Figure 4 E, the second polysilicon layer 109 is formed using comprehensive polycrystalline silicon growth process, described second
The emitter window 302 is filled up completely and extends to the p-type germanium outside the emitter window 302 by polysilicon layer 109
The polycrystalline structure surface of silicon epitaxy layer 106.
It in present invention method, is formed after second polysilicon layer 109, is additionally included in described in step 9
Second polysilicon layer, 109 surface forms the step of the 4th silicon oxide layer 113, afterwards using comprehensive first conduction type heavy doping
Ion implanting adulterates second polysilicon layer 109, realizes the doping of the launch site polysilicon 109.In other embodiments
Also can be in method：The polycrystalline that the doping of the launch site polysilicon 109 passes through second polysilicon layer 109 in step 9
Doping in situ is realized during silicon growth.
Step 10: as illustrated in figure 4f, polysilicon grinding is carried out using the second dielectric layer 111 as stop layer, it is described more
Crystal silicon is ground second polysilicon layer 109 for being located at 111 top of second dielectric layer in the longitudinal direction and the p-type germanium silicon
The polycrystalline structure of epitaxial layer 106 all removes.
By residue the launch site polysilicon is formed in second polysilicon layer 109 in the emitter window 302
109；The polycrystalline structure and first polysilicon layer 105 of the p-type germanium silicon epitaxial layer 106 of 301 side of base window
It is in contact and forms outer base area polysilicon；Pass through described between the launch site polysilicon 109 and the outer base area polysilicon
One side wall 108 is isolated.
The launch site polysilicon 109 is the first conduction type heavy doping, and the outer base area polysilicon is the second conductive-type
Type heavy doping.
In present invention method, as shown in Figure 4 G, after the completion of the polysilicon grinding of step 10, described in removal
Second dielectric layer 111 is protected the top of the launch site polysilicon 109 using photoetching process formation photoetching offset plate figure 115, carried out
Second conduction type heavy doping ion injects the doping to form the outer base area polysilicon.Also can be in other embodiments：Institute
The doping of outer base area polysilicon is stated by the way that doping is real in situ in the growth course of the first polysilicon layer 105 described in step 5
It is existing.
Step 11: as shown in figure 3, launch site 107 is formed, the launch site 107 is formed from the emitter window
The first conduction type doped region composition on the mono-crystalline structures surface of the p-type germanium silicon epitaxial layer 106 of 302 bottoms.It is of the invention real
It applies in a method, the doping of the launch site 107 does rapid thermal annealing diffusion by the impurity to the launch site polysilicon 109
It is formed.
Intrinsic base region is formed from the mono-crystalline structures group of the p-type germanium silicon epitaxial layer 106 of 107 bottom of launch site
Into.
The mono-crystalline structures of the p-type germanium silicon epitaxial layer 106 between the outer base area polysilicon and the intrinsic base region are
Overlapping outer base area, the width of the overlapping outer base area is by the width adjusting of first side wall 108 and with self-alignment structure
First side wall 108 reduce the width of the overlapping outer base area, so as to reduce base resistance.
Step 12: as shown in figure 3, interlayer film, contact hole, deep hole contact and front metal layer are formed, to the front
Metal layer is patterned to form collector, base stage and emitter；The deep hole contact is located at the top of the counterfeit buried regions 102 simultaneously
Through shallow trench field oxygen 104 and the interlayer film and and top the collector contact；The base stage passes through corresponding
Contact hole and the outer base area polysilicon contact through the interlayer film；The emitter by pass through corresponding contact hole and
The launch site polysilicon 109 contacts.
In present invention method, Ge-Si heterojunction bipolar transistor be NPN pipe, the first conduction type be N-type, second
Conduction type is p-type.Also can be in other embodiments method：Ge-Si heterojunction bipolar transistor is PNP pipe, the first conduction type
For p-type, the second conduction type is N-type.
The present invention has been described in detail through specific embodiments, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these also should
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of Ge-Si heterojunction bipolar transistor, is formed on silicon substrate, active area is isolated by shallow trench field oxygen, and feature exists
In the Ge-Si heterojunction bipolar transistor includes：
Collecting zone, the first conductive type ion injection region composition being formed from the active area；
Counterfeit buried regions is formed from the first conduction type heavy doping ion injection of the shallow trench field oxygen bottom of the active area both sides
District's groups are into laterally contact contacts for the counterfeit buried regions and the collecting zone；The shallow ridges is formed through at the top of the counterfeit buried regions
The collecting zone is connected to the collector being made of front metal layer by the deep hole contact of slot field oxygen by the deep hole contact；
Base window, by being formed after base Windows media layer chemical wet etching, the base Windows media layer is included using comprehensively raw
The superimposed layer of first medium layer, the first polysilicon layer and second dielectric layer that long technique is formed；The base window is located at described
The width of the surface of active area and the base window is less than or equal to the width of the active area and by the table of the collecting zone
Face is exposed；
P-type germanium silicon epitaxial layer, the p-type germanium silicon epitaxial layer are formed using comprehensive non-selective epitaxial growth technique, the p-type
Germanium silicon epitaxial layer is divided into mono-crystalline structures and polycrystalline structure by the base window autoregistration, the institute in the base window
The p-type germanium silicon epitaxial layer for stating the part on the surface of active area is mono-crystalline structures；Positioned at the side of the base window and
The part of the base Windows media layer surface outside the base window is polycrystalline structure；
Emitter window, is defined by the first side wall autoregistration, and the first side wall autoregistration is formed at the base window
The side of the polycrystalline structure of the p-type germanium silicon epitaxial layer of side, the emitter window is by the p-type germanium and silicon epitaxial of bottom
The surface of the mono-crystalline structures of layer is exposed；
The second polysilicon layer formed using comprehensive polycrystalline silicon growth process, second polysilicon layer is by the emitter window
It is filled up completely and extends to the polycrystalline structure surface of the p-type germanium silicon epitaxial layer outside the emitter window；Described second is situated between
Matter layer as polysilicon grinding stop layer and define the height of launch site polysilicon, in the longitudinal direction positioned at the second medium
Second polysilicon layer at layer top and the polycrystalline structure of the p-type germanium silicon epitaxial layer are all removed；
By residue the launch site polysilicon is formed in second polysilicon layer in the emitter window；The base window
The polycrystalline structure and first polysilicon layer of the p-type germanium silicon epitaxial layer of mouthful side are in contact and form outer base area polycrystalline
Silicon；Isolated between the launch site polysilicon and the outer base area polysilicon by first side wall；
The launch site polysilicon is the first conduction type heavy doping, and the outer base area polysilicon is heavily doped for the second conduction type
It is miscellaneous；
What launch site was formed from the mono-crystalline structures surface of the p-type germanium silicon epitaxial layer of the emitter window bottom first leads
Electric type doped region composition；
Intrinsic base region is formed from the mono-crystalline structures composition of the p-type germanium silicon epitaxial layer of the launch site bottom；
The mono-crystalline structures of the p-type germanium silicon epitaxial layer between the outer base area polysilicon and the intrinsic base region are to overlap outer base
Area, width adjusting of the width by first side wall of the overlapping outer base area and first side with self-alignment structure
Wall reduces the width of the overlapping outer base area, so as to reduce base resistance.
2. Ge-Si heterojunction bipolar transistor as described in claim 1, it is characterised in that：The doping of the launch site polysilicon
It to be formed by being injected after the completion of second polysilicon layer growth using comprehensive first conduction type heavy doping ion；Or
Person, the doping of the launch site polysilicon is by the way that doping is realized in situ in the second polysilicon layer growth course.
3. Ge-Si heterojunction bipolar transistor as described in claim 1, it is characterised in that：The doping of the launch site by pair
The impurity of the launch site polysilicon does rapid thermal annealing and diffuses to form.
4. Ge-Si heterojunction bipolar transistor as described in claim 1, it is characterised in that：The second dielectric layer is in the hair
It penetrates the corresponding polysilicon grinding of area's polysilicon to be removed after finishing, the doping of the outer base area polysilicon passes through to be situated between described second
Matter layer carries out the second conduction type heavy doping ion after being removed and injects to be formed, and second in the outer base area polysilicon is conductive
The top of launch site polysilicon is protected by photoresist described in the injection of type heavy doping ion；Alternatively, the outer base area polycrystalline
The doping of silicon is by the way that doping is realized in situ in the first polysilicon layer growth course.
5. Ge-Si heterojunction bipolar transistor as described in claim 1, it is characterised in that：The first medium layer is silica
Layer；The second dielectric layer is silicon nitride layer.
6. Ge-Si heterojunction bipolar transistor as claimed in claim 5, it is characterised in that：In first polysilicon layer and institute
Stating also has the 3rd dielectric layer between second dielectric layer, and the 3rd dielectric layer is silicon oxide layer.
7. Ge-Si heterojunction bipolar transistor as claimed in claim 5, it is characterised in that：The material of first side wall is oxygen
SiClx.
8. a kind of manufacturing method of Ge-Si heterojunction bipolar transistor, which is characterized in that include the following steps：
Step 1: providing a silicon substrate, form shallow trench on the silicon substrate, the region that the shallow trench is surrounded it is described
Silicon substrate forms active area；
Step 2: counterfeit buried regions is formed on the bottom that the first conduction type heavy doping ion of progress is infused in the shallow trench；
Step 3: filling oxide layer forms shallow trench field oxygen in the shallow trench；
Step 4: carry out the first conductive type ion injection forms collecting zone in the active area；
Step 5: first medium layer, the first polysilicon layer and second dielectric layer are sequentially formed and by institute using overall growth process
The superposition for stating first medium layer, first polysilicon layer and the second dielectric layer forms base Windows media layer；
Step 6: it carries out lithographic definition and the base Windows media layer is performed etching to form base window；The base window
Mouth is located at the surface of the active area and the width of the base window is less than or equal to the width of the active area and by described in
The surface of collecting zone is exposed；
Step 7: p-type germanium silicon epitaxial layer is formed using comprehensive non-selective epitaxial growth technique；The p-type germanium silicon epitaxial layer
Mono-crystalline structures and polycrystalline structure are divided by the base window autoregistration, the active area in the base window
The p-type germanium silicon epitaxial layer of the part on surface is mono-crystalline structures；Positioned at the side of the base window and the base window
The part of the base Windows media layer surface outside mouthful is polycrystalline structure；
Step 8: the side autoregistration in the polycrystalline structure of the p-type germanium silicon epitaxial layer of the side of the base window is formed
First side wall, the first side wall autoregistration in the base window define emitter window；The emitter window will
The surface of the mono-crystalline structures of the p-type germanium silicon epitaxial layer of bottom is exposed；
Step 9: forming the second polysilicon layer using comprehensive polycrystalline silicon growth process, second polysilicon layer is by the transmitting
Area's window is filled up completely and extends to the polycrystalline structure surface of the p-type germanium silicon epitaxial layer outside the emitter window；
Step 10: carrying out polysilicon grinding using the second dielectric layer as stop layer, the polysilicon grinding will in the longitudinal direction
The polycrystalline structure of second polysilicon layer and the p-type germanium silicon epitaxial layer at the top of the second dielectric layer all removes；
By residue the launch site polysilicon is formed in second polysilicon layer in the emitter window；The base window
The polycrystalline structure and first polysilicon layer of the p-type germanium silicon epitaxial layer of mouthful side are in contact and form outer base area polycrystalline
Silicon；Isolated between the launch site polysilicon and the outer base area polysilicon by first side wall；
The launch site polysilicon is the first conduction type heavy doping, and the outer base area polysilicon is heavily doped for the second conduction type
It is miscellaneous；
Step 11: forming launch site, the launch site is formed from the p-type germanium and silicon epitaxial of the emitter window bottom
The first conduction type doped region composition on the mono-crystalline structures surface of layer；
Intrinsic base region is formed from the mono-crystalline structures composition of the p-type germanium silicon epitaxial layer of the launch site bottom；
The mono-crystalline structures of the p-type germanium silicon epitaxial layer between the outer base area polysilicon and the intrinsic base region are to overlap outer base
Area, width adjusting of the width by first side wall of the overlapping outer base area and first side with self-alignment structure
Wall reduces the width of the overlapping outer base area, so as to reduce base resistance；
Step 12: forming interlayer film, contact hole, deep hole contact and front metal layer, figure is carried out to the front metal layer
Change forms collector, base stage and emitter；The deep hole contact is located at the top of the counterfeit buried regions and passes through the shallow trench field
Oxygen and the interlayer film and and top the collector contact；The base stage passes through the corresponding contact through the interlayer film
Hole and the outer base area polysilicon contact；The emitter is by passing through corresponding contact hole and the launch site polysilicon to connect
It touches.
9. the manufacturing method of Ge-Si heterojunction bipolar transistor as claimed in claim 8, it is characterised in that：The launch site is more
The doping of crystal silicon is by the way that doping is realized in situ in the polysilicon growth process of second polysilicon layer of step 9；
Alternatively, being formed in step 9 after second polysilicon layer, it is additionally included in the second polysilicon layer surface and is formed
The step of four silicon oxide layers, is injected using comprehensive first conduction type heavy doping ion to second polysilicon layer afterwards
Doping, realizes the doping of the launch site polysilicon.
10. the manufacturing method of Ge-Si heterojunction bipolar transistor as claimed in claim 8, it is characterised in that：In step 11,
The doping of the launch site is done rapid thermal annealing by the impurity to the launch site polysilicon and is diffuseed to form.
11. the manufacturing method of Ge-Si heterojunction bipolar transistor as claimed in claim 8, it is characterised in that：The outer base area
The doping of polysilicon is by the way that doping is realized in situ in the growth course of the first polysilicon layer described in step 5；
Alternatively, after the completion of the polysilicon grinding of step 10, the second dielectric layer is removed, institute is protected using photoetching process
The top of launch site polysilicon is stated, the second conduction type heavy doping ion is carried out and injects to form mixing for the outer base area polysilicon
It is miscellaneous.
12. the manufacturing method of Ge-Si heterojunction bipolar transistor as claimed in claim 8, it is characterised in that：Described first is situated between
Matter layer is silicon oxide layer；The second dielectric layer is silicon nitride layer.
13. the manufacturing method of Ge-Si heterojunction bipolar transistor as claimed in claim 12, it is characterised in that：Described first
Also there is the 3rd dielectric layer, the 3rd dielectric layer is silicon oxide layer between polysilicon layer and the second dielectric layer.
14. the manufacturing method of Ge-Si heterojunction bipolar transistor as claimed in claim 12, it is characterised in that：First side
The material of wall is silica, and described first is formed by carrying out comprehensive anisotropic etching to silica after first silicon oxide deposition
Side wall.
15. the manufacturing method of the Ge-Si heterojunction bipolar transistor as described in any claim in claim 1 to 14, feature exist
In：Ge-Si heterojunction bipolar transistor is managed for NPN, and the first conduction type is N-type, and the second conduction type is p-type；Alternatively, germanium silicon
Heterojunction bipolar transistor is PNP pipe, and the first conduction type is p-type, and the second conduction type is N-type.
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| CN111883428A (en) * | 2020-07-16 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Method and device for forming polycrystalline silicon of emitter region |
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