CN100508209C - NPN type germanium-silicon heterogenous dual-pole transistor and its making method - Google Patents
NPN type germanium-silicon heterogenous dual-pole transistor and its making method Download PDFInfo
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- CN100508209C CN100508209C CNB2007101198503A CN200710119850A CN100508209C CN 100508209 C CN100508209 C CN 100508209C CN B2007101198503 A CNB2007101198503 A CN B2007101198503A CN 200710119850 A CN200710119850 A CN 200710119850A CN 100508209 C CN100508209 C CN 100508209C
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Abstract
The invention is concerned with a kind of NPN type of SiGe heterojunction bipolar transistor and its preparation method, belonging to semiconductor device preparation technology field. Implant selectivity ion into impure collector, and carry epitaxial growth of SiGe base area after high temperature annealing. It activates the implanted impurity primely and keeps the quality of SiGe layer. Product integrating circuit unit apparatus, and its collector is at a same plane with base pole and emitter. This method carries epitaxial growth of N- collector and SiGe area to reduce autoeciousness parameter of apparatus. It uses sidewall to separate and form silicide on outside base area and emitter to reduce resistance between base pole and emitter and enhance high frequency capability of apparatus.
Description
Technical field
The invention belongs to the semiconductor device preparing technical field, particularly the Ge-Si heterojunction bipolar transistor and the manufacture method thereof of a kind of NPN type of NPN type Ge-Si heterojunction bipolar transistor (SiGeHBT).
Background technology
Because have the germanium and silicon heterogeneous junction transistors of energy band engineering characteristics, its performance obviously is better than having the silicon bipolar transistor of doping engineering characteristic, has obtained swift and violent development in recent years.The band structure of NPN type SiGeHBT has suppressed the hole, base and has injected to the emitter region, the electronics that helps the emitter region injects to the base, therefore improved the injection efficiency of emitter, current gain is mainly no longer only determined by the impurity concentration ratio of emitter region and base by being with definite, base impurity concentration can significantly be improved, accomplish that the base is very thin but base resistance can be very little, make device that performances such as good frequency, power gain and noise thereof be arranged.
The structure of SiGeHBT has non-autoregistration, autoregistration and three kinds of forms of super-self-aligned, the complex process of autoregistration and super-self-aligned structure, the technology of existing non-self-alignment structure is fairly simple, but also there is defective, carry out after the SiGe extension such as selecting ion to inject collector region (SIC), foreign ion penetrated the SiGe layer, bring to a certain degree lattice damage for the SiGe layer, and annealing temperature and time that lattice need to recover are subjected to certain restriction, otherwise make SiGe layer relaxation easily, cause the electric leakage of knot.In addition, the step that adopts deep trench isolation to bring needs the backfill planarization, otherwise will cause difficulty to the technology of back, for example the metal bar etc. that easily breaks at the step place.At last, base resistance and contact resistance thereof in the conventional bipolar junction transistor all are difficult to do little, and base resistance and each ohmic contact resistance are very big to the high frequency power gain and the noiseproof feature influence of device, need to reduce base resistance and each ohmic contact resistance, to improve the high frequency performance of device.Therefore, structure and the arts demand of Chang Gui non-autoregistration SiGeHBT further improve.
Summary of the invention
The Ge-Si heterojunction bipolar transistor and the manufacture method thereof that the purpose of this invention is to provide a kind of NPN type.
N+ buried regions district 2 and P+ shading ring 3 are set on P type silicon substrate 1, and N+ buried regions district 2 thickness are concordant substantially with P type substrate 1 upper surface, keep SiO on the P type substrate 1 on 2 both sides, N+ buried regions district
2Layer 7, it on N+ buried regions district 2 selectivity Si extension N-district 5, inlaying SIC in this district as the collector region 6 of selecting ion to inject, is that collector electrode is drawn N+ district 4 in the selectivity Si extension N-district 5 on collector region 6 the right, and collector region 6 contacts with N+ buried regions district 2 with the lower plane that collector electrode is drawn N+ district 4; Planar growth one layer-selective SiGe epitaxial region 8 on said structure, 5 both sides, selectivity Si extension N-district are the U type side wall medium layer 12.1 of passing selectivity SiGe epitaxial region 8, insert hole medium 14 in the U type groove of U type side wall medium layer 12.1; SiO above the selectivity SiGe epitaxial region 8
2Emitter window on the layer 9 is corresponding with collector region 6, and the polysilicon of ion implantation doping is having the SiO of emitter window
2Form T type polysilicon emitter 10 on the layer 9, the part of the ion implantation doping outer base area 11 that is formed by the autoregistration of T type polysilicon emitter has the SiGe layer of boron ion implantation, and becomes the zone of P+ silicon because of mixing boron in the following N-silicon epitaxy layer.It is silicide 13 that polysilicon emitter 10 and ion inject above the outer base area 11, and metal electrode 15 is separately positioned on polysilicon emitter 10, outer base area 11 and collector electrode and draws on the N+ district 4, and the lower surface of metal electrode is on silicide 13; Metal interlayer medium 16 covers the entire device upper surface, and upper strata metal 17 is connected by through hole on the metal interlayer medium 16 and metal electrode 15.
Be provided with around the described polysilicon emitter 10 and split type medium side wall 12.
Described collector electrode, base stage and emitter are at grade integrated.
The manufacture method of the Ge-Si heterojunction bipolar transistor of described NPN type, this method adopts conventional microfabrication, and the process characteristic of the Ge-Si heterojunction bipolar transistor of manufacturing NPN type is as follows:
1. the formation of collector region is at first, in P type＜100〉make SiO on the silicon chip 1
2 Layer 7 utilizes dry etching or/and wet etching, at SiO
2Leave the window of local N+ buried regions 2 on the layer 7, and inject N type impurity arsenic, antimony or the phosphorus of high dose, high temperature furnace annealing then meets design requirement the junction depth of N+/P, and it is dark to be generally 1-3 μ m, and the boron ion injects and forms P+ shading ring 3 or making SiO
2Carry out before the layer 7, the impurity concentration of P+ shading ring is 10
17/ cm
3Reduced pressure chemical vapor deposition (RPCVD) or high vacuum chemical vapor deposition (UHVCVD) carry out the selective silicon extension, and original position is mixed low concentration N type impurity, at SiO
2Obtain the N-silicon epitaxy layer 5 of low concentration in the window that layer 7 limits.Carry out selectivity ion implantation doping afterwards on the position corresponding with emitter junction, mixing concentration is 10
16/ cm
3～2 * 10
17/ cm
3N type foreign matter of phosphor or arsenic, through the short annealing of 950 ℃, 30 minutes annealing of furnace temperature or 1050 ℃, 20 seconds, finish the impurity activation of selecting the collector region 6 that ion injects and distribute again, owing to 6 higher of collector regions of concentration concentrate on and SiO
2The emitter junction The corresponding area that window limited of layer 9, and the N-district impurity concentration below the outer base area 11 is very low, has so both guaranteed the electric current and the frequency performance of device, has limited the electric capacity of BC knot again, helps improving the high frequency power gain performance of device;
2.SiGe the formation of base is carried out selectivity SiGe extension with RPCVD or UHVCVD, is selecting to form SiGe district 8 on the N-silicon epitaxy district (comprising collector region), general thickness is tens nanometers;
3. the formation of emitter and outer base area inject, with thermal decomposition method deposit SiO
2, utilize photoresist masking, with optionally dry etching or wet etching are left emitter-window, the deposit un-doped polysilicon; Adopt ion to inject the N type impurity (phosphorus and/or arsenic) that mixes high dose, finish the making of emitter mesa with reactive ion etching and wet etching, and as the p type impurity (boron or boron difluoride) that is sequestered in outer base area injection high dose;
4. with thermal decomposition method deposit SiO
2, be sequestered in the position that collector electrode draws with photoresist and remove SiO
2, and the N type impurity of injection high dose, make the collector electrode draw-out area, adopt rapid thermal annealing to activate implanted dopant.The RIE dry back is carved SiO in active area
2, make the both sides of emitter mesa form side wall 12; Splash-proofing sputtering metal titanium or nickel or cobalt, double annealing add selective wet etching Ti or nickel or cobalt, and base region surface, emitter surface and surface, collector electrode draw-out area form silicide outside;
5. make the hole medium, leave the ohmic contact window with selective etch or corrosion, can in contact window, replenish silicide, the complex metal layer of deposit contact layer+barrier layer+conductive layer in case of necessity, make the metal interconnected postchannel process of Denging then in the usual way, can obtain high performance SiGeHBT.
The technology of the Ge-Si heterojunction bipolar transistor of described manufacturing NPN type is made following change:
1. substrate 1 is changed into N+＜100〉silicon materials;
2. save P+ shading ring, SiO
2 Floor 7 and N+ buried regions district directly carry out the non-selective N-silicon epitaxy of large tracts of land on the N+ substrate;
3. save and make collector electrode draw-out area, collector electrode fairlead and collector electrode extraction electrode;
4. save inter-level dielectric and upper strata metal;
Can realize that then the back side is the discrete device making of collector electrode, its technology is simpler.
Beneficial effect of the present invention is:
1) adopt and to do selectivity ion implantation doping collector region earlier, the method for epitaxy Si Ge base again behind high annealing both can activate implanted dopant well, did not influence the quality in SiGe district again.
2) adopt selectivity Si epitaxial growth N-collector region and SiGe district, help reducing the parasitic parameter of device.
3) adopt simple technology, utilize side wall to isolate, simultaneously on outer base area and emitter, form silicide, thereby can reduce the serial resistance (comprising relevant sheet resistance and ohmic contact resistance) of base stage and emitter well, improve the high frequency performance of device effectively.
4) can make collector electrode and base stage and emitter integrated circuit unit device at grade
Description of drawings
Fig. 1 is collector electrode and base stage and emitter SiGeHBT structure at grade.
Fig. 2 is the SiGeHBT structure of collector electrode for the back side.
Fig. 3 is made up of P type substrate, local N+ buried regions, P+ shading ring, selective epitaxy N-layer and collector region.
Fig. 4 is made up of P type substrate, local N+ buried regions, P+ shading ring, selective epitaxy N-floor, SIC district and selectivity SiGe epitaxial loayer.
Fig. 5 is polysilicon emitter and the outer base area on the above-mentioned composition.
Fig. 6 is on surface, collector electrode draw-out area, outer base area surface and emitter mesa, has formed Titanium silicide or nickel silicide or cobalt silicide, and wherein the silicide on outer base area surface and the emitter mesa forms with self-aligned manner.
Embodiment
The invention provides a kind of Ge-Si heterojunction bipolar transistor (SiGeHBT) and manufacture method thereof of NPN type, its structure is seen schematic diagram 1 (annotate: the top electrode and the through hole of the collector electrode that only drawn among the figure, the top electrode and the through hole of emitter and base stage do not draw).Through simplification step, also can make the discrete device that the back side is collector electrode, its structure is seen schematic diagram 2.This method adopts conventional microfabrication, and the manufacturing technical feature of the Ge-Si heterojunction bipolar transistor of NPN type is as follows:
1. the formation of collector region is at first, in P type＜100〉make SiO on the silicon chip 1
2 Layer 7 utilizes dry etching or/and wet etching, at SiO
2Leave the window of local N+ buried regions 2 on the layer 7, and inject N type impurity arsenic, antimony or the phosphorus of high dose, high temperature furnace annealing then meets design requirement the junction depth of N+/P, and it is dark to be generally 1-3 μ m.The boron ion injects formation P+ shading ring 3, and (this step also can made SiO
2Carry out before the layer 7), the impurity concentration of P+ shading ring is about 10
17/cm
3Reduced pressure chemical vapor deposition (RPCVD) or high vacuum chemical vapor deposition (UHVCVD) carry out the selective silicon extension, and original position is mixed low concentration N type impurity, at SiO
2Obtain the N-silicon epitaxy layer 5 of low concentration in the window that layer 7 limits.On the position corresponding, carry out selectivity ion implantation doping afterwards, mix higher concentration (10 with emitter junction
16/ cm
3～2 * 10
17/ cm
3) N type foreign matter of phosphor or arsenic, through the short annealing of 950 ℃, 30 minutes annealing of furnace temperature or 1050 ℃, 20 seconds, finish the impurity activation of collector region 6 and distribution again.Because the SIC layer of the collector region that concentration is higher only concentrates on and SiO
2The emitter junction The corresponding area that window limited of layer 9, and the N-district impurity concentration below the outer base area 11 is very low, has so both guaranteed the electric current and the frequency performance of device, has limited the electric capacity of BC knot again, helps improving the high frequency power gain performance of device.(referring to schematic diagram 3).
2.SiGe the formation of base is carried out selectivity SiGe extension with RPCVD or UHV/CVD, is selecting to form SiGe district 8 on the N-silicon epitaxy district (comprising collector region), general thickness is tens nanometers (referring to schematic diagrames 4).
3. the formation of emitter and outer base area inject, with thermal decomposition method deposit SiO
2, utilize photoresist masking, with optionally dry etching or wet etching are left emitter-window, the deposit un-doped polysilicon; Adopt ion to inject the N type impurity (phosphorus and/or arsenic) that mixes high dose, finish the making of emitter mesa with reactive ion etching and wet etching, and as the p type impurity (boron or boron difluoride) that is sequestered in outer base area injection high dose.(referring to schematic diagram 5).
4. with thermal decomposition method deposit SiO
2, be sequestered in the position that collector electrode draws with photoresist and remove SiO
2, and the N type impurity of injection high dose, make the collector electrode draw-out area, adopt rapid thermal annealing to activate implanted dopant.The RIE dry back is carved SiO in active area
2, make the both sides of emitter mesa form side wall 12.Splash-proofing sputtering metal titanium or nickel or cobalt, double annealing add selective wet etching Ti or nickel or cobalt, and base region surface, emitter surface and surface, collector electrode draw-out area form silicide outside.(referring to schematic diagram 6).
5. make the hole medium, leave the ohmic contact window, can in contact window, replenish silicide in case of necessity, deposit composition metal (contact layer+barrier layer+conductive layer) with selective etch or corrosion.Make the metal interconnected postchannel process of Denging in the usual way, can obtain high performance SiGeHBT.(referring to schematic diagram 1)
If the present invention is made following change:
5. substrate 1 is changed into the N+ material;
6. save P+ shading ring, SiO
2 Floor 7 and N+ buried regions district directly carry out large tracts of land N silicon epitaxy on the N+ substrate;
7. save and make collector electrode draw-out area, collector electrode fairlead and collector electrode extraction electrode;
8. save through hole and upper strata metal electrode;
Can realize that then the back side is the discrete device making of collector electrode, its technology is simpler.Its structure is referring to schematic diagram 2.
Generally, the N-Si layer is the method with the normal pressure extension, carries out large-area Si extension and utilize shallow slot and deep trouth that the collector region of each device is kept apart then on whole wafer, has influence on the technology of back for fear of the step of groove, must be with SiO
2Insert in the groove with polysilicon, and return to carve and realize planarization, in the present invention, utilize selective epitaxy only on single crystalline Si, to carry out isoepitaxial growth, and at SiO
2Go up because Si can't nucleation, utilize the SiO that makes local N+ buried regions
2Window, the zone of N-silicon is exposed with needing, and just can obtain selective N-Si epitaxial loayer on exposed silicon.Because selective N-Si epi region is the isolated island shape, and SiO is arranged each other
2Isolate, therefore can save technologies such as carving deep trouth and backfill planarization thereof, simplified processing step.Referring to Fig. 3.
The present invention selects carry out selectivity ion implantation doping this moment on corresponding to the position of emitter window, injects an amount of N type impurity.(at this moment also can in the zone of collector electrode fairlead, inject the N type impurity of high dose according to the thickness of N-layer.When the N-layer was thin, this step can not do yet).This moment, the mode and the condition of annealing were unrestricted, can obtain perfect lattice and desirable Impurity Distribution owing to there is not the existence of SiGe layer.SIC zone among Fig. 4 is collector region 6, because 6 higher of collector regions of concentration concentrate on and SiO
2In the emitter junction The corresponding area that layer 9 limits, and the N-district concentration below the outer base area 11 is still very low, very helps reducing the BC junction capacitance of SiGeHBT, improves its high frequency performance.After SIC finishes, still with selective epitaxial growth SiGe district, to reduce the parasitic capacitance between base stage and the collector electrode as far as possible.
The present invention is after base doping is finished outside, outside on base region surface, the emitter mesa and collector electrode draw the trap inner surface and form Titanium silicide or cobalt silicide, wherein the silicide on outer base area surface and the emitter mesa is the self-aligned manner formation of adopting side wall to isolate.Conventional BJT does not do silicide usually, and minority is with the mode of photoetching, at SiO
2On leave window, shape silicide in window area.Because the present invention is a self-aligned manner, therefore in the maximum magnitude on emitter mesa and outer base area surface, formed silicide, can reduce the ohmic contact resistance of outer base area sheet resistance and base stage and emitter better, improve the high frequency power gain and the noiseproof feature of device.Structure is referring to Fig. 6.In order to guarantee the ohmic contact resistance of base stage and emitter, also can after forming, contact hole in the hole, further replenish silicide in case of necessity.
Between the SIC and emitter window among the present invention, outer base area injects and emitter window between be not self aligned, wherein the former is less demanding for what aim at, the alignment precision of 0.8um mask aligner can satisfy the device performance requirement fully.The same with traditional non-autoregistration SiGeHBT structure, outer base area injects higher slightly for the requirement of aiming at emitter window, otherwise the base series resistance of emitter both sides is with asymmetric.Should reduce series resistance shared proportion in whole Rb in base, emitter both sides during design as far as possible.
Claims (5)
1. the Ge-Si heterojunction bipolar transistor of a NPN type, it is characterized in that, P+ shading ring (3) and N+ buried regions district (2) are set on P type silicon substrate (1), N+ buried regions district (2) thickness is concordant substantially with P type substrate (1) upper surface, keeps SiO on the P type substrate (1) on both sides, N+ buried regions district (2)
2(7), it on N+ buried regions district (2) selectivity Si extension N-district (5), the selectivity ion that the SIC material is inlayed at this middle part, district injects collector region (6), in collector region (6) selective epitaxy N-district, the right (5) is that collector electrode is drawn N+ district (4), and the selectivity ion injects collector region (6) and contacts with N+ buried regions district (2) with the lower plane that collector electrode is drawn N+ district (4).Planar growth one layer-selective SiGe epitaxial region (8) on said structure, both sides, selectivity Si extension N-district (5) are the U type side wall medium layer (12.1) of passing selectivity SiGe epitaxial region (8), insert hole medium (14) in the U type groove of U type side wall medium layer (12.1); SiO above the selectivity SiGe epitaxial region (8)
2Emitter window on the layer (9) is corresponding with collector region (6), and the polysilicon emitter of ion implantation doping (10) is having the SiO of emitter window
2Layer (9) go up to form T type polysilicon emitter, and the part of the ion implantation doping outer base area (11) that is formed by T type emitter-self-alignment has the SiGe layer of boron ion implantation and the zone that becomes P+ silicon in the following N-silicon epitaxy layer because of injection boron.It is silicide (13) that polysilicon emitter (10) and ion inject above the outer base area (11), metal electrode (15) is separately positioned on polysilicon emitter (10), outer base area (11) and collector electrode and draws on the N+ district (4), and the lower surface of metal electrode is on silicide (13); Metal interlayer medium (16) covers the entire device upper surface, and upper strata metal (17) is connected by through hole on the metal interlayer medium (16) and metal electrode (15).
2. according to the Ge-Si heterojunction bipolar transistor of the described NPN type of claim 1, it is characterized in that described polysilicon emitter (10) is established in addition and split type medium side wall (12) on every side.
3. according to the Ge-Si heterojunction bipolar transistor of the described NPN type of claim 1, it is characterized in that described collector electrode, base stage and emitter are at grade integrated.
4.NPN the manufacture method of the Ge-Si heterojunction bipolar transistor of type is characterized in that, the manufacture method of the Ge-Si heterojunction bipolar transistor of described NPN type is to adopt conventional microfabrication, and its manufacturing technical feature is as follows:
1), the formation of collector region, at first, and in P type＜100〉the last SiO that makes of silicon chip (1)
2Layer (7) utilizes dry etching or/and wet etching, at SiO
2Layer leave on (7) local N+ buried regions (2 window, and inject N type impurity arsenic, antimony or the phosphorus of high dose, high temperature furnace annealing then meets design requirement the junction depth of N+/P, it is dark to be generally 1-3 μ m, the boron ion injects and forms P+ shading ring (3) or making SiO
2Layer (7) carries out before, and the impurity concentration of P+ shading ring is 10
17/ cm
3Reduced pressure chemical vapor deposition RPCVD or high vacuum chemical vapor deposition UHVCVD carry out the selective silicon extension, and original position is mixed low concentration N type impurity, at SiO
2The N-silicon epitaxy layer (5) that obtains low concentration in the window that layer (7) limits carries out selectivity ion implantation doping afterwards on the position corresponding with emitter junction, mixing concentration is 10
16/ cm
3～2 * 10
17/ cm
3N type foreign matter of phosphor or arsenic, through the short annealing of 950 ℃/30 minutes furnace annealings or 1050 ℃/20 seconds, finish the selectivity ion and inject the impurity activation of collector region (6) and distribute again, owing to the higher collector region (6) of concentration only concentrates on and SiO
2The emitter junction The corresponding area that window limited of layer (9), and the N-district impurity concentration below the outer base area (11) is very low, so both guarantee the electric current and the frequency performance of device, limited the electric capacity of BC knot again, helped improving the high frequency power gain performance of device;
2), the formation of SiGe base is carried out selectivity SiGe extension with RPCVD or UHVCVD, is selecting to form SiGe district (8) on the N-silicon epitaxy district, and thickness is tens nanometers;
3), the formation of emitter and outer base area inject, with thermal decomposition method deposit SiO
2, utilize photoresist masking, with optionally dry etching or wet etching are left emitter-window, the deposit un-doped polysilicon; Adopting ion to inject and mixing above-mentioned concentration is 10
16/ cm
3～2 * 10
17/ cm
3N type foreign matter of phosphor or arsenic, finish the making of emitter mesa with reactive ion etching and wet etching, and as being sequestered in p type impurity boron or the boron difluoride that outer base area injects high dose;
4), with thermal decomposition method deposit SiO
2, be sequestered in the position that collector electrode draws with photoresist and remove SiO
2, and the N type impurity of injection high dose, make the collector electrode draw-out area, adopt rapid thermal annealing to activate implanted dopant, the RIE dry back is carved SiO in active area
2, make the both sides of emitter mesa form side wall (12), splash-proofing sputtering metal titanium or nickel or cobalt, double annealing adds selective wet etching Ti or nickel or cobalt, and base region surface, emitter surface and surface, collector electrode draw-out area form silicide outside;
5), make the hole medium, leave the ohmic contact window with selective etch or corrosion, or in contact window, replenish silicide, the complex metal layer of deposit contact layer+barrier layer+conductive layer is made metal interconnected postchannel process then in the usual way, can obtain high performance SiGeHBT.
5. according to the manufacture method of the Ge-Si heterojunction bipolar transistor of the described NPN type of claim 4, it is characterized in that, the material of described substrate (1) is by P type＜100〉silicon changes N+＜100 into〉silicon materials, directly on the N+ substrate, carry out the N-extension, thereby save P+ shading ring, SiO
2Floor (7) and N+ buried regions district also save simultaneously and make collector electrode draw-out area, collector electrode fairlead, collector electrode extraction electrode, metal interlayer medium and upper strata metal electrode; Can realize that then the back side is the discrete device making of collector electrode, its technology is simpler.
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|---|---|---|---|---|
| CN102544082A (en) * | 2010-12-17 | 2012-07-04 | 上海华虹Nec电子有限公司 | Si-ge heterojunction NPN (negative-positive-negative) triode device and manufacturing method thereof |
| CN102544082B (en) * | 2010-12-17 | 2014-10-08 | 上海华虹宏力半导体制造有限公司 | Si-ge heterojunction NPN (negative-positive-negative) triode device and manufacturing method thereof |
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| CN101101922A (en) | 2008-01-09 |
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