CN102833201B - Highway addressable remote transducer (HART) modem based on singlechip, and implementation method thereof - Google Patents

Abstract

The invention discloses a highway addressable remote transducer (HART) modem and an implementation method of the HART modem. According to the HART modem, a data receiving module, a parallel to series conversion module and a modulation module are sequentially connected with one another and are connected with a buffering or filtration or blocking module through a first gating switch together with a half duplex control module; a data sending module, a series to parallel conversion module and a demodulation module are sequentially connected with one another; a period module and a threshold module are connected with the demodulation module through a second gating switch; a filtration or biasing module is respectively connected with the period module and the threshold module; and an isolation module is respectively connected with the buffering or filtration or blocking module and the filtration or biasing module and then connected with an input/output module. The HART modem can be implemented based on a singlechip, so that the problems of relatively high cost, single commodity supply way and the like in the prior art are solved.

Description

SCM Based HART modulator-demodulator and its implementation

Technical field

The present invention relates to a kind of based on chip microcontroller, HART (HighwayAddressable Remote Transducer can be supported, highway addressable remote transducer) modulator-demodulator of agreement, also relate to the method that this HART modulator-demodulator realizes demodulation simultaneously, belong to technical field of automation in industry.

Background technology

Along with the fast development of industrial automation, PLC (Programmable LogicController, programmable logic controller (PLC)), the automatic control equipment such as DCS (Distributed Control System, dcs) obtains large-scale application in industry spot.This proposes more and more higher requirement to the communication support ability of industry spot.On the one hand, in industry spot with transmitter be representative ancillary equipment need communicate whenever and wherever possible with control appliance; On the other hand, need to adopt addressing means in communication process, significantly to simplify the connected mode of control appliance and ancillary equipment.

In the prior art, industry generally acknowledges that HART agreement is the effective technology solution meeting above-mentioned requirements.HART agreement is a kind of agreement for solving communication issue between field intelligent instrument and control appliance that ROSEMOUNT company of the U.S. released in 1985, has become one of industrial standard of global intelligent instrument.At present, the Survey control mode being representative with 4 ~ 20mA electric current loop occupies dominant position in industrial automation, and will adopt the quite a long time.HART agreement, as the communication protocol of a kind of compatible tradition 4 ~ 20mA electric current loop, has vigorous vitality and wide market prospects.

HART agreement has following technical characterstic:

1. adopt based on FSK (frequency shift keying) signal of Bell202 standard, in 4 ~ 20mA analog signal of low frequency, superposition amplitude is that the audio digital signals of 0.5mA carries out bi-directional digital communication, and message transmission rate can be 1.2Mbps.Mean value due to fsk signal is 0, does not affect the analog signal size sending control appliance to, ensure that the compatibility with existing analogue system.

2. adopt semiduplex communication mode, existing transmission line analog signal realizes digital signal communication.HART agreement belongs to analogue system to the transitional product in digital system transition process, thus has the stronger market competitiveness in current transition period.But due to this analog and digital mixed signal system, cause being difficult to develop a kind of communication interface chip that can meet each companies ask.

3. adopt unified DDL DDL.Field apparatus developer adopts DDL language description field apparatus characteristic, and being responsible for these device descriptions of registration management by HART foundation and they are compiled is device description dictionary, and main equipment uses DDL language to understand the characterisitic parameter of field apparatus.

The core technology realizing HART agreement is modulator-demodulator, but special HART modulator-demodulator only has a few chip producer to supply, on the high side, and delivery cycle not easily ensures.On the other hand, single-chip microcomputer is as a kind of general-purpose device, through the fast development in nearly ten or twenty year, significant progress is achieved in high integration, high-performance, low-power consumption, low cost etc., after being particularly integrated with the analog peripheral such as ADC, DAC, comparator, coordinate typical timer, Μ SART, GPIO etc., a complete mini system can be realized on a single-chip microcomputer.If HART modulator-demodulator to be considered as a mini system, to select suitable single-chip microcomputer to realize this mini system, higher cost performance can be realized.

For this reason, the patent No. is that the Chinese invention patent of ZL 02160544.0 provides a kind of SCM Based modulator-demodulator and realizes the method for HART protocol signal transmission.This HART modulator-demodulator comprises a single-chip microcomputer, and is arranged on HART signal demodulation unit in this single-chip microcomputer, HART signal madulation unit and I/O output port register, asynchronous serial receiver module, a HART protocol signal link and resolves and command processor.Corresponding method comprises the following steps: be input to HART signal madulation unit from the pin of single-chip microcomputer after HART sine wave signal is first become frequency shift keying square wave by a. after bandpass filtering; B. after the demodulation of HART signal madulation unit output logic " 0 ", " 1 " signal to I/O output port register; C. by single-chip microcomputer pin, logical zero, " 1 " signal are input to asynchronous serial receiver module; D. asynchronous serial receiver module receives the HART communication frame through demodulation, deliver to HART protocol signal link again to resolve and command processor carries out link parsing and command process to communication frame, acquisition logical zero, " 1 " signal are delivered to signal madulation unit and are carried out signal madulation; E. after demodulation, producing frequency shift keying square wave export from the pin of single-chip microcomputer, transferring out by exporting HART sine wave signal after waveform shaping.

Summary of the invention

Primary technical problem to be solved by this invention is to provide a kind of HART modulator-demodulator.This HART modulator-demodulator, based on chip microcontroller, can solve the problems such as high expensive in prior art, supply channel be single.

Another technical problem to be solved by this invention is to provide the concrete grammar that above-mentioned HART modulator-demodulator realizes demodulation.

For realizing above-mentioned goal of the invention, the present invention adopts following technical scheme:

A kind of HART modulator-demodulator, comprise half-duplex control module, modulation module, demodulation module, parallel serial conversion module, serioparallel exchange module, receive data module, send data module, buffered/filtered/every straight module, cycle module, threshold module, filtering/biasing module, isolation module and input/output module; Wherein,

Described reception data module, described parallel serial conversion module and described modulation module are linked in sequence, and by gating switch and described buffered/filtered/be connected every straight module together with described half-duplex control module;

Described transmission data module, described serioparallel exchange module and described demodulation module are linked in sequence, described cycle module is connected with described demodulation module by described gating switch with described threshold module, and described filtering/biasing module connects described cycle module and described threshold module respectively;

Described isolation module on the one hand respectively with described buffered/filtered/is connected every straight module and described filtering/biasing module, another aspect connects described input/output module.

Wherein more preferably, described half-duplex control module, described modulation module, described demodulation module, described parallel serial conversion module, described serioparallel exchange module, described reception data module and described transmission data module are realized by the intrinsic module in single-chip microcomputer.

Wherein more preferably, described single-chip microcomputer is STM8L15x series monolithic.

Wherein more preferably, described modulation module is made up of digital to analog converter, direct memory access device and timer, and wherein said timer connects described direct memory access device, and described direct memory access device connects described digital to analog converter.

Wherein more preferably, after the sinusoidal array of described direct memory access device in traversal in-chip FLASH region, return the waveform that array beginning continues to generate next cycle.

Wherein more preferably, described demodulation module comprises monostable flipflop, pulse width timer, decision unit and demodulating algorithm submodule, and wherein threshold signal is through described monostable flipflop, forms the enable signal of described demodulating algorithm submodule; Periodic signal inputs in described pulse width timer, and is converted to symbol sebolic addressing after described decision unit process, enters described demodulating algorithm submodule and processes, final output 0/1 data slot.

Wherein more preferably, what described periodic signal connect timer in single-chip microcomputer catches pin, and described threshold signal connects the I/O pin of single-chip microcomputer, utilizes the PWM capturing function of timer in single-chip microcomputer to carry out pulsewidth timing to the high-low level time of described periodic signal.

Wherein more preferably, the outermost of described input/output module is provided with Transient Suppression Diode and resettable fuse.

HART modulator-demodulator realizes a method for demodulation, realizes, wherein in demodulation module, arrange demodulating algorithm submodule based on above-mentioned HART modulator-demodulator; The method comprises the steps:

In described demodulating algorithm submodule, whether enable signal is sent to subsequent cell as gate-control signal control character sequence, then the symbol not affecting subsequent treatment in symbol sebolic addressing is filtered out, simultaneously a trailing edge detecting unit in parallel, LS and the LMS sequence occurred in monitoring symbol sebolic addressing;

Symbol sebolic addressing after filtration and trailing edge detecting unit output signal are input to demodulating algorithm state machine jointly;

Described demodulating algorithm state machine adopts ping-pong buffers deal with data, and exporting effective symbol fragment, by decision unit, symbol fragment is converted to 0/1 data slot, is byte through serioparallel exchange module converts.

Wherein more preferably, described demodulating algorithm state machine comprises four kinds of states: idle, head confirms, receives and reprocessing;

When idle condition, wait for trailing edge signal; When trailing edge detecting unit provides trailing edge signal, enter an acknowledgement state;

Under head acknowledgement state, to confirm after trailing edge being the whether bit 0 of a complete code-element period, confirm successfully to enter accepting state, confirm unsuccessfully to return idle condition;

Accepting state safeguards a timer, restarts this timer when entering accepting state, receiving symbol data complete during this period of time, only when abnormal conditions being detected, directly returning idle condition;

Reprocessing state is entered, this reprocessing state-maintenance soft timer after described timer expiry; When receiving continuous data, reprocessing state issues existing trailing edge, crosses idle condition and enters an acknowledgement state, switches ping-pong buffers and notifier processes; When receiving the end of non-continuous data or continuous data, if described soft timer is overtime, returning idle condition, switching ping-pong buffers and notifier processes.

HART modulator-demodulator provided by the present invention can based on chip microcontroller, thus solves the problems such as high expensive in prior art, supply channel are single.The modulation module of this HART modulator-demodulator and demodulation module are through optimal design, and not only operational capability is comparatively strong, and are convenient to debugging, and the scope of application is wider.

Accompanying drawing explanation

Fig. 1 is the overall system diagram of HART modulator-demodulator provided by the present invention;

Fig. 2 is in HART modulator-demodulator, the theory of constitution block diagram of modulation module;

Fig. 3 is buffered/filtered/every the circuit theory schematic diagram of straight module;

Fig. 4 is the circuit theory schematic diagram of cycle module, threshold module and filtering/biasing module;

Fig. 5 is the operation principle schematic diagram of demodulation module;

Fig. 6 is the decision rule schematic diagram that cycle duration is reduced to symbol stream;

Fig. 7 is the decision rule schematic diagram that cycle duration is reduced to symbol stream;

Fig. 8 is the operation principle block diagram of demodulating algorithm submodule;

Fig. 9 is the working state schematic representation of demodulating algorithm state machine;

Figure 10 is the circuit theory diagrams of isolation module and input/output module.

Embodiment

Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.

In one embodiment of the invention, STM8L15x series monolithic is adopted to realize supporting the modulator-demodulator of HART agreement.STM8L15x series monolithic is 8 8-digit microcontrollers (MCU) that STMicw Electronics releases, built-in 12 DAC (digital to analog converter) in its sheet, with the DMA (direct memory access device) of circulation pattern and the timer (TIMER) as DMA time reference, modulation module can be formed.Certainly, adopt other to have the general single chip of similar functions, such as STM8L10x series or STM8L16x is serial can realize the present invention equally, just differing at this one illustrates.

Fig. 1 is the overall system diagram of HART modulator-demodulator provided by the present invention.This HART modulator-demodulator comprises the half-duplex control module (being called for short half-duplex control module) of RTS (request send)/automatically, modulation module, demodulation module, parallel serial conversion module, serioparallel exchange module, RXD (reception data) module, TXD (transmission data) module, buffered/filtered/every straight module, cycle module, threshold module, filtering/biasing module, isolation module and input/output module.Wherein, RTS/ automatic half-duplex control module, modulation module, demodulation module, parallel serial conversion module, serioparallel exchange module, RXD module, TXD module can be realized by the intrinsic module in STM8L15x series monolithic.Among this single-chip microcomputer, RXD module, parallel serial conversion module and modulation module are linked in sequence, and by gating switch and buffered/filtered/be connected every straight module together with RTS/ automatic half-duplex control module.This modulation module is made up of DAC, DMA and timer, and this is one of technical characterstic of the present invention.On the other hand, TXD module, serioparallel exchange module and demodulation module are linked in sequence, and cycle module is connected with above-mentioned demodulation module by gating switch with threshold module.Outside this single-chip microcomputer, filtering/biasing module connects cycle module and threshold module respectively.Isolation module on the one hand respectively with buffered/filtered/is connected every straight module and filtering/biasing module, another aspect connects above-mentioned input/output module.

Above-mentioned HART modulator-demodulator data link is operationally such: when modulating, after byte to be modulated enters single-chip microcomputer by the pin of RXD module, 0/1 code stream is obtained via parallel serial conversion module, the modulation module that DAC, DMA and timer are formed in single chip microcomputer, by sinusoidal wave for the Phase Continuation that code stream modulation becomes 1200Hz and 2200Hz, buffered/filtered again outside single chip microcomputer/wait process every straight, is loaded into foreign current ring by isolation module and input/output module; When carrying out demodulation, it is inner that carrier wave on foreign current ring enters HART modulator-demodulator via isolation module and input/output module, after the process such as filtering/biasing module, cycle module and threshold module, analog waveform is converted among digital waveform input single-chip microcomputer, again through zero passage detection demodulating algorithm, serioparallel exchange link, finally exported by the pin of the TXD module in single-chip microcomputer.

HART agreement is a kind of half-duplex protocol, and synchronization can only get one in both transmission and accepting state.In one embodiment of the invention, the half-duplex of HART modulator-demodulator controls to be realized by outside RTS module pin, also can be realized automatically controlling by house software.Such as HART modulator-demodulator can be set to manual mode, half-duplex control is carried out by the RTS module pin of UART, also can changing to automatic mode by house software, only switching to modulating mode when there being data, At All Other Times equal auto-returned demodulation modes.

Before address, the modulation module in the present invention is made up of DAC, DMA and timer.Fig. 2 is the theory of constitution block diagram of this modulation module, and wherein timer connects DMA, DMA and connects DAC.In one embodiment of the invention, 12 DAC, DMA and timer be STM8L15x series monolithic sheet in peripheral hardware, all modulation operation all complete in single-chip microcomputer inside, using DAC modulating output pin as the output of modulation module.In modulation link, first byte to be modulated is received by the UART peripheral hardware receiving unit (being generally the pin of RXD module) of single-chip microcomputer in the mode of interrupting, then parallel serial conversion module is passed through, forming 0/1 code stream according to information such as the baud rate of specifying, parity checks (is 1200 baud rates in HART agreement, odd), and jointly complete modulated process by DAC, DMA of single-chip microcomputer inside and timer, wherein 0 in code stream is modulated into 2200Hz, and 1 is modulated to 1200Hz.

In STM8L15x series monolithic, the conversion speed of DAC is 1 μ s ~ 10 μ s magnitude, uses DMA in sheet can increase substantially the access efficiency established inside and outside this such sheets.In addition, in this sheet, DMA supports circulation pattern, can after the sinusoidal array of traversal, and the beginning of auto-returned array continues the waveform generating next cycle.Like this, not only do not need kernel intervention in the monophasic waveform cycle, and the generation of whole continuous wave does not need kernel intervention.Because the interrupt response processing speed of kernel is often also in μ s magnitude, so this characteristic ensure that the continuity that sinusoidal waveform generates and flatness.

In the modulation module shown in Fig. 2, sine table is 12 read-only arrays in in-chip FLASH region, for exporting sinusoidal array to DMA to realize producing sine-shaped function.By arranging DMA, directly the digital quantity in sinusoidal array equally spaced can be input in DAC, and form analog sine waveforms at the output of DAC.Obviously, larger sinusoidal array is conducive to the step effect reducing DAC sine wave output, but the speed of DMA moving data can not more than the conversion speed of DAC.Under this prerequisite, the cycle of DMA moving data determines the frequency of sine wave output.In STM8L15x series monolithic, timer is for the cycle of control DMA moving data.When runs is at cyclic pattern, in order to export the analog sine waveforms of 1200Hz and 2200Hz, calculated in advance can go out the register parameters of the timer as DMA time reference, the register parameters of switching timer, the analog sine waveforms that can realize 1200Hz and 2200Hz exports.

HART agreement adopts Bell202 modulation demodulation system, and an important feature of modulation is the continuity of waveform, namely requires that code-element period initial phase is equal with last code-element period end phase place.2200Hz logical zero export time, code-element period and wave period inconsistent because the existence of this inconsistency, specific to certain code-element period, first phase is not the value determined, but depends on previous code-element period.Utilize the modulation module implementation shown in Fig. 2, when switching when between code element, only need the register parameters upgrading timer, any operation is not done to DMA and DAC, DMA is still by sinusoidal array next continuous print data importing DAC, form continuous print output level, thus meet the requirement of HART agreement to waveform continuity.

Modulation module in the present invention, except having 0/1 data flow input port, also has the enable port controlled for realizing half-duplex.This enable port directly acts on DAC and output pin thereof.When HART modulator-demodulator is in Signal reception state, the output pin of DAC is high-impedance state, is conducive to the detection of input signal.In order to improve the accuracy that waveform receives, before and after formal 0/1 data flow, respectively can produce one section of default 1200Hz logical one (high level).

In modulation module provided by the present invention, DAC has optional sheet internal inner ring (Buffer), operating current due to its sheet internal inner ring is obviously greater than the low-power consumption amplifier outside sheet, when modulation module has special requirement to low-power consumption, time such as HART modulator-demodulator, sheet internal inner ring should be forbidden and adopt the low-power consumption amplifier outside sheet as far as possible.In addition, the step effect etc. reducing dominant frequency, shorten sinusoidal data, suitably increase output waveform is also the important technique measure reducing modulation module overall power.

The waveform that modulation generates is sent through DAC output pin, is amplitude sinusoidal signal with " alias " between 0 to reference voltage, and when forbidding sheet internal inner ring, the driving force of waveform is very weak.From the angle of frequency spectrum, signal, except 1200Hz and 2200Hz needed, also has the high fdrequency component of DC component and generation " alias ".This signal, through buffered/filtered/every straight resume module, obtains modulating rear output.

Fig. 3 is buffered/filtered/every the circuit theory schematic diagram of straight module.This buffered/filtered/comprise main the first voltage follower playing cushioning effect every straight module, the second voltage follower mainly strobed and the electric capacity play every straight effect, wherein the positive input of the first voltage follower connects the output of modulation module, the output of the first voltage follower connects the positive input of the second voltage follower after RC filter circuit, and the output of the second voltage follower has connected electric capacity every straight effect and isolating transformer.This buffered/filtered/every the operation principle of straight module be such: consider that in modulation module, the output impedance of DAC is higher, first realize buffering by the first voltage follower, improve driving force and reduce the distortion of waveform.Step effect in DAC output waveform can be considered the high-frequency noise in frequency spectrum, RC filter circuit and the second voltage follower subsequently form first-order low-pass wave circuit, due to the high-frequency noise of step effect and the frequency phase-difference of sine wave itself very far away, first-order filtering also can play good filter effect, obtains level and smooth sinusoidal waveform.In single-chip microcomputer, what DAC received is that scope is 0 ~ 4095 without character type 12 integers.Sinusoidal array is with 2047 for oscillation center, and waveform always after this is the sinusoidal waveform with direct current biasing, therefore in buffered/filtered/before straight module end, isolating transformer, cuts off its flip-flop with an electric capacity.Although this circuit design is because isolating transformer also has every straight effect, but electric capacity passes through isolating transformer every directly avoiding flip-flop, Loss reducing to raise the efficiency, and avoids the saturated of isolating transformer magnetic core, improves the transmission performance of isolating transformer.

In demodulation link, the analog signal first sent here by isolation module is carried out filtering and is biased.Filtering is to reduce high-frequency noise, and biased is to provide a flip-flop to through the signal of transformer after straight, signal amplitude being controlled within the scope of the significant level of SCM peripheral circuit.Through cycle module and threshold module process, amplitude information, these two information of obtaining the zero passage cycle information of signal waveform and signal waveform are all digital quantities, send into single-chip microcomputer process by I/O mouth.

Fig. 4 is the circuit theory diagrams of cycle module, threshold module and filtering/biasing module.In filtering/biasing module, the AC signal from isolating transformer enters first order homophase and amplifies discharge circuit after a RC filter circuit.This amplifier is single supply op, interval in order to AC signal be controlled at the significant level of amplifier, adds the 100K resistance that one is connected to Vref, add a capacitance before after RC filter circuit.Vref can get the half of VCC voltage or be slightly less than half (this is the technical characteristic of single supply op), such as, when 5V powers, and the desirable 2 ~ 2.5V of Vref.The 100K resistance of aforementioned increase and capacitance provide biased for the pure AC signal of input, ensure that the normal work of first order in-phase amplification circuit.The gain of first order in-phase amplification circuit is determined by the ratio of a pair resistance in below, usually only needs to get 1 ~ 4 times.

As shown in Figure 4, the waveform after the process of first order in-phase amplification circuit, then through the straight bias treatment of a septum secundum, enter two comparators below.Direct and the bias level Vref of the cycle comparator (i.e. cycle module) of top compares, and now amplifier is in operate in open loop state state, sinusoidal waveform can be processed into synchronous square wave of same cycle.So far, analog signal becomes 0/1 digital signal that a road is loaded with input waveform cycle information, and common I/O pin or the timer capture pin that can send into single-chip microcomputer carry out subsequent treatment.The threshold compataror (i.e. threshold module) of below compares with a reference level a little less than Vref, when there is no Waveform Input or wave-shape amplitude is not enough, threshold compataror exports the high level continued, only have when input waveform amplitude is greater than certain thresholding, threshold compataror just can export a series of low level.This threshold value can adjust by changing divider resistance value.This series of low level or trailing edge being loaded with input waveform amplitude information, the common I/O pin can sending into single-chip microcomputer carries out subsequent treatment.

Figure 5 shows that the operation principle schematic diagram of demodulation module.This demodulation module comprises monostable flipflop, pulse width timer, decision unit and demodulating algorithm submodule, and wherein threshold signal is through a monostable flipflop, forms the enable signal of demodulating algorithm submodule; In periodic signal input pulse width timer, and after decision unit process, be converted to symbol stream (i.e. symbol sebolic addressing), enter demodulating algorithm submodule and process, effective 0/1 data slot of final output.The time delay of monostable flipflop is 1 ~ 4 code-element period, is triggered by low level, that is only has the enough large waveform of amplitude just to perform demodulating algorithm.This point is consistent with the regulation of HART agreement.

In one embodiment of the invention, what periodic signal connect timer in single-chip microcomputer catches pin, threshold signal connects the common I/O pin of single-chip microcomputer, utilizes the PWM capturing function of timer in STM8L15x series monolithic to carry out pulsewidth timing to the high-low level time of periodic signal.Timer capture function does not need the intervention of kernel, has nothing to do, do not need the operations such as interrupt response, there is not the problems such as interrupt nesting, can be as accurate as the single clock cycle, can obtain the precision higher than the timing of IO interruption+timer with the program of current execution.

The pulsewidth that timer obtains is the duration at adjacent two edges, comprises rising edge and trailing edge, is generally the numerical value of 16 bits.For this 8 single-chip microcomputers of STM8L15x, subsequent treatment is relatively complicated.In order to simplify subsequent treatment, through a decision unit in the present invention, convert 16 bit duration informations to a symbol stream.As shown in Figure 6, due to corresponding two pulsewidths of a sinusoidal cycles, ideally the pulsewidth of 1200Hz and 2200Hz should be 0.5 × 1200Hz to concrete transformation rule ^-1with 0.5 × 2200Hz ^-1these two pulsewidths symbol L (Long) and S (Short) represent, consider the shake that the input imbalance of the uncertainty of initial phase, comparator and noise cause, symbol L and S allows the error of certain limit, as shown in dash area in Fig. 6.

Initial phase is uncertain also can cause larger change, as in Fig. 7,2200Hz bit 0 first phase is 3/2 π, now being positioned at middle pulsewidth is just the intermediate value of L and S, be judged to be that bit 0 and bit 1 respectively account for half more suitable, here represent, as the blank parts in Fig. 6 between L and S by symbol M (Middle).Region lower than symbol S is judged to U (Under), and when this situation is generally comparator upset, the shake that the remaining high-frequency noise of filtering causes, much smaller than the pulsewidth that symbol S represents.Region higher than symbol L is judged as O (Over), and this situation is generally that wiring or amplitude instability cause waveform localized loss, forms time-out.

Demodulating algorithm submodule is the core component of demodulation module, for receiving the symbol sebolic addressing from decision unit, exports effective 0/1 data slot.In UART agreement, the idle condition of countless certificate is equivalent to also have quite a few time to be in this state of complete 1 in complete 1, HART modulator-demodulator, and demodulating algorithm submodule is regarded as invalid data.Again according to UART agreement, the starting character of data is the low level of 1 code-element period, and can think that valid data must be guided by trailing edge, demodulating algorithm submodule only exports this effective data slot.

The wave period information of acquisition and amplitude information are sent into demodulating algorithm submodule and are carried out solution mediation judgement by single-chip microcomputer, obtain effective 0/1 code stream.Shown in Figure 2, these code streams are become byte by certain compatible rule merging by serioparallel exchange module, carry out parity check simultaneously.If there are the mistakes such as verification mistake to occur, output error information, the byte after correct serioparallel exchange, is sent by the UART peripheral hardware transmitting portion (being generally the pin of TXD module) of single-chip microcomputer.

The operation principle block diagram of demodulating algorithm submodule as shown in Figure 8, whether enable signal is sent to subsequent cell as gate-control signal control character sequence, then (symbol U is generally caused by shake during comparator zero passage to filter out the U not affecting subsequent treatment in symbol sebolic addressing, sequence judgement is not affected) after filtration, a trailing edge detecting unit in parallel simultaneously, " LS " and " LMS " that occur in monitoring symbol sebolic addressing, if there is then providing trailing edge signal.Symbol sebolic addressing after filtration and trailing edge detecting unit output signal are input to demodulating algorithm state machine jointly.

Demodulating algorithm state machine, in units of byte, not only exports and has certain time delay, and need to take a buffering area during process.Therefore, demodulating algorithm state machine adopts ping-pong buffers (Buffer) to carry out deal with data.Ping-pong buffers is by input data selection and export data selection, by beat, co-operatively switch, data flow through buffering is delivered to follow-up decision unit without a break and carried out computing and process, and when effectively can solve continuous data, data forward lap, receive and the problem such as subsequent treatment is parallel.The valid data fragment that demodulating algorithm state machine detects, be still symbol fragment when being exported by ping-pong buffers, symbol fragment is converted to 0/1 data slot by decision unit subsequently, is byte through serioparallel exchange module converts.The sequence that demodulating algorithm state machine exports only is made up of S, M, L, and M must appear between L and S, and the switching criterion of decision unit is as follows:

● meet the direct switching of L and S, or through the switching of M, be symbol interval mark, as interval, symbol fragment be divided into subsegment, and add up the number of continuous symbol;

● when adding up the number of continuous print L and S, M is converted to 1/2 L and 1/2 S, as shown in Figure 7, obtains, entirely by L or the complete two class subsegments be made up of S, might as well becoming L subsegment and S subsegment;

● for L subsegment, if symbol L number is X, be then converted to X/2 continuous print 1;

● for S subsegment, if symbol S number is Y, be then converted to Y/3.667 continuous print 0, wherein 3.667=2*2200Hz/1200Hz;

Fig. 9 is the schematic diagram of demodulating algorithm state machine, and it has four kinds of states: idle, head confirms, receives and reprocessing.When idle condition, wait for trailing edge; When trailing edge detecting unit provides trailing edge signal, enter data head acknowledgement state.In this condition, to confirm after trailing edge being the whether bit 0 of a complete code-element period, confirm successfully to enter data receiving state, confirm unsuccessfully to return idle condition.

Accepting state safeguards a soft timer, and timer duration is the duration of a byte in HART agreement.Restart timer when entering accepting state, receiving symbol data complete during this period of time, only when the abnormal conditions such as symbol O being detected, directly returning idle condition.

Enter reprocessing state after receiving timer expiry, this state-maintenance duration is the soft timer of several code-element period.When receiving continuous data, an and then trailing edge point out the beginning of next data after the position of rest of 1 or 2 bit, i.e. reprocessing state issues existing trailing edge, crosses idle condition and enters an acknowledgement state, switches ping-pong buffers and notifier processes.When receiving the end of non-continuous data or continuous data, reprocessing soft timer time-out, returns idle condition, switches ping-pong buffers and notifier processes.

In HART agreement, main variable and control information are by the transmission of 4 ~ 20mA electric current loop.As HART modulator-demodulator, needs can jump in 4 ~ 20mA electric current loop, carry out carrier communication when not affecting electric current loop.Therefore, after modulation exports, isolation module and input/output module is added.Wherein, isolation module is formed primarily of audio frequency transformer, and input/output module is made up of TVS (Transient Suppression Diode), resettable fuse etc., mainly plays a protective role.Isolation module and input/output module are two-way modules, and sinusoidal signal to be demodulated also returns from this link.

Figure 10 is the circuit theory diagrams of isolation module and input/output module in HART modulator-demodulator, and its core is an isolating transformer and a capacitance.Because 1200Hz and 2200Hz is all in the stage casing of audio frequency, isolating transformer can adopt 600:600 audio frequency transformer common on the market, and this transformer turn is many, wire diameter thin, and patch-type can be selected to reduce volume.The alternating component of modulation /demodulation is only connected with 4 ~ 20mA current loop for guaranteeing by capacitance, does not affect the direct current signal of electric current loop.This capacitance can not be polar capacitor, is employed herein common 0.1u patch capacitor, is withstand voltagely generally more than 36V.

For the consideration of electromagnetic compatibility and fail safe, input/output interface outermost adds TVS (Transient Suppression Diode) and resettable fuse.Consider a large amount of 24V DC power supply used, the withstand voltage desirable 36V of TVS, do not affect normal use and can capacitance be protected.Resettable fuse can guarantee that together with TVS the large voltage high-current that surge or misoperation cause enters input/output module, and protective separation transformer is not burnt.

Above SCM Based HART modulator-demodulator provided by the present invention and its implementation are described in detail.For one of ordinary skill in the art, to any apparent change that it does under the prerequisite not deviating from connotation of the present invention, all by formation to infringement of patent right of the present invention, corresponding legal liabilities will be born.

Claims (9)

1. a HART modulator-demodulator, it is characterized in that comprising half-duplex control module, modulation module, demodulation module, parallel serial conversion module, serioparallel exchange module, receive data module, send data module, buffered/filtered/every straight module, cycle module, threshold module, filtering/biasing module, isolation module and input/output module; Wherein,

Described reception data module, described parallel serial conversion module and described modulation module are linked in sequence, and by gating switch and described buffered/filtered/be connected every straight module together with described half-duplex control module;

Described transmission data module, described serioparallel exchange module and described demodulation module are linked in sequence, described cycle module is connected with described demodulation module by described gating switch with described threshold module, and described filtering/biasing module connects described cycle module and described threshold module respectively;

Described isolation module on the one hand respectively with described buffered/filtered/is connected every straight module and described filtering/biasing module, another aspect connects described input/output module;

Described buffered/filtered/the first voltage follower having comprised cushioning effect every straight module, the second voltage follower strobed and the electric capacity play every straight effect, the positive input of wherein said first voltage follower connects the output of described modulation module, the positive input of the second voltage follower described in the output termination of described first voltage follower, the output of described second voltage follower has connected electric capacity every straight effect and isolating transformer;

In described filtering/biasing module, AC signal from described isolating transformer enters first order in-phase amplification circuit after RC filter circuit, waveform after the process of first order in-phase amplification circuit passes through every straight bias treatment again, enters in described cycle module and described threshold module; Wherein, described cycle module and bias level compare, sinusoidal waveform to be processed into synchronous square wave of same cycle; Described threshold module compares with the reference level a little less than described bias level, when there is no Waveform Input or wave-shape amplitude is not enough, described threshold module exports high level, when input waveform amplitude is greater than described reference level, and described threshold module output low level.

2. HART modulator-demodulator as claimed in claim 1, is characterized in that:

Described half-duplex control module, described modulation module, described demodulation module, described parallel serial conversion module, described serioparallel exchange module, described reception data module and described transmission data module are realized by the intrinsic module in single-chip microcomputer.

3. HART modulator-demodulator as claimed in claim 2, is characterized in that:

Described single-chip microcomputer is STM8L15x series monolithic.

4., as the HART modulator-demodulator in claims 1 to 3 as described in any one, it is characterized in that:

Described modulation module is made up of digital to analog converter, direct memory access device and timer, and wherein said timer connects described direct memory access device, and described direct memory access device connects described digital to analog converter.

5. HART modulator-demodulator as claimed in claim 4, is characterized in that:

After the sinusoidal array of described direct memory access device in traversal in-chip FLASH region, return the waveform that array beginning continues to generate next cycle.

6., as the HART modulator-demodulator in claims 1 to 3 as described in any one, it is characterized in that:

Described demodulation module comprises monostable flipflop, pulse width timer, decision unit and demodulating algorithm submodule, and wherein threshold signal is through described monostable flipflop, forms the enable signal of described demodulating algorithm submodule; Periodic signal inputs in described pulse width timer, and is converted to symbol sebolic addressing after described decision unit process, enters described demodulating algorithm submodule and processes, final output 0/1 data slot.

7. HART modulator-demodulator as claimed in claim 6, is characterized in that:

What described periodic signal connect timer in single-chip microcomputer catches pin, and described threshold signal connects the I/O pin of single-chip microcomputer, utilizes the PWM capturing function of timer in single-chip microcomputer to carry out pulsewidth timing to the high-low level time of described periodic signal.

8., as the HART modulator-demodulator in claims 1 to 3 as described in any one, it is characterized in that:

The outermost of described input/output module is provided with Transient Suppression Diode and resettable fuse.

9. HART modulator-demodulator realizes a method for demodulation, realizes, wherein in demodulation module, arrange demodulating algorithm submodule based on HART modulator-demodulator as claimed in claim 1; It is characterized in that:

In described demodulating algorithm submodule, whether enable signal is sent to subsequent cell as gate-control signal control character sequence, then the symbol not affecting subsequent treatment in symbol sebolic addressing is filtered out, a trailing edge detecting unit in parallel simultaneously, the LS sequence occurred in monitoring symbol sebolic addressing and LMS sequence;

Symbol sebolic addressing after filtration and trailing edge detecting unit output signal are input to demodulating algorithm state machine jointly;

Described demodulating algorithm state machine adopts ping-pong buffers deal with data, and exporting effective symbol fragment, by decision unit, symbol fragment is converted to 0/1 data slot, is byte through serioparallel exchange module converts; Wherein,

Described demodulating algorithm state machine comprises four kinds of states: idle, head confirms, receives and reprocessing:

When idle condition, wait for trailing edge signal; When trailing edge detecting unit provides trailing edge signal, enter an acknowledgement state;

Under head acknowledgement state, to confirm after trailing edge being the whether bit 0 of a complete code-element period, confirm successfully to enter accepting state, confirm unsuccessfully to return idle condition;

Accepting state safeguards a timer, restarts this timer when entering accepting state, receiving symbol data complete during this period of time, only when abnormal conditions being detected, directly returning idle condition;

Reprocessing state is entered, this reprocessing state-maintenance soft timer after described timer expiry; When receiving continuous data, reprocessing state issues existing trailing edge, crosses idle condition and enters an acknowledgement state, switches ping-pong buffers and notifier processes; When receiving the end of non-continuous data or continuous data, if described soft timer is overtime, returning idle condition, switching ping-pong buffers and notifier processes.