CN202513866U

CN202513866U - Motion controller for stepper motor

Info

Publication number: CN202513866U
Application number: CN 201220176339
Authority: CN
Inventors: 廖高华
Original assignee: Nanchang Institute of Technology
Current assignee: Nanchang Institute of Technology
Priority date: 2012-04-24
Filing date: 2012-04-24
Publication date: 2012-10-31
Anticipated expiration: 2022-04-24

Abstract

A motion controller for a stepper motor is characterized by comprising a storer in electric connection with a high-speed singlechip W77E58, a signal processing circuit, a human-machine interface module, a watchdog circuit, a communication circuit, a serial communication interface and an FPGA (field programmable gate array) module, wherein the storer is solidified with a control algorithm program and forms an upper and lower machine control structure with a computer; and communication between an upper machine and a lower machine is EPP (enhanced parallel port) protocol communication. The motion controller for the stepper motor takes a VHDL (hardware description language) as a design tool and a programmable logic device as a carrier and can revise output pulse parameters according to an application occasion at any time to realize pulse distribution; the enhanced parallel port (EPP) communication way is an efficient real-time communication mode and is greatly improved in aspects of speed and reliability of data transmission, simplicity of a hardware circuit and the like; hardware and software are modularized, so that the motion controller for the stepper motor is flexible in control and high in integration; the volume is reduced; the development cost is lowered; and the running effect of a stepper motor system is effectively improved.

Description

Stepper motor movement controller

Technical field

The utility model relates to electric equipment, particularly stepper motor movement controller.

Background technology

The rotating speed of stepping motor and the angle of being rotated are determined that by the speed and the overall pulse number of input pulse its anglec of rotation error can progressively not accumulated.In reality, often need to regulate the rotary speed or the stepping amount of stepping motor, promptly need the pulse generator that accurately to set pulse rate and pulse sum.Main controller output signal is through the control and the interpolation operation of a series of complicacies such as pulse generator completion stepping motor position, rotating, up-down, reduction of speed control.The design of pulse generator and interpolation operation can and adopt the method for dedicated logic circuit to realize through single-chip microcomputer; But adopt chip microcontroller to receive the restriction of its clock frequency; Realize low, the poor anti jamming capability of precision, be difficult to realize the pulse signal of non-integer clock cycle.

Summary of the invention

The purpose of the utility model provides the high stepper motor movement controller of a kind of cost performance; With enhancement mode LPT (EPP) is communication interface; FPGA realizes pulse signal generator; High-speed microprocessor is a main controller, utilizes computer resource, realize stepping pulse signal continuously, stablely can be in harmonious proportion the interlock interpolation.When controller was used for tracking Control, accurate positioning was reliable in real time, and man-machine interface is convenient, has good adaptability and self-shield ability.

The technical scheme of the utility model stepper motor movement controller is following: it comprises memory, signal processing circuit, human-computer interface module, watchdog circuit, telecommunication circuit and parallel communication interface (EPP), field programmable gate array (FPGA) module that is connected with high-speed microprocessor W77E58 circuit; Said memory is solidified with the program of control algolithm; Constitute the upper and lower computer control structure with computer, upper and lower computer communication is to connect through the EPP protocol communication.The utility model is responsible for motion control, can export step-by-step impulse and direction signal, with the running of control motor; Simultaneously can external limit signal, control system is to external input and make handled,, adopt open, the modularized design of software and hardware.

It is design means that the utility model controllor for step-by-step motor adopts VHDL, and programmable logic device is a carrier, can revise the output pulse parameter according to the application scenario at any time, realizes pulse distribution.The mode of enhancement mode LPT EPP communication is a kind of high-efficiency real-time communication pattern, all has greatly improved at the aspects such as simplicity of data transmission bauds, reliability, hardware circuit; Software and hardware adopts modular design, and control is flexible, and integrated level is high, and controller has reduced volume, reduced development cost, improves the operational effect of step motor system effectively.

Description of drawings

Fig. 1 is the utility model electric machine control system figure.

Fig. 2 is the utility model boosting velocity procedure figure.

Fig. 3 is the utility model communication interface circuit.

Fig. 4 is the utility model display keyboard interface circuit.

Embodiment

Below in conjunction with accompanying drawing the utility model is further described:

A kind of stepper motor movement controller; It is characterized in that: it comprises memory, signal processing circuit, human-computer interface module, watchdog circuit, telecommunication circuit and parallel communication interface, the FPGA module that is connected with high-speed microprocessor W77E58 circuit; Said memory is solidified with the program of control algolithm; Constitute the upper and lower computer control structure with computer, upper and lower computer communication is to connect through the EPP protocol communication.

The utility model FPGA digital module, the internal timing/counter that is designed by FPGA constitutes, and the timing value of Timer and timing range can be by software set and changes.After configuring the working method of timer and the numerical value of packing into, it just can be worked, and does not take the plenty of time, and easy to use, function is stronger.After internal timing/counter startup, timer begins the system machine cycle is added counting from the initial value that loads, and when the count value generation was overflowed, timer produced interrupt signal, ends the execution of main program, and system transfers execution timer interruption subroutine to.The motor commutation subprogram is placed in the timer interrupt service routine, and then timer interrupts once, and motor just commutates once, thereby realizes SPEED CONTROL OF MOTOR.

Up-down degree module; Adopt trapezoidal rate curve, in the control procedure of carrying out speed, go out these motion needs according to the condition judgment that oneself knows through several stages; Just can obtain the used period of each section then; According to this time be Rule of judgment, for program provides the translational speed in each cycle, and the amount of feeding in each cycle.In the process of the up-down speed of controlling motor, adopt discrete way to approach desirable up-down speed curve.Calculate the loading time in order to reduce per step; Be solidificated in the required loading value of the speed of each discrete point in the memory during system design; Be in operation and find required loading value, thereby reduce the time that takies significantly, improved the response speed of system with look-up method.Time, was more little; Raising speed is fast more, otherwise gradually slow.The big I of is confirmed by theory analysis or experiment; The fastest and don't to lose the step be principle with raising speed; The step number of then every step operation is

,

reflected that each velocity step moves the relation between step number and the speed s.Program in the process of implementation; Each speed rises one grade; All to calculate the step number that this step should be walked, check with the mode of successively decreasing then, represent that when reducing to zero the operation of this grade speed finishes;

rises up into another shelves speed.The rule of reduction of speed process is identical with boosting velocity procedure, and process is undertaken by opposite order.Boosting velocity procedure such as Fig. 2.

The utility model main circuit module comprises telecommunication circuit, human-computer interface module, the single-ended modular converter of difference.

Telecommunication circuit can be designed the various interface application circuit through the EPP LPT, and the EPP agreement is that a kind of and spp are compatible and can accomplish the agreement of bidirectional data transfers, can realize the asymmetric bidirectional data transfers of host driven.Because its used holding wire is limited, must be divided into two cycles to the transmission of data.In design, adopted data select lines, address strobe line, write signal line have been made up the method for decoding, realized the read-write control signal of controller, interface circuit such as Fig. 3.

Decoding circuit U11 (74LS138) is subdivided into data/address read write signal address and data is read or write the gating control signal.Write address gating (WA); Write data gating (WD); Read address strobe (RA); Read data strobe (RDS) (RD).Go reading or writing of control data with control signal.Through WA, WD is that the NAND gate (U10) of input produces the DIR end that the output signal removes to control U1 (74LS245), as long as WA, WD one of them effectively (low level), then NAND gate is output as high level, U1 gating then, thereby the data of writing or address.Equally, reading in of data then is that the instruction of sending through program produces the RD negative pulse and comes gating U1, and with data read to the EPP mouth.Therefore transmission needs four instructions to accomplish, a selection that is used for read/write address, and another is used for the data read/write of appropriate address.It is the expanded circuit of core that slave computer has been selected for use with U2 (8255), and U2 is operated in mode 2.The A mouth is that mode can be carried out input-output operation 2 times, as the port of the next single-chip microcomputer and computer transmission transfer of data.

Human-computer interface module in controller, needs to realize the demonstration of various functions, and device adopts the large-size screen monitors dot-matrix lcd module to realize.512K bytes of memory device has been used in MCU operation for ease, is used for 16 X, 16 dot matrix Chinese character character libraries that storage system needs, interface display Background etc.In fact SED1335 control system that LCD is built-in becomes the process of the SED1335 control system being carried out interface communication to the control of LCD, and simplified system is to the control of liquid crystal display.Be provided with a plurality of function keys in the system, keyboard adopts matrix form to arrange, and button is arranged on the determinant intersection point, can realize human-computer dialogue through keyboard, to apparatus system input relevant parameter and control command.Circuit is as shown in Figure 4.

The conversion chip that the single-ended conversion designs of difference is used is the AM26LS32ACD (it is single-ended that difference is changeed) and the AM26LS31ACD (single-ended transfer difference) of TI company.This two chip is formed by four groups of modular converters, and code device signal is a differential signal from the signal of driver output, and the signal that outputs to driver from FPGA simultaneously also need convert differential signal to, could the operation of enter drive control motor.The former is the differential signal of encoder output for example, and the latter is pulse control signal for example.Utilize the difference method transmission signals that high common-mode rejection ratio is arranged, antijamming capability is strong, can guarantee the integrality of signal, improves transmission speed.Can satisfy the conversion of four groups of signals simultaneously, like Fig. 5, resistance wherein uses to such an extent that main purpose is to realize level match.Because the supply power voltage of chip is 5V, so and the FPGA signal voltage value is a 3.3V needs realization level match.Between FPGA and conversion chip, adding resistance and impact in order to prevent super-high-current, burn chip, is in order to realize the coupling between output voltage and the chip voltage and be provided with pull-up resistor, guarantees that signal accurately exports.

The utility model has 16 road input switch amounts, and 8 tunnel output switching values also have 1 tunnel warning input simultaneously, wherein, utilizes the abundant I/O resource of FPGA to manage input/output signal.Adopt the method input amount of light-coupled isolation, the light lotus root can be transmitted switching information between the switching value of varying level.The input impedance of optocoupler is little, can be good at suppressing instantaneous high pressure and disturbs, the protection internal circuit.The switching value input signal of control card (comprising spacing, deceleration, initial point, external alert) can be a contact type switch, also can be that the transducer of NPN output is near switch etc.The circuit that optocoupler connects is as shown in Figure 6, and wherein the I/O of FPGA is 3.3V, and external interface is 12V-24V.The general output loop of the switching value of controller is open collector output, may command relay, photoelectrical coupler etc., single channel maximum output current 500mA, voltage 24V, auxiliary relay or the photoelectrical coupler of driving 24DCV.

Claims

1. stepper motor movement controller; It is characterized in that: it comprises memory, signal processing circuit, human-computer interface module, watchdog circuit, telecommunication circuit and parallel communication interface, the FPGA module that is connected with high-speed microprocessor W77E58 circuit; Said memory is solidified with the program of control algolithm; Constitute the upper and lower computer control structure with computer, upper and lower computer communication is to connect through the EPP protocol communication.

2. stepper motor movement controller according to claim 1 is characterized in that: said FPGA digital module is made up of the internal timing/counter of FPGA design, and is solidificated in the required loading value of the speed of each discrete point in the memory.

3. stepper motor movement controller according to claim 1, it is characterized in that: telecommunication circuit is the application circuit through the EPP LPT.

4. stepper motor movement controller according to claim 1; It is characterized in that: said human-computer interface module, adopt the large-size screen monitors dot-matrix lcd module to realize, used 512K bytes of memory device; Be provided with a plurality of function keys, keyboard adopts matrix form to arrange.

5. stepper motor movement controller according to claim 1 is characterized in that: be provided with 16 road input switch amounts, 8 tunnel output switching values; Also have 1 tunnel warning input simultaneously, wherein the I/O of FPGA is 3.3V, and external interface is 12V-24V; The general output loop of the switching value of controller is open collector output, may command relay, photoelectrical coupler etc., single channel maximum output current 500mA; Voltage 24V, auxiliary relay or the photoelectrical coupler of driving 24DCV.