CN102833201A - Highway addressable remote transducer (HART) modem based on singlechip, and implementation method thereof - Google Patents

Abstract

The invention discloses a highway addressable remote transducer (HART) modem and an implementation method of the HART modem. According to the HART modem, a data receiving module, a parallel to series conversion module and a modulation module are sequentially connected with one another and are connected with a buffering or filtration or blocking module through a first gating switch together with a half duplex control module; a data sending module, a series to parallel conversion module and a demodulation module are sequentially connected with one another; a period module and a threshold module are connected with the demodulation module through a second gating switch; a filtration or biasing module is respectively connected with the period module and the threshold module; and an isolation module is respectively connected with the buffering or filtration or blocking module and the filtration or biasing module and then connected with an input/output module. The HART modem can be implemented based on a singlechip, so that the problems of relatively high cost, single commodity supply way and the like in the prior art are solved.

Description

SCM Based HART modulator-demodulator and its implementation

Technical field

The present invention relates to a kind of based on chip microcontroller, can support HART (Highway Addressable Remote Transducer; Highway addressable remote transducer) modulator-demodulator of agreement; Also relate to simultaneously this HART modulator-demodulator and realize the method for demodulation, belong to the industrial automation technical field.

Background technology

Fast development along with industrial automation; PLC (Programmable Logic Controller; Programmable logic controller (PLC)), DCS automatic control equipments such as (Distributed Control System, dcss) obtains large-scale application in industry spot.This communication support ability to industry spot has proposed increasingly high requirement.On the one hand, in the industry spot be that the ancillary equipment of representative need communicate with control appliance whenever and wherever possible with the transmitter; On the other hand, in communication process, need to adopt the addressing means, so that simplify the connected mode of control appliance and ancillary equipment significantly.

In the prior art, industry generally acknowledges that the HART agreement is to satisfy the effective technology solution of above-mentioned requirements.The HART agreement is a kind of agreement that is used to solve communication issue between field intelligent instrument and the control appliance that U.S. ROSEMOUNT company released in 1985, has become one of industrial standard of global intelligence instrument.At present, be that the measurement control mode of representative occupies dominant position in the industrial automation field with 4～20mA electric current loop, and will prolong and use the quite a long time.The HART agreement has vigorous vitality and vast market prospect as a kind of communication protocol of compatible tradition 4～20mA electric current loop.

The HART agreement has following technical characterstic:

1. adopt FSK (frequency shift keying) signal based on the Bell202 standard, the stack amplitude is that the audio digital signals of 0.5mA carries out bi-directional digital communication on 4～20mA of low frequency analog signal, and message transmission rate can be 1.2Mbps.Because the mean value of fsk signal is 0, do not influence the analog signal size that sends control appliance to, guaranteed compatibility with existing analogue system.

2. employing half-duplex communication mode realizes digital signal communication on existing transmission line analog signal.The HART agreement belongs to the transitional product of analogue system in the digital system transition process, thereby has the stronger market competitiveness in current transition period.But because this analog and digital mixed signal system causes being difficult to develop a kind of communication interface chip that can satisfy each company's requirement.

3. adopt unified DDL DDL.The field apparatus developer adopts DDL language description field apparatus characteristic, and being responsible for these device descriptions of registration management and being compiled them by the HART foundation is the device description dictionary, and the characterisitic parameter of field apparatus understood in main equipment utilization DDL language.

The core technology that realizes the HART agreement is modulator-demodulator, yet special-purpose HART modulator-demodulator only has a few chip producer supply of material, and is on the high side, and delivery cycle is difficult for guaranteeing.On the other hand; Single-chip microcomputer is as a kind of general-purpose device; Through the fast development in nearly ten or twenty year, obtained significant progress at aspects such as high integration, high-performance, low-power consumption, low costs, particularly integrated after the analog peripheral such as ADC, DAC, comparator; Cooperate typical timer, M SART, GPIO etc., can on a single-chip microcomputer, realize a complete mini system.If the HART modulator-demodulator is regarded as a mini system, select suitable single-chip microcomputer to realize this mini system, can realize higher cost performance.

For this reason, the patent No. is the method that the Chinese invention patent of ZL 02160544.0 provides a kind of SCM Based modulator-demodulator and the transmission of realization HART protocol signal thereof.This HART modulator-demodulator comprises a single-chip microcomputer, and HART signal demodulation unit, HART signal modulating unit and I/O output port register, asynchronous serial receiver module, a HART protocol signal link of being arranged in this single-chip microcomputer are resolved and command processor.Corresponding method may further comprise the steps: the pin from single-chip microcomputer is input to HART signal modulating unit to a. behind the frequency shift keying square wave through becoming behind the bandpass filtering with the HART sine wave signal earlier; B. after the demodulation of HART signal modulating unit output logic " 0 ", " 1 " signal to I/O output port register; C. through the single-chip microcomputer pin logical zero, " 1 " signal are input to the asynchronous serial receiver module; D. the asynchronous serial receiver module receives the HART communication frame through demodulation; Deliver to parsing of HART protocol signal link and command processor again communication frame is carried out link parsing and command process, acquisition logical zero, " 1 " signal are delivered to the signal modulating unit and are carried out the signal modulation; E. after demodulation, produce of the pin output of frequency shift keying square wave, transfer out through output HART sine wave signal after the waveform shaping from single-chip microcomputer.

Summary of the invention

Primary technical problem to be solved by this invention provides a kind of HART modulator-demodulator.This HART modulator-demodulator can solve problems such as cost is higher in the prior art, supply channel is single based on chip microcontroller.

Another technical problem to be solved by this invention provides the concrete grammar that above-mentioned HART modulator-demodulator is realized demodulation.

For realizing above-mentioned goal of the invention, the present invention adopts following technical scheme:

A kind of HART modulator-demodulator is characterized in that:

Said HART modulator-demodulator comprises half-duplex control module, modulation module, demodulation module, parallel serial conversion module, string and modular converter, reception data module, transmission data module, buffered/filtered/separated straight module, cycle module, thresholding module, filtering/biasing module, isolation module and input/output module; Wherein,

Said reception data module, said parallel serial conversion module and said modulation module are linked in sequence, and are connected with said buffered/filtered/separated straight module through first gating switch with said half-duplex control module;

Said transmission data module, said string and modular converter and said demodulation module are linked in sequence; Said cycle module is connected with said demodulation module through second gating switch with said thresholding module, and said filtering/biasing module connects said cycle module and said thresholding module respectively;

Said isolation module is connected with said filtering/biasing module with said buffered/filtered/separated straight module respectively on the one hand, connects said input/output module on the other hand.

Wherein more excellently, said half-duplex control module, said modulation module, said demodulation module, said parallel serial conversion module, said string and modular converter, said reception data module and said transmission data module are realized by the intrinsic module in the single-chip microcomputer.

Wherein more excellently, said single-chip microcomputer is the STM8L15x series monolithic.

Wherein more excellently, said modulation module is made up of digital to analog converter, direct memory access device and timer, and wherein said timer connects said direct memory access device, and said direct memory access device connects said digital to analog converter.

Wherein more excellently, after the sinusoidal array of said direct memory access device in traversal in-chip FLASH zone, return the waveform that the array beginning continues to generate following one-period.

Wherein more excellently, said demodulation module comprises monostable flipflop, pulse width timer, decision unit and demodulating algorithm submodule, and wherein threshold signal forms the enable signal of said demodulating algorithm submodule through said monostable flipflop; Periodic signal is imported in the said pulse width timer, and after said decision unit is handled, converts symbol sebolic addressing into, gets into said demodulating algorithm submodule and handles, and finally exports 0/1 data slot.

Wherein more excellently, said periodic signal connects the pin of catching of timer in the single-chip microcomputer, and said threshold signal connects the IO pin of single-chip microcomputer, and the PWM capturing function that utilizes timer in the single-chip microcomputer carries out the pulsewidth timing to the high-low level time of said periodic signal.

Wherein more excellently, the outermost of said input/output module is provided with Transient Suppression Diode and resettable fuse.

A kind of HART modulator-demodulator is realized the method for demodulation, realizes based on above-mentioned HART modulator-demodulator, and the demodulating algorithm submodule wherein is set in demodulation module; It is characterized in that:

In said demodulating algorithm submodule; Whether enable signal is sent to follow-up unit as gate-control signal control character sequence; Filtering out does not then influence the symbol of subsequent treatment U in the symbol sebolic addressing, trailing edge detecting unit of parallel connection is monitored the LS and the LMS that occur in the symbol sebolic addressing simultaneously;

Symbol sebolic addressing after filtering and trailing edge detecting unit output signal are input to the demodulating algorithm state machine jointly;

Said demodulating algorithm state machine adopts ping-pong buffers device deal with data, and output valid symbol fragment converts the symbol fragment into 0/1 data slot by decision unit, converts byte into through string and modular converter.

Wherein more excellently, said demodulating algorithm state machine comprises four kinds of states: free time, an affirmation, reception and reprocessing;

When idle condition, wait for the trailing edge signal; When the trailing edge detecting unit provides the trailing edge signal, get into an affirmation state;

Under head affirmation state, confirm that whether the trailing edge back is the bit 0 of a complete code-element period, confirms successfully to get into accepting state, confirm to fail and return idle condition;

Accepting state is safeguarded a timer, restarts this timer when getting into accepting state, and complete symbol data in the reception during this period of time only when detecting abnormal conditions, directly returns idle condition;

Get into reprocessing state, soft timer of this reprocessing state-maintenance behind the said timer expiry; When receiving continuous data, the reprocessing state issues existing trailing edge, crosses idle condition and gets into an affirmation state, switches ping-pong buffers device and notifier processes; When receiving the end of non-continuous data or continuous data, if said soft timer is overtime, return idle condition, switch ping-pong buffers device and notifier processes.

HART modulator-demodulator provided by the present invention can be based on chip microcontroller, thereby solves problems such as cost is higher in the prior art scheme, supply channel is single.The modulation module of this HART modulator-demodulator and demodulation module are through optimal design, and not only operational capability is stronger, and are convenient to debugging, and the scope of application is wider.

Description of drawings

Fig. 1 is the overall system diagram of HART modulator-demodulator provided by the present invention;

Fig. 2 is in the HART modulator-demodulator, the theory of constitution block diagram of modulation module;

Fig. 3 is the circuit theory sketch map of buffered/filtered/separated straight module;

Fig. 4 is the circuit theory sketch map of cycle module, thresholding module and filtering/biasing module;

Fig. 5 is the operation principle sketch map of demodulation module;

Fig. 6 is reduced to the decision rule sketch map of symbols streams for cycle duration;

Fig. 7 is reduced to the decision rule sketch map of symbols streams for cycle duration;

Fig. 8 is the operation principle block diagram of demodulating algorithm submodule;

Fig. 9 is the working state schematic representation of demodulating algorithm state machine;

Figure 10 is the circuit theory diagrams of isolation module and input/output module.

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed description.

In one embodiment of the invention, adopt the STM8L15x series monolithic to realize supporting the modulator-demodulator of HART agreement.The STM8L15x series monolithic is 8 8-digit microcontrollers (MCU) that STMicw Electronics releases; Built-in 12 DAC (digital to analog converter) in its sheet, have the DMA (direct memory access device) of circulation pattern and, can constitute modulation module as the timer (TIMER) of DMA time reference.Certainly, adopt other general single chip with similar functions, for example STM8L10x series or STM8L16x series can realize the present invention equally, just differ at this and one have explained for example.

Fig. 1 is the overall system diagram of HART modulator-demodulator provided by the present invention.This HART modulator-demodulator comprises RTS (request is sent)/automatically half-duplex control module (being called for short the half-duplex control module), modulation module, demodulation module, parallel serial conversion module, string and modular converter, RXD (reception data) module, TXD (transmission data) module, buffered/filtered/separated straight module, cycle module, thresholding module, filtering/biasing module, isolation module and input/output module.Wherein, the automatic half-duplex control module of RTS/, modulation module, demodulation module, parallel serial conversion module, string and modular converter, RXD module, TXD module can be realized by the intrinsic module in the STM8L15x series monolithic.Among this single-chip microcomputer, RXD module, parallel serial conversion module and modulation module are linked in sequence, and are connected with buffered/filtered/separated straight module through gating switch with the automatic half-duplex control module of RTS/.This modulation module is made up of DAC, DMA and timer, and this is one of technical characterstic of the present invention.On the other hand, TXD module, string and modular converter and demodulation module are linked in sequence, and the cycle module is connected with above-mentioned demodulation module through gating switch with the thresholding module.Outside this single-chip microcomputer, filtering/biasing module connects cycle module and thresholding module respectively.Isolation module is connected with filtering/biasing module with buffered/filtered/separated straight module respectively on the one hand, connects above-mentioned input/output module on the other hand.

The data link of above-mentioned HART modulator-demodulator when work is such: when modulating; Behind byte to be modulated the pin entering single-chip microcomputer through the RXD module; Obtain 0/1 code stream via parallel serial conversion module, the modulation module that DAC, DMA and timer constitute in the single-chip microcomputer sheet, the phase place of code stream modulation becoming 1200Hz and 2200Hz is sinusoidal wave continuously; Buffered/filtered outside the single-chip microcomputer sheet/separated straight processing that waits is loaded into the foreign current ring by isolation module and input/output module again; Separating timing; It is inner that carrier wave on the foreign current ring gets into the HART modulator-demodulator via isolation module and input/output module; After filtering/biasing module, cycle module and thresholding module etc. are handled; Analog waveform is converted among the digital waveform input single-chip microcomputer, detect demodulating algorithm, string and conversion links through zero passage again, finally by the pin output of the TXD module in the single-chip microcomputer.

The HART agreement is a kind of half-duplex agreement, and synchronization can only send and accepting state is got one of which in the two.In one embodiment of the invention, the half-duplex of HART modulator-demodulator control can be realized by outside RTS module pin, also can realize control automatically by in house software.For example can be set to manual mode by the HART modulator-demodulator; RTS module pin through UART carries out half-duplex control; Also can change to automatic mode, only when data, switch to modulating mode, all return demodulation modes At All Other Times automatically by in house software.

Before address, the modulation module among the present invention is made up of DAC, DMA and timer.Fig. 2 is the theory of constitution block diagram of this modulation module, and wherein timer connects DMA, and DMA connects DAC.In one embodiment of the invention, 12 interior peripheral hardwares of sheet that DAC, DMA and timer are the STM8L15x series monolithic, all modulation operation are all in the inner completion of single-chip microcomputer, with the output of DAC simulation output pin as modulation module.In the modulation link; At first receive byte to be modulated by the UART peripheral hardware receiving unit (generally being the pin of RXD module) of single-chip microcomputer with the mode of interrupting, then through parallel serial conversion module, forming 0/1 code stream according to information such as the baud rate of appointment, parity checks (is 1200 baud rates in the HART agreement; Odd); And accomplish modulated process jointly by single-chip microcomputer inner DAC, DMA and timer, and wherein 0 in the code stream is modulated into 2200Hz, and 1 is modulated to 1200Hz.

In the STM8L15x series monolithic, the conversion speed of DAC is 1 μ s～10 μ s magnitudes, uses the interior DMA of sheet can increase substantially the access efficiency of peripheral hardware in this type sheet.In addition, DMA supports circulation pattern in this sheet, can after the sinusoidal array of traversal, return the waveform that the array beginning continues to generate following one-period automatically.Like this, not only monophasic waveform does not need the kernel intervention in the cycle, and the generation of whole continuous wave does not need the kernel intervention.Because the interrupt response processing speed of kernel is often also in μ s magnitude, this characteristic has guaranteed continuity and flatness that sinusoidal waveform generates.

In modulation module shown in Figure 2, sine table is 12 read-only arrays in the in-chip FLASH zone, is used for exporting sinusoidal array so that realize producing sine-shaped function to DMA.Through DMA is set, can directly the digital quantity in the sinusoidal array equally spaced be input among the DAC, and forms analog sine waveforms at the output of DAC.Obviously, bigger sinusoidal array helps reducing the step effect of DAC sine wave output, but the speed of DMA moving data can not surpass the conversion speed of DAC.Under this prerequisite, the cycle of DMA moving data has determined the frequency of sine wave output.In the STM8L15x series monolithic, timer is used to control the cycle of DMA moving data.When timer is operated in cyclic pattern; In order to export the analog sine waveforms of 1200Hz and 2200Hz; Can calculated in advance go out the register parameters as the timer of DMA time reference, the register parameters of switching timer can realize the analog sine waveforms output of 1200Hz and 2200Hz.

The HART agreement adopts the Bell202 modulation demodulation system, and a continuity that important feature is a waveform of modulation promptly requires code-element period initial phase and last code-element period end phase place to equate.During the output of 2200Hz logical zero, code-element period and wave period are inconsistent, because the existence of this inconsistency, specific to certain code-element period, first phase is not the value of confirming, but depends on previous code-element period.Utilize modulation module implementation shown in Figure 2; When switching between code element; Only need to upgrade the register parameters of timer, DMA and DAC are not done any operation, the data importing DAC that DMA is still next continuous with sinusoidal array; Form continuous output level, thereby satisfy the HART agreement the successional requirement of waveform.

Modulation module among the present invention also has the enable port that is used to realize half-duplex control except having 0/1 data flow input port.This enable port directly acts on DAC and output pin thereof.When the HART modulator-demodulator was in the signal accepting state, the output pin of DAC was a high-impedance state, helped the detection of input signal.In order to improve the accuracy that waveform receives, can before and after formal 0/1 data flow, respectively produce one section default 1200Hz logical one (high level).

In modulation module provided by the present invention; DAC has optional sheet internal inner ring (Buffer); Because the operating current of its sheet internal inner ring is obviously greater than the outer low-power consumption amplifier of sheet; When modulation module has special demands to low-power consumption, during for example as the HART modulator-demodulator, should forbid the sheet internal inner ring and adopt the low-power consumption amplifier outside the sheet as far as possible.In addition, reducing dominant frequency, shorten sinusoidal data, suitably increase the step effect of output waveform etc., also is the important technique measure that reduces the modulation module overall power.

The waveform that modulation generates is seen off through the DAC output pin, for amplitude 0 have " alias " between the reference voltage sinusoidal signal, and when forbidding sheet internal inner ring, the driving force of waveform very a little less than.From the angle of frequency spectrum, signal also has the high fdrequency component of DC component and generation " alias " except that the 1200Hz that needs with the 2200Hz.This signal obtains modulating back output through buffered/filtered/separated straight resume module.

Fig. 3 is the circuit theory sketch map of buffered/filtered/separated straight module.This buffered/filtered/comprise main first voltage follower that plays cushioning effect at a distance from straight module; Second voltage follower that mainly strobes and the electric capacity that plays at a distance from straight effect; Wherein the positive input of first voltage follower connects the output of modulation module; The output of first voltage follower connects the positive input of second voltage follower behind the RC filter circuit, the output of second voltage follower has connected electric capacity and the isolating transformer at a distance from straight effect.This buffered/filtered/at a distance from the operation principle of straight module is such: consider that the output impedance of DAC is higher in the modulation module, realize buffering through first voltage follower earlier, improve driving force and reduce the distortion of waveform.Step effect in the DAC output waveform can be considered the high-frequency noise in the frequency spectrum; RC filter circuit and second voltage follower subsequently constitute the single order low-pass filter circuit; Because the high-frequency noise of step effect differs greatly with sinusoidal wave frequency own; First-order filtering also can play good filter effect, obtains level and smooth sinusoidal waveform.In single-chip microcomputer, what DAC received is 12 integers of no character type, and scope is 0～4095.Sinusoidal array is an oscillation center with 2047, and waveform after this always is the sinusoidal waveform that has direct current biasing, therefore before buffered/filtered/separated straight module end, isolating transformer, cuts off its flip-flop with an electric capacity.Isolating transformer also has at a distance from straight effect although the sort circuit design is; But electric capacity is at a distance from directly avoiding flip-flop to pass through isolating transformer; Reduce loss raising the efficiency, and avoid the saturated of isolating transformer magnetic core, improve the transmission performance of isolating transformer.

In the demodulation link, the analog signal of at first isolation module being sent here is carried out filtering and biasing.Filtering is in order to reduce high-frequency noise, and biasing is in order to give through the signal of transformer after straight a flip-flop to be provided, and signal amplitude is controlled in the significant level scope of SCM peripheral circuit.Through cycle module and thresholding resume module, obtaining the zero passage cycle information of signal waveform and amplitude information, these two information of signal waveform all is digital quantity, can send into single-chip microcomputer through the I/O mouth and handle.

Fig. 4 is the circuit theory diagrams of cycle module, thresholding module and filtering/biasing module.In filtering/biasing module, get into first order homophase from the AC signal of isolating transformer after through a RC filter circuit and amplify discharge circuit.This amplifier is single supply op, and is interval for the significant level that AC signal is controlled at amplifier, after the RC filter circuit, increased a 100K resistance that is connected to Vref, increased a capacitance before.Vref can get the half the of VCC voltage or be slightly less than half the (this is the technical characterictic of single supply op), for example when 5V supplies power, and the desirable 2～2.5V of Vref.The 100K resistance of aforementioned increase and capacitance have guaranteed the operate as normal of first order in-phase amplification circuit for the pure AC signal of input provides biasing.The gain of first order in-phase amplification circuit is confirmed by the ratio of a pair of resistance in below, only need be got 1～4 times usually and get final product.

As shown in Figure 4, the waveform after first order in-phase amplification circuit is handled again through the straight bias treatment of a septum secundum, gets into two comparators of back.The cycle comparator (being the cycle module) of top directly compares with bias level Vref, and amplifier is in the operate in open loop state state at this moment, can sinusoidal waveform be processed into synchronous square wave of cycle.So far, analog signal become one the road be loaded with input waveform cycle information 0/1 digital signal, common IO pin or the timer that can send into single-chip microcomputer are caught pin and are carried out subsequent treatment.The threshold compataror (being the thresholding module) of below with a little less than reference level of Vref relatively; When not having waveform input or wave-shape amplitude not enough; The high level that threshold compataror output continues; Have only when importing wave-shape amplitude greater than certain thresholding, threshold compataror just can be exported a series of low level.This threshold value can be adjusted through changing the divider resistance value.These a series of low level or trailing edges that are loaded with input waveform amplitude information, the common IO pin that can send into single-chip microcomputer carries out subsequent treatment.

Shown in Figure 5 is the operation principle sketch map of demodulation module.Comprise monostable flipflop, pulse width timer, decision unit and demodulating algorithm submodule in this demodulation module, wherein threshold signal forms the enable signal of demodulating algorithm submodule through a monostable flipflop; In the periodic signal input pulse width timer, and after decision unit is handled, convert symbols streams (being symbol sebolic addressing) into, get into the demodulating algorithm submodule and handle, finally export effective 0/1 data slot.The time delay of monostable flipflop is that 1～4 code-element period gets final product, and is triggered by low level, that is to say and has only the enough big waveform of amplitude just to carry out demodulating algorithm.This point is consistent with the regulation of HART agreement.

In one embodiment of the invention; Periodic signal connects the pin of catching of timer in the single-chip microcomputer; Threshold signal connects the common IO pin of single-chip microcomputer, and the PWM capturing function that utilizes timer in the STM8L15x series monolithic carries out the pulsewidth timing to the high-low level time of periodic signal.The timer capturing function does not need the intervention of kernel, and is irrelevant with the program of current executed, do not need operations such as interrupt response, do not have problems such as interrupt nesting, can be as accurate as the single clock cycle, can obtain than the higher precision of IO interruption+timer timing.

The pulsewidth that timer obtains is the duration at adjacent two edges, comprises rising edge and trailing edge, is generally the numerical value of 16 bits.For this 8 single-chip microcomputers of STM8L 15x, subsequent treatment is relatively complicated.In order to simplify subsequent treatment, through a decision unit, convert 16 bit duration informations to a symbols streams among the present invention.Concrete transformation rule is as shown in Figure 6; Because corresponding two pulsewidths of sinusoidal period; The pulsewidth of 1200Hz and 2200Hz should be 0.5 * 1200Hz-1 and 0.5 * 2200Hz-1 under the ideal situation, and these two pulsewidths are considered the uncertainty of initial phase, the input imbalance of comparator and the shake that noise causes with symbol L (Long) and S (Short) expression; Symbol L and S allow the error of certain limit, shown in dash area among Fig. 6.

Initial phase is uncertain also can to cause bigger variation; Like 2200Hz bit 0 first phase among Fig. 7 is 3/2 π; Pulsewidth in the middle of be positioned in this moment just is the intermediate value of L and S; Be judged to be bit 0 and bit 1 and account for respectively that half is more suitable, use symbol M (Middle) expression here, like the blank parts between L among Fig. 6 and the S.The zone that is lower than symbol S is judged to U (Under), when this situation generally is comparator toggles, and the shake that high-frequency noise caused that filtering is remaining, the pulsewidth of representing much smaller than symbol S.The zone that is higher than symbol L is judged as O (Over), and this situation generally is that wiring or amplitude instability cause the local disappearance of waveform, forms overtime.

The demodulating algorithm submodule is the core part of demodulation module, is used to receive the symbol sebolic addressing from decision unit, exports effective 0/1 data slot.In the UART agreement, it is complete 1 that the idle condition of free of data is equivalent to, and also has quite a few time to be in this complete 1 state in the HART modulator-demodulator, and the demodulating algorithm submodule is regarded as invalid data with it.According to the UART agreement, the initial symbol of data is the low level of 1 code-element period again, can think that valid data must be guided by trailing edge, and the demodulating algorithm submodule is only exported this active data fragment.

Single-chip microcomputer is sent wave period information that obtains and amplitude information into the demodulating algorithm submodule and is separated to be in harmonious proportion and adjudicate, and obtains effective 0/1 code stream.Referring to shown in Figure 2, string and modular converter are merged into byte with these code streams by certain rule, carry out parity check simultaneously.Verification mistake etc. is wrong to be occurred if having, the output error information, correctly go here and there and change after byte, the UART peripheral hardware transmitting section (generally being the pin of TXD module) through single-chip microcomputer sends.

The operation principle block diagram of demodulating algorithm submodule is as shown in Figure 8; Whether enable signal is sent to follow-up unit as gate-control signal control character sequence; Filter out then the U that do not influence subsequent treatment in the symbol sebolic addressing (symbol U during generally by the comparator zero passage shake cause, do not influence the sequence judgement after the filtration), trailing edge detecting unit of parallel connection simultaneously; " LS " and " LMS " that occurs in the monitoring symbol sebolic addressing is if then provide the trailing edge signal.Symbol sebolic addressing after filtering and trailing edge detecting unit output signal are input to the demodulating algorithm state machine jointly.

The demodulating algorithm state machine is unit with the byte, and not only output has certain delay, and need take a buffering area during handling.Therefore, the demodulating algorithm state machine adopts ping-pong buffers device (Buffer) to come deal with data.The ping-pong buffers device selects through the input data and dateout is selected; By beat, switching with cooperatively interacting; Problems such as the data flow that will pass through buffering is delivered to follow-up decision unit without a break and carried out computing and processing, and data forward lap in the time of can solving continuous data effectively, reception and subsequent treatment are parallel.The valid data fragment that the demodulating algorithm state machine detects still is the symbol fragment when being exported by the ping-pong buffers device, and decision unit subsequently converts the symbol fragment into 0/1 data slot, converts byte into through string and modular converter.The sequence of demodulating algorithm state machine output only is made up of S, M, L, and M must appear between L and the S, and the switching criterion of decision unit is following:

● meet the direct switching of L and S, or, be the symbol interval sign through the switching of M, as at interval the symbol fragment being divided into the son section, and the number of statistics continuous symbol;

● when adding up the number of continuous L and S, M is converted to 1/2 L and 1/2 S, and is as shown in Figure 7, obtains entirely by L or two types of son sections being made up of S entirely, might as well become L section and S section;

● for L section,, then convert X/2 continuous 1 into if symbol L number is X;

● for S section, if symbol S number is Y, then convert into Y/3.667 continuous 0,3.667=2*2200Hz/1200Hz wherein;

Fig. 9 is the sketch map of demodulating algorithm state machine, and it has four kinds of states: free time, an affirmation, reception and reprocessing.When idle condition, wait for trailing edge; When the trailing edge detecting unit provides the trailing edge signal, get into data head and confirm state.Under this state, confirm that whether the trailing edge back is the bit 0 of a complete code-element period, confirms successfully to get into data receiving state, confirm to fail and return idle condition.

Accepting state is safeguarded a soft timer, and timer duration is the duration of a byte in the HART agreement.Restart timer when getting into accepting state, receive during this period of time in complete symbol data, only when detecting abnormal conditions such as symbol 0, directly return idle condition.

Get into the reprocessing state, the soft timer that duration of this state-maintenance is several code-element periods after receiving timer expiry.When receiving continuous data, an and then trailing edge and the beginning of pointing out next data behind the position of rest of 1 or 2 bit, promptly the reprocessing state issues existing trailing edge, crosses idle condition and gets into an affirmation state, switches ping-pong buffers device and notifier processes.When receiving the end of non-continuous data or continuous data, the reprocessing soft timer is overtime, returns idle condition, switches ping-pong buffers device and notifier processes.

In the HART agreement, main variables and control information are transmitted by 4～20mA electric current loop.As the HART modulator-demodulator, need can jump in 4～20mA electric current loop, under the situation that does not influence electric current loop, carry out carrier communication.Therefore, after modulation output, add isolation module and input/output module.Wherein, isolation module mainly is made up of audio frequency transformer, and input/output module is mainly played a protective role by formations such as TVS (Transient Suppression Diode), resettable fuses.Isolation module and input/output module are two-way modules, and sinusoidal signal to be demodulated is also returned from this link.

Figure 10 is the circuit theory diagrams of isolation module and input/output module in the HART modulator-demodulator, and its core is an isolating transformer and a capacitance.Because 1200Hz and 2200Hz all are in the stage casing of audio frequency, isolating transformer can adopt common on the market 600:600 audio frequency transformer, and this transformer number of turn is many, the line footpath is thin, can select for use patch-type to reduce volume.Capacitance only is used to guarantee the alternating component of modulation is connected with 4～20mA electric current loop loop, does not influence the direct current signal of electric current loop.This capacitance can not be polar capacitor, has adopted common 0.1u patch capacitor here, withstand voltage being generally more than the 36V.

From the consideration of electromagnetic compatibility and fail safe, the input/output interface outermost has increased TVS (Transient Suppression Diode) and resettable fuse.Consider the 24V DC power supply of a large amount of uses, the withstand voltage desirable 36V of TVS does not influence normal use and can protect capacitance.Resettable fuse and TVS can guarantee that together the big electric current of big voltage that surge or misoperation cause gets into input/output module, and the protection isolating transformer is not burnt.

Above SCM Based HART modulator-demodulator provided by the present invention and its implementation have been carried out detailed explanation.As far as one of ordinary skill in the art, any conspicuous change of under the prerequisite that does not deviate from connotation of the present invention, it being done all will constitute to infringement of patent right of the present invention, with corresponding legal responsibilities.

Claims (10)

1. HART modulator-demodulator is characterized in that:

Said HART modulator-demodulator comprises half-duplex control module, modulation module, demodulation module, parallel serial conversion module, string and modular converter, reception data module, transmission data module, buffered/filtered/separated straight module, cycle module, thresholding module, filtering/biasing module, isolation module and input/output module; Wherein,

Said reception data module, said parallel serial conversion module and said modulation module are linked in sequence, and are connected with said buffered/filtered/separated straight module through first gating switch with said half-duplex control module;

Said transmission data module, said string and modular converter and said demodulation module are linked in sequence; Said cycle module is connected with said demodulation module through second gating switch with said thresholding module, and said filtering/biasing module connects said cycle module and said thresholding module respectively;

Said isolation module is connected with said filtering/biasing module with said buffered/filtered/separated straight module respectively on the one hand, connects said input/output module on the other hand.

2. HART modulator-demodulator as claimed in claim 1 is characterized in that:

Said half-duplex control module, said modulation module, said demodulation module, said parallel serial conversion module, said string and modular converter, said reception data module and said transmission data module are realized by the intrinsic module in the single-chip microcomputer.

3. HART modulator-demodulator as claimed in claim 2 is characterized in that:

Said single-chip microcomputer is the STM8L15x series monolithic.

4. like any described HART modulator-demodulator in the claim 1～3, it is characterized in that:

Said modulation module is made up of digital to analog converter, direct memory access device and timer, and wherein said timer connects said direct memory access device, and said direct memory access device connects said digital to analog converter.

5. HART modulator-demodulator as claimed in claim 4 is characterized in that:

After the sinusoidal array of said direct memory access device in traversal in-chip FLASH zone, return the waveform that the array beginning continues to generate following one-period.

6. like any described HART modulator-demodulator in the claim 1～3, it is characterized in that:

Said demodulation module comprises monostable flipflop, pulse width timer, decision unit and demodulating algorithm submodule, and wherein threshold signal forms the enable signal of said demodulating algorithm submodule through said monostable flipflop; Periodic signal is imported in the said pulse width timer, and after said decision unit is handled, converts symbol sebolic addressing into, gets into said demodulating algorithm submodule and handles, and finally exports 0/1 data slot.

7. HART modulator-demodulator as claimed in claim 6 is characterized in that:

Said periodic signal connects the pin of catching of timer in the single-chip microcomputer, and said threshold signal connects the IO pin of single-chip microcomputer, and the PWM capturing function that utilizes timer in the single-chip microcomputer carries out the pulsewidth timing to the high-low level time of said periodic signal.

8. like any described HART modulator-demodulator in the claim 1～3, it is characterized in that:

The outermost of said input/output module is provided with Transient Suppression Diode and resettable fuse.

9. the method for a HART modulator-demodulator realization demodulation realizes based on HART modulator-demodulator as claimed in claim 1, and the demodulating algorithm submodule wherein is set in demodulation module; It is characterized in that:

In said demodulating algorithm submodule; Whether enable signal is sent to follow-up unit as gate-control signal control character sequence; Filtering out does not then influence the symbol of subsequent treatment U in the symbol sebolic addressing, trailing edge detecting unit of parallel connection is monitored the LS and the LMS that occur in the symbol sebolic addressing simultaneously;

Symbol sebolic addressing after filtering and trailing edge detecting unit output signal are input to the demodulating algorithm state machine jointly;

Said demodulating algorithm state machine adopts ping-pong buffers device deal with data, and output valid symbol fragment converts the symbol fragment into 0/1 data slot by decision unit, converts byte into through string and modular converter.

10. HART modulator-demodulator as claimed in claim 9 is realized the method for demodulation, it is characterized in that:

Said demodulating algorithm state machine comprises four kinds of states: free time, an affirmation, reception and reprocessing;

When idle condition, wait for the trailing edge signal; When the trailing edge detecting unit provides the trailing edge signal, get into an affirmation state;

Under head affirmation state, confirm that whether the trailing edge back is the bit 0 of a complete code-element period, confirms successfully to get into accepting state, confirm to fail and return idle condition;

Accepting state is safeguarded a timer, restarts this timer when getting into accepting state, and complete symbol data in the reception during this period of time only when detecting abnormal conditions, directly returns idle condition;

Get into reprocessing state, soft timer of this reprocessing state-maintenance behind the said timer expiry; When receiving continuous data, the reprocessing state issues existing trailing edge, crosses idle condition and gets into an affirmation state, switches ping-pong buffers device and notifier processes; When receiving the end of non-continuous data or continuous data, if said soft timer is overtime, return idle condition, switch ping-pong buffers device and notifier processes.

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