CN1514596A - Modulator-demodulator based on single chip machine and its method of realizing HART protocol signal transmission - Google Patents
Modulator-demodulator based on single chip machine and its method of realizing HART protocol signal transmission Download PDFInfo
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Abstract
The modem includes a single chip containing HART signal demodulation unit, register at I/O output port, asynchronous serial receiving module, command processor for parsing signal link in HART protocol. The method includes following steps: (1) HART sine wave signal through band-pass filter become frequency shift keying (FSK) square wave, which is input to HART signal demodulation unit from pins of single chip; (2) with being modulated by HART signal demodulation unit, '0' or '1' signals are input to register at I/O output port; (3) '0' or '1' signals through pins of single chip are input to the asynchronous serial receiving module; (4) the asynchronous serial receiving module receives demodulated HART communication frame, which is processed by the command processor and modulated by the signal demodulation unit; (5) demodulated FSK square wave is reshaped to sine wave to be output. The modem possesses features of high calculation capability, reliable operation and wide application.
Description
Technical field
The present invention relates to the data communication at Industry Control scene, particularly relate to the method for SCM Based modulator-demodulator and realization HART protocol signal thereof transmission, it is applicable to the embedded system in fieldbus in the Industry Control (Fieldbus) field.
Background technology
HART communications protocol (Highway Addressable Remote Transducer) is the interim standards that Rosemount company proposed in 1986.It is that the amplitude that superposeed on 4 ~ 20mA analog signal is FSK (the Frequency Shift Keying of 0.5mA, frequency shift keying) digital signal, 1200Hz represents logical one, and 2200Hz represents logical zero, as shown in Figure 1, its data transfer rate is 1200bps.Like this, both the transmission of 4 ~ 20mA analog signal can be carried out, digital communication can be carried out again.As an open agreement, through the development of more than ten years, the HART agreement has become the actual industrial standard of intelligence instrument.
Up to now, the HART Protocol-Modem is to realize with special circuit (ASIC) or programmable digital signal processor (DSP) usually always.In typical application, a microprocessor and an asic chip or a DSP can cooperate effectively with master-slave mode.In this cooperation work, " 0 " or " 1 " logical signal that the hardware HART modulator-demodulator that asic chip or dsp chip are realized can be familiar with HART signal demodulation the becoming microprocessor of loop; Simultaneously, this hardware MODEM can send microprocessor " 0 " or " 1 " logical signal again and convert the HART protocol signal to.Therefore, microprocessor only plays the effect of " controller ", bears the function of control; Asic chip or dsp chip then play spending of a dedicated computing and modulation engine substantially and realize conversion between HART protocol signal and " 0 ", " 1 " logical signal.Fig. 2 is that the typical case of hardware MODEM uses block diagram.
Above-mentioned typical arrangement will move in " in real time " context (context).In other words: microprocessor and ASIC modem chip (or DSP) are if the both is special-purpose, to realize controller and modulation engine function respectively.In real time context provides the certainty behavior, and this certainty behavior is desirable in the modulation context, because modem traffic is with continuous and arrive with fixed rate.Because this certainty, determined under this kind modulation demodulation system must have powerful operation capacity as the ASIC modem chip (or DSP) of modulation engine.
Though the said structure arrangement has become main flow, to be accepted extensively by market, the parts expense that asic chip (or DSP) and other specialized hardware relate to is relatively more expensive.Moreover they have increased the manufacturing that is associated, and supply with and safeguard the expense of aspect, and influence the reliability of whole system; Simultaneously, because the uncertainty in market, can cause the application of hardware modem to be subjected to the restriction of market supply, cause negative effect to product development.
Summary of the invention
The present invention is the SCM Based modulator-demodulator of fieldbus embedded system of a kind of software program based on general low-power consumption single chip microcontroller of proposing for the defective that solves existing HART signal modem HART modulating and demodulating signal function of realizing special-purpose asic chip (or DSP) and the method for realization HART protocol signal transmission thereof, this modulator-demodulator operational capability is strong, operation is reliable, applied range.
The technical measures that the present invention takes are:
SCM Based HART protocol signal modulator-demodulator, it is characterized in that, comprise a single-chip microcomputer, and HART signal demodulation unit, HART signal modulating unit and the I/O output port register, asynchronous serial receiver module, the HART protocol signal link that are arranged in this single-chip microcomputer are resolved and command processor; Described HART signal demodulation unit receives from the next signal of HART signal medium medium transmission, after demodulation, deliver to I/O output port register, by this I/O output port register transfer to the asynchronous serial receiver module, this asynchronous serial receiver module receives the HART communication frames through demodulation, delivering to parsing of HART protocol signal link and command processor again handles, acquisition logical zero, " 1 " signal are delivered to the signal modulating unit and are carried out the signal modulation, and the signal after the signal modulation is gone out by HART signal medium medium transmission again.
Above-mentioned SCM Based HART protocol signal modulator-demodulator, wherein, described HART signal demodulation unit comprises that marginal detector, maintenance register input selector switch, pulsewidth keep register, pulsewidth to keep register value to move into shift register selector switch, filtering shift register, adder-subtractor, accumulated value comparator, the maximum amplitude limiter of accumulated value, filtering accumulator;
Described marginal detector is used to detect the pulsewidth of the square wave on the CPU pin, and this pulsewidth is sent into maintenance register input selector switch;
Described maintenance register input selector switch is used to judge that pulsewidth that marginal detector sends into whether less than minimum pulse width, sends into a suitable pwm value pulsewidth then and keep register;
Described pulsewidth keeps register that this value is sent into 16 filtering accumulator and pulsewidth keeping planting and move into the shift register selector switch;
Described pulsewidth keeps register value to move into the selection that the shift register selector switch is used to move into and does not move into;
Described filtering shift register is used for moving in and out and depositing of pwm value;
Described filtering accumulator is used for adding up of pwm value, and this accumulated value is delivered to the accumulated value comparator;
Described accumulated value comparator is used for the comparison to filtering accumulated value size, thereby decision is defeated " 1 " or " 0 ";
The maximum amplitude limiter of described accumulated value is used for current filtering accumulated value is carried out maximum amplitude limit, and whether the value of control and decision filtering accumulator be updated, and the control pulsewidth keeps register value to move into shift register selector switch decision pulsewidth keeping the sampled value of register whether to move into the filtering shift register.
Above-mentioned SCM Based HART protocol signal modulator-demodulator, wherein, described HART signal modulating unit comprises phase-accumulated value selector, adder, phase accumulator, phase-accumulated value determining device, single-chip microcomputer pin negate follower; Thereby described phase-accumulated value selector determines the size of phase-accumulated value with 0,1 logical signal that HART protocol signal link is resolved and command processor is exported in 1200 the baud rate reception single-chip microcomputer.Selected phase-accumulated value is added to phase accumulator every the very short time after adder, the value of phase accumulator outputs to phase-accumulated value determining device, after judging, phase-accumulated value determining device outputs to single-chip microcomputer pin negate follower single-chip microcomputer pin negate follower: when phase accumulator is added to the π integral multiple, the negate of CPU pin level is once represented one time zero passage.From the frequency shift keying square wave of single-chip microcomputer pin negate follower output through HART signal medium medium transmission.
SCM Based HART protocol signal modulation-demo-demodulation method is characterized in, may further comprise the steps:
A, earlier the pin from single-chip microcomputer is input to the HART signal demodulation unit behind the translation keying square wave through becoming behind the bandpass filtering with the HART sine wave signal;
B, after the demodulation of HART signal demodulation unit output logic " 0 ", " 1 " signal to I/O output port register;
C, logical zero, " 1 " signal are input to the asynchronous serial receiver module by the single-chip microcomputer pin;
D, asynchronous serial receiver module receive the HART communication frames through demodulation, deliver to parsing of HART protocol signal link and command processor again communication frames is carried out link parsing and command process, acquisition logical zero, " 1 " signal are delivered to the signal modulating unit and are carried out the signal modulation;
E, after demodulation, produce of the pin output of translation keying square wave, transfer out by output HART sine wave signal after the waveform shaping from single-chip microcomputer.
Above-mentioned SCM Based HART protocol signal modulation-demo-demodulation method, wherein, the described method through the demodulation of HART signal demodulation unit of step b may further comprise the steps:
B1, marginal detector receive the square-wave signal that transmission medium transmits, deliver to the maintenance register after testing after the pulsewidth by selector switch, deliver to pulsewidth again and keep register, if this pulsewidth is less than the minimum pulse width of setting, then minimum pulse width is put into pulsewidth and keeps register, realize minimum amplitude limit;
B2, keep register to sample with certain frequency to pulsewidth, each sampling back adds this sampled value with the value of filtering accumulator and deducts the value to be shifted out of filtering shift register, draws a new accumulated value in adder-subtractor;
B3, the new accumulated value that step b2 is drawn are divided into two-way:
One the tunnel sends into the maximum amplitude limiter of accumulated value and the maximum limit amplitude compares; Result relatively will control and determine whether the value of filtering accumulator is updated, and the control pulsewidth keeps register value immigration shift register selector switch to decide pulsewidth to keep the sampled value of register whether to move into the filtering shift register: if accumulated value is greater than the maximum limit amplitude, then the filtering accumulator will not upgraded by this accumulated value, and the filtering shift register does not carry out moving in and out of data yet; If accumulated value is less than the maximum limit amplitude, then the filtering accumulator is updated to this accumulated value, and the pulsewidth that samples keeps register value to move into the filtering shift register;
Another road is sent into the accumulated value comparator and is compared, if greater than set point, and with regard to demodulation output 1, otherwise with regard to demodulation output 0;
0,1 logical signal after b4, the demodulation is through the I/0 output port output of single-chip microcomputer.
Above-mentioned SCM Based HART protocol signal modulation-demo-demodulation method, wherein, the described method through the modulation of HART signal modulating unit of steps d may further comprise the steps:
Thereby d1, phase-accumulated value selector determine the size of phase-accumulated value with 0,1 logical signal that HART protocol signal link is resolved and command processor is exported in 1200 the baud rate reception single-chip microcomputer;
D2, selected phase-accumulated value are added to phase accumulator every the very short time after adder;
The value of d3, phase accumulator outputs to phase-accumulated value determining device, output to single-chip microcomputer pin negate follower after phase-accumulated value determining device is judged, the frequency shift keying square wave after the modulation of single-chip microcomputer pin negate follower output is through HART signal medium medium transmission.
Above-mentioned SCM Based HART protocol signal modulation-demo-demodulation method, wherein, steps d 3 described phase-accumulated value determining devices judgements are meant: the negate of single-chip microcomputer pin level is once represented one time zero passage when phase accumulator is added to the π integral multiple; Otherwise, represent also not zero passage, level keeps.
Above-mentioned SCM Based HART protocol signal modulation-demo-demodulation method, wherein, described phase accumulator is added to the π integral multiple and is meant that accumulator overflows expression and arrives a π phase place.
Because the present invention has adopted above technical scheme, and the modulator-demodulator specialized designs on a low-power consumption general-purpose built-in type single chip microcontroller platform, is controlled by the main program of single chip microcontroller, realizes the modulation to the HART protocol signal.Because of the hardware platform and the control program of this modulator-demodulator is scalable and transplantable, therefore, this modulator-demodulator can be modified at an easy rate, to adapt to dissimilar microcontrollers.
Description of drawings
Concrete feature of the present invention, performance are further described by following embodiment and accompanying drawing thereof.
Fig. 1 is general HART signal schematic representation.
Fig. 2 is that prior art modulator-demodulator typical case uses block diagram.
Fig. 3 is the structured flowchart that the present invention is based on the HART protocol signal modulator-demodulator of single-chip microcomputer.
Fig. 4 is the electrical block diagram of demodulating unit of the present invention.
Fig. 5 is the electrical block diagram of modulating unit of the present invention.
Fig. 6 is the structured flowchart of the present invention when using.
Fig. 7 is the embodiment schematic diagram of the present invention when using.
Fig. 8 is the modulate circuit schematic diagram of received signal among Fig. 7.
Fig. 9 sends the signal conditioning circuit schematic diagram among Fig. 7.
Figure 10 is by 11 HART communication charcter topology figure that form.
Figure 11 is noise suppressed and the minimum amplitude limit flow chart of pressure that pulsewidth of the present invention detects.
Figure 12 is geometric average software filtering of the present invention and forces maximum amplitude limit techniqueflow chart.
Figure 13 is a router FB(flow block) of the present invention.
Embodiment
See also Fig. 3, this is a structured flowchart of the present invention.SCM Based HART protocol signal modulator-demodulator, it comprises a single-chip microcomputer 1, and the HART signal demodulation unit 11, HART signal modulating unit 12, an I/O output port register 13, asynchronous serial receiver module 14, the HART protocol signal link that are arranged in this single-chip microcomputer are resolved and command processor 15; HART signal demodulation unit 11 receives from the next signal of HART signal medium medium transmission, after demodulation, deliver to I/O output port register 13, by this I/0 output port register transfer to asynchronous serial receiver module 14, this asynchronous serial receiver module receives the HART communication frames through demodulation, delivering to parsing of HART protocol signal link and command processor 15 again handles, acquisition logical zero, " 1 " signal are seen off signal modulating unit 12 and are carried out the signal modulation, and the signal after the signal modulation is gone out by HART signal medium medium transmission again.
See also Fig. 4, this is the electrical block diagram of demodulating unit of the present invention.HART signal demodulation unit 11 of the present invention comprises that marginal detector 111, maintenance register input selector switch 112, pulsewidth keep register 113, pulsewidth to keep register value to move into shift register selector switch 114, filtering shift register 115, adder-subtractor 116, accumulated value comparator 117, the maximum amplitude limiter 118 of accumulated value, filtering accumulator 119; Marginal detector receives the square-wave signal that transmission medium transmits, deliver to the maintenance register after testing after the pulsewidth by selector switch, deliver to pulsewidth again and keep register, if this pulsewidth is less than the minimum pulse width of setting, then minimum pulse width is put into pulsewidth and keeps register, realize minimum amplitude limit; Keep register to sample with certain frequency to pulsewidth, each sampling back adds this sampled value with the value of filtering accumulator and deducts the value to be shifted out of filtering shift register, draws a new accumulated value in adder-subtractor.This new accumulated value is divided into two-way: the one tunnel sends into the maximum amplitude limiter of accumulated value and the maximum limit amplitude compares.Result relatively will control and determine whether the value of filtering accumulator is updated, and the control pulsewidth keeps register value immigration shift register selector switch to decide pulsewidth to keep the sampled value of register whether to move into the filtering shift register; If accumulated value is greater than the maximum limit amplitude, then the filtering accumulator will not upgraded by this accumulated value, and the filtering shift register does not carry out moving in and out of data yet; If accumulated value is less than the maximum limit amplitude, then the filtering accumulator is updated to this accumulated value, and the pulsewidth that samples keeps register value to move into the filtering shift register; Another road is sent into the accumulated value comparator and is compared, if greater than set point, and with regard to demodulation output 1, otherwise with regard to demodulation output 0.After the demodulation 0,1 logical signal are exported through the I/O output port of single-chip microcomputer.
See also Fig. 5, this is the electrical block diagram of modulating unit of the present invention.HART signal modulating unit 12 of the present invention comprises phase-accumulated value selector 121, adder 122, phase accumulator 123, phase-accumulated value determining device 124, single-chip microcomputer pin negate follower 125; Thereby described phase-accumulated value selector determines the size of phase-accumulated value with 0,1 logical signal that HART protocol signal link is resolved and command processor is exported in 1200 the baud rate reception single-chip microcomputer.Selected phase-accumulated value is added to phase accumulator every the very short time after adder, the value of phase accumulator outputs to phase-accumulated value determining device, after judging, phase-accumulated value determining device outputs to single-chip microcomputer pin negate follower: when phase accumulator is added to the π integral multiple, the negate of CPU pin level is once represented one time zero passage.From the frequency shift keying square wave of single-chip microcomputer pin negate follower output through HART signal medium medium transmission.
See also Fig. 6, Fig. 6 is the structural representation block diagram of the present invention when using.Single chip microcontroller 1 directly produces the FSK square wave of 1200Hz or 2200Hz on I/O, convert the HART protocol signal to through waveform shaping circuit 7 and be coupled on the transmission medium 9; Convert the FSK square wave of 1200Hz or 2200Hz from the HART protocol signal of transmission medium to through bandpass filtering shaping circuit 8, the I/O mouth of single chip microcontroller directly to this square wave frequency discrimination of sampling, demodulates 0,1 logical signal, and is sent by I/O.This 0,1 logical signal of being sent by the I/O mouth can directly be received by the serial ports of this single chip microcontroller oneself.Certainly, in some special application scenarios, this 0,1 logical signal of being sent by the I/O mouth also can be by the serial ports acceptance of a slice single-chip microcomputer in addition.The present invention saves expensive special chip, and development cost is reduced greatly.While is scalable and portable owing to the present invention has, and makes that this HART modulator-demodulator can be transplanted easily between different single chip microcontrollers.Therefore, use the exploration project of this HART modulator-demodulator can not be subjected to the restriction of market supply.
See also Fig. 7, this is the concrete embodiment schematic diagram of using of the present invention.
The present invention is based on the HART protocol signal modulation-demo-demodulation method of single-chip microcomputer, may further comprise the steps:
A, earlier the pin from single-chip microcomputer is input to HART signal modulating unit behind the translation keying square wave through becoming behind the bandpass filtering with the HART sine wave signal;
B, after the demodulation of HART signal modulating unit output logic " 0 ", " 1 " signal to I/O output port register;
C, logical zero, " 1 " signal are input to the asynchronous serial receiver module by the single-chip microcomputer pin;
D, asynchronous serial receiver module receive the HART communication frames through demodulation, deliver to parsing of HART protocol signal link and command processor again communication frames is carried out link parsing and command process, acquisition logical zero, " 1 " signal are delivered to the signal modulating unit and are carried out the signal modulation;
E, after demodulation, produce of the pin output of translation keying square wave, transfer out by output HART sine wave signal after the waveform shaping from single-chip microcomputer.
See also Fig. 8, this is the modulate circuit schematic diagram of received signal of the present invention, is made of band pass filter.This bandwidth-limited circuit comprises that the sinusoidal wave fsk signal of HART triggers via bandpass filtering, SMIT, is shaped as the square wave fsk signal consistent with the CPU operation level of corresponding frequencies.Signal conditioning circuit as shown in Figure 4, by being the bandwidth-limited circuit of core with IC201B and being that the SMIT circuits for triggering of core are formed with IC201A.So far, HART protocol signal reception work just becomes measurement and the corresponding logic identification to the square-wave signal pulsewidth.How the square wave fsk signal is sampled, 1200Hz and 2200Hz are demodulated into logical one, the 0th respectively, the key of the realization of the receiving demodulation of this software modem.Adopt an external interrupt that the edge detects in the reception program of the present invention, detected pulsewidth.This pulsewidth is exactly the current frequency that receives.But because link noise disturbs and the existence of HART signal transition waveform, the current frequency that receives is 1200Hz or 2200Hz accurately not necessarily, also just can't directly carry out logical one, 0 demodulation.Receiving algorithm of the present invention adopts the software filtering technology of forcing limiting technology (comprising minimum amplitude limit and maximum amplitude limit) and geometric average.
See also Fig. 9, the modulate circuit that the present invention sends signal is made of waveform shaping circuit.The realization of the transmission of modulator-demodulator of the present invention modulation is based on following such fact, and promptly the FSK square wave of 1200Hz or 2200Hz is exactly the HART signal after through the sincere sine wave of shape shaping circuit shaping.Among the present invention, such FSK square wave is directly produced with software program by microcontroller.The HART communication frames is made up of several characters, and each character is one 11 a byte: a start bit, eight bit data position, odd parity bit and position of rest.Character code as shown in figure 10.Byte press least significant bit the preceding order send.When sending a communication frames, the transmission between per two characters at interval (GAP) can not greater than a character time 9.167ms (character time be with 1200bps send character required time=11bits/1200bps=9.167ms).The transmission rate of HART agreement is 1200Hz, like this in a bit time, ' 1 ' signal (frequency the is 1200Hz) one-period of will passing by, ' 0 ' signal (frequency is 2200Hz) will be passed by 1+5/6 cycle, promptly send the phase difference that will produce one 60 degree after ' 0 '.Because the FSK frequency shift keyed signals keeps phase place continuous in when transmission, promptly between 1200Hz and 2200Hz during conversion phase place continuous, cause between 1200Hz and the 2200Hz converted-wave width indefinite.
The continuous FSK square wave of phase place mechanism of production is as follows: for one-period is the cycle of T, through one-period time T, its phase change 2 π.For certain equal portions time t, then its phase change is 2 π * t/T, if the equal portions time is fixed, then this phase change is a certain value, is made as W, and this definite value is corresponding to the cycle of certain frequency.Therefore, each π phase place is made up of several such W, one 16 phase accumulator is set, the phase accumulator W that adds up a time in each equal portions time t, software detects phase accumulator, when phase accumulator is added to the π integral multiple, (is that phase accumulator is added to the π integral multiple and is meant that accumulator overflows expression and arrives a π phase place,) decode the output pin upset once, represent one time zero passage.For the square wave of 1200Hz, W is a little bit smaller, and required number is just more, and just the number of t is more; For the square wave of 2200Hz, W more greatly, required number is just a little less, the number of t is also a little less.When transmission frequency changes, then need W is changed.The present invention utilizes the timer of a 1200bps to come each HART bit timing, determines that next bit is 0 or 1, thereby determines the accumulated value of accumulator.Represent phase place π with 65536 during realization, be respectively for 1200Hz and its definite value that adds up of 2200Hz:
W1200＝t*2*65536/T1200
W2200＝t*2*65536/T2200
Detected phase π only need detect overflowing of accumulator (with an int type data representation) and gets final product like this.
The phase error analysis that the FSK square wave produces: the inverse of phase change value W recited above is appreciated that into the resolution that phase place is exported after being multiplied by π, and this resolution reduces along with the increase of frequency.Cross null phase error: the resolution decision of this error size phase place output during by 2200Hz.Though there was null phase error, during owing to zero passage, the phase difference of existence continues on for adding up of next round, therefore can not produce owing to abandoning of phase difference produces accumulated error.The mode that adopts phase change to add up can guarantee the phase place continuation property of HART signal.
See also Figure 11, Figure 12, wherein, Figure 11 is the noise suppressed and the method for forcing minimum limiting technology during pulsewidth detects; Figure 12 is the geometric average software filtering and the method for forcing maximum limiting technology during pulsewidth detects.The pulsewidth that at every turn samples is put into a sampling keeps register.Set up a shift register and a filtering sampling timer.The filtering sampling timer is at regular intervals to maintenance register once sampling, and a value that samples moves into shift register one by one.Each value of shift register is added to the filtering accumulator.If the value of filtering accumulator greater than set point, with regard to demodulation output 1, otherwise exports 0 with regard to demodulation.Simultaneously the value of filtering accumulator is carried out maximum amplitude limit; If the value of filtering accumulator is greater than the maximum limit amplitude, then current maintenance register value does not move into shift register.Logical one after the process demodulation, the output pin that 0 signal advances microcontroller can directly be received by the serial port of microcontroller after exporting.The present invention adopts the highest priority interrupt Driving technique, guarantees real-time and accuracy to the demodulation of HART signal.
See also Figure 13, this is the FB(flow block) of router of the present invention.The present invention generates 11 transmission character with each HART character in router, carry out timed sending by the timer of 1200bps, and 11 send the back and send character late, distribute until frame data at once.
Its process is: after entering router, at first open carrier wave, then HART is sent byte and generate 11 transmission character and begin to send 11 characters, whenever send one and just just be ready for sending next bit, finish until 11 whole transmissions; Whether all bytes of judging frame data then distribute, if not, then program is returned " be written into HART and send byte, generates 11 transmission characters " and is located, and proceeds the transmission of HART byte.If frame data distribute, wait for that so carrier wave is closed after distributing in last position of last byte, send and finish.The 1200bps interrupt routine is used for determining that next byte is 0 or 1, thereby determines the size of accumulated value.Basic time, interrupt routine was used for adding up, overflow and judging and pin negate output of accumulator.
Claims (8)
1, SCM Based HART protocol signal modulator-demodulator, it is characterized in that, comprise a single-chip microcomputer, and HART signal demodulation unit, HART signal modulating unit and the I/O output port register, asynchronous serial receiver module, the HART protocol signal link that are arranged in this single-chip microcomputer are resolved and command processor; Described HART signal demodulation unit receives from the next signal of HART signal medium medium transmission, after demodulation, deliver to I/O output port register, by this I/O output port register transfer to the asynchronous serial receiver module, this asynchronous serial receiver module receives the HART communication frames through demodulation, delivering to parsing of HART protocol signal link and command processor again handles, acquisition logical zero, " 1 " signal are delivered to the signal modulating unit and are carried out the signal modulation, and the signal after the signal modulation is gone out by HART signal medium medium transmission again.
2, SCM Based HART protocol signal modulator-demodulator according to claim 1, it is characterized in that described HART signal demodulation unit comprises that marginal detector, maintenance register input selector switch, pulsewidth keep register, pulsewidth to keep register value to move into shift register selector switch, filtering shift register, adder-subtractor, accumulated value comparator, the maximum amplitude limiter of accumulated value, filtering accumulator;
Described marginal detector is used to detect the pulsewidth of the square wave on the CPU pin, and this pulsewidth is sent into maintenance register input selector switch;
Described maintenance register input selector switch is used to judge that pulsewidth that marginal detector sends into whether less than minimum pulse width, sends into a suitable pwm value pulsewidth then and keep register;
Described pulsewidth keeps register that this value is sent into 16 filtering accumulator and pulsewidth keeping planting and move into the shift register selector switch;
Described pulsewidth keeps register value to move into the selection that the shift register selector switch is used to move into and does not move into;
Described filtering shift register is used for moving in and out and depositing of pwm value;
Described filtering accumulator is used for adding up of pwm value, and this accumulated value is delivered to the accumulated value comparator;
Described accumulated value comparator is used for the comparison to filtering accumulated value size, thereby decision is defeated " 1 " or " 0 ";
The maximum amplitude limiter of described accumulated value is used for current filtering accumulated value is carried out maximum amplitude limit, and whether the value of control and decision filtering accumulator be updated, and the control pulsewidth keeps register value to move into shift register selector switch decision pulsewidth keeping the sampled value of register whether to move into the filtering shift register.
3, SCM Based HART protocol signal modulator-demodulator according to claim 1, it is characterized in that described HART signal modulating unit comprises phase-accumulated value selector, adder, phase accumulator, phase-accumulated value determining device, single-chip microcomputer pin negate follower; Thereby described phase-accumulated value selector determines the size of phase-accumulated value with 0,1 logical signal that HART protocol signal link is resolved and command processor is exported in 1200 the baud rate reception single-chip microcomputer.Selected phase-accumulated value is added to phase accumulator every the very short time after adder, the value of phase accumulator outputs to phase-accumulated value determining device, after judging, phase-accumulated value determining device outputs to single-chip microcomputer pin negate follower single-chip microcomputer pin negate follower: when phase accumulator is added to the π integral multiple, the negate of CPU pin level is once represented one time zero passage.From the frequency shift keying square wave of single-chip microcomputer pin negate follower output through HART signal medium medium transmission.
4, SCM Based HART protocol signal modulation-demo-demodulation method is characterized in that, may further comprise the steps:
A, earlier the pin from single-chip microcomputer is input to the HART signal demodulation unit behind the translation keying square wave through becoming behind the bandpass filtering with the HART sine wave signal;
B, after the demodulation of HART signal demodulation unit output logic " 0 ", " 1 " signal to I/O output port register;
C, logical zero, " 1 " signal are input to the asynchronous serial receiver module by the single-chip microcomputer pin;
D, asynchronous serial receiver module receive the HART communication frames through demodulation, deliver to parsing of HART protocol signal link and command processor again communication frames is carried out link parsing and command process, acquisition logical zero, " 1 " signal are delivered to the signal modulating unit and are carried out the signal modulation;
E, after demodulation, produce of the pin output of translation keying square wave, transfer out by output HART sine wave signal after the waveform shaping from single-chip microcomputer.
5, SCM Based HART protocol signal modulation-demo-demodulation method according to claim 4 is characterized in that, the described method through the demodulation of HART signal demodulation unit of step b may further comprise the steps:
B1, marginal detector receive the square-wave signal that transmission medium transmits, deliver to the maintenance register after testing after the pulsewidth by selector switch, deliver to pulsewidth again and keep register, if this pulsewidth is less than the minimum pulse width of setting, then minimum pulse width is put into pulsewidth and keeps register, realize minimum amplitude limit;
B2, keep register to sample with certain frequency to pulsewidth, each sampling back adds this sampled value with the value of filtering accumulator and deducts the value to be shifted out of filtering shift register, draws a new accumulated value in adder-subtractor;
B3, the new accumulated value that step b2 is drawn are divided into two-way:
One the tunnel sends into the maximum amplitude limiter of accumulated value and the maximum limit amplitude compares; Result relatively will control and determine whether the value of filtering accumulator is updated, and the control pulsewidth keeps register value immigration shift register selector switch to decide pulsewidth to keep the sampled value of register whether to move into the filtering shift register: if accumulated value is greater than the maximum limit amplitude, then the filtering accumulator will not upgraded by this accumulated value, and the filtering shift register does not carry out moving in and out of data yet; If accumulated value is less than the maximum limit amplitude, then the filtering accumulator is updated to this accumulated value, and the pulsewidth that samples keeps register value to move into the filtering shift register;
Another road is sent into the accumulated value comparator and is compared, if greater than set point, and with regard to demodulation output 1, otherwise with regard to demodulation output 0;
0,1 logical signal after b4, the demodulation is through the I/O output port output of single-chip microcomputer.
6, SCM Based HART protocol signal modulation-demo-demodulation method according to claim 4 is characterized in that, the described method through the modulation of HART signal modulating unit of steps d may further comprise the steps:
Thereby d1, phase-accumulated value selector determine the size of phase-accumulated value with 0,1 logical signal that HART protocol signal link is resolved and command processor is exported in 1200 the baud rate reception single-chip microcomputer;
D2, selected phase-accumulated value are added to phase accumulator every the very short time after adder;
The value of d3, phase accumulator outputs to phase-accumulated value determining device, output to single-chip microcomputer pin negate follower after phase-accumulated value determining device is judged, the frequency shift keying square wave after the modulation of single-chip microcomputer pin negate follower output is through HART signal medium medium transmission.
7, SCM Based HART protocol signal modulation-demo-demodulation method according to claim 6, it is characterized in that, steps d 3 described phase-accumulated value determining devices judgements are meant: when phase accumulator was added to the π integral multiple, the negate of single-chip microcomputer pin level was once represented one time zero passage; Otherwise, represent also not zero passage, level keeps.
8, SCM Based HART protocol signal modulation-demo-demodulation method according to claim 7 is characterized in that, described phase accumulator is added to the π integral multiple and is meant that accumulator overflows expression and arrives a π phase place.
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