CN102832242B - A kind of trench MOS structure semiconductor device and preparation method thereof - Google Patents
A kind of trench MOS structure semiconductor device and preparation method thereof Download PDFInfo
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- CN102832242B CN102832242B CN201110159093.9A CN201110159093A CN102832242B CN 102832242 B CN102832242 B CN 102832242B CN 201110159093 A CN201110159093 A CN 201110159093A CN 102832242 B CN102832242 B CN 102832242B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 238000001459 lithography Methods 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 14
- 238000005260 corrosion Methods 0.000 claims description 11
- 230000003628 erosive Effects 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N Silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005755 formation reaction Methods 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N oxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 description 12
- 239000002210 silicon-based material Substances 0.000 description 9
- 238000005036 potential barrier Methods 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000001413 cellular Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 210000002421 Cell Wall Anatomy 0.000 description 1
- 210000004027 cells Anatomy 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
Abstract
The invention discloses a kind of trench MOS structure semiconductor device, the growth of trench wall bottom has grid oxygen, polysilicon it is filled with in groove, being provided with body contact area, source region, body district and drain region in the silicon body of groove avris from top to bottom, the semiconductor device of the present invention is the base structure of super barrier rectifier；The present invention also provides for the preparation method of a kind of semiconductor device.The semiconductor device of the application present invention and preparation method, as a example by manufacturing super barrier rectifier, realize the manufacture of device, and improve the conducting current density of device not only by Twi-lithography technique.
Description
Technical field
The present invention relates to a kind of trench MOS structure semiconductor device, it is super barrier rectifier
Base structure, can be used to manufacture the semiconductor device such as super barrier rectifier, the invention still further relates to
A kind of preparation method of trench MOS structure semiconductor device.
Background technology
There is the semiconductor device of trench MOS structure, it has also become the important trend of device development, with
And constantly reduce the requirement of cost and requirement that electric current density is improved constantly by power device so that constantly
Minimizing cellular size and minimizing photoetching number of times become the development trend of device.
Conventional Super potential barrier commutation diode profile is as it is shown on figure 3, its base structure is groove
The semiconductor device of MOS structure has grid oxic horizon 5 as it is shown in figure 1, the whole inwall of groove grows,
Be filled with grid polycrystalline silicon 6 in groove, be provided with from top to bottom in the silicon body of groove avris source region 4,
Body district 3 and drain region 2, super potential barrier commutation diode processing technology comprises the steps: the first step,
Thermal oxidation technology is carried out on the surface of the N-type semiconductor silicon materials drift layer with N-type substrate layer 1
Form thermal oxide oxide layer 8, bottom drift layer, form device drain region 2；Second step, a photoetching corruption
Lose and remove thermal oxide oxide layer 8 on surface, trench area to be formed；3rd step, carries out silicon dry etching shape
Become groove；4th step, carries out grid oxygen oxidation technology, grows one layer of grid oxic horizon 5 at groove cell wall；
5th step, carries out polysilicon deposit, anti-carves polysilicon, forms grid polycrystalline silicon 6；6th step, enters
Row secondary photoetching corrosion, carries out boron impurity and injects diffusion propelling formation body district 3, and original drift layer is made
For drain region 2, formed while body district 3 in body district 3 superficial growth layer of oxide layer；7th step, three
Secondary photoetching corrosion is outputed source region and is injected window, is then injected into the impurity annealing of phosphorus source district and forms source region 4；The
Eight steps, four mask corrosion is outputed body district and is injected window, is then injected into the impurity annealing of body district and forms body district
Ohmic contact regions；9th step, five times photoetching corrosion removes surface oxide layer；Tenth step, deposition of electrode
Metal, six times photoetching corrosion anti-carves electrode metal, is formed as source region 4, grid polycrystalline silicon 6 and body district
The 3 upper surface metal levels 10 that current potential is provided；11st step, back face metalization, be formed as drain region 2 and carry
Lower surface metal layer 11 for current potential.
In traditional processing technology, there is polysilicon and return the risk beyond source electrode junction depth at the quarter in grid, it is impossible to
Ensure the performance of device；Third photo etching technique and four mask technique, the live width to photoetching process simultaneously
With alignment level, there is higher requirement.
Summary of the invention
The present invention is directed to the problems referred to above propose, it is provided that a kind of trench MOS structure semiconductor device and
Preparation method, this semiconductor device can be used to manufacture the semiconductor device such as super barrier rectifier.
A kind of trench MOS structure semiconductor device, it is characterised in that: including: multiple grooves are positioned at
First conductive type semiconductor material surface, the bottom of trench wall and the lower surface of sidewall are provided with
Dielectric, the top of trenched side-wall does not has dielectric, is filled with gate dielectric in groove；Groove
Between or slot wedge semi-conducting material top be provided with second conductive type semiconductor material constitute body
District, body district upper surface is provided with dielectric；Body district internal upper part and abut against groove to be provided with high concentration miscellaneous
The body contact area that second conductive type semiconductor material of matter doping is constituted；Body contact area it is positioned in body district
Bottom and abut against groove be provided with first conductive type semiconductor material constitute source region, and source region with
Between source region, semi-conducting material is body district；Body it is provided with from top to bottom in the semi-conducting material of groove avris
The drain region that contact area, source region, body district and the first conductive type semiconductor material are constituted；Platform between groove
Surface, face and device terminal body structure surface have identical dielectric；Metal level it is provided with even in device
Junctor district, source region and gate dielectric.
The preparation method of described groove vertical MOS structure semiconductor device, it is characterised in that: bag
Include following steps:
1) the first conductive type semiconductor material drift in the first conductive type semiconductor material substrate
The surface moving layer forms the first dielectric；
2) carrying out lithography corrosion process, semiconductor material surface removes the first dielectric of part；
3) the body district impurity implantation annealing of the second conduction type is carried out at semiconductor material surface；
4) carry out etching process, remove dielectric on surface, trench area to be formed, at formed window
Mouth region performs etching semi-conducting material, forms groove；
5) gate insulator medium is grown at trench wall；
6) carry out gate dielectric deposit, gate dielectric is etched back to, exposes trenched side-wall certain
Length dielectric, dielectric exposed to trenched side-wall corrodes；
7) the source region impurity of the first conduction type is carried out by trenched side-wall bare semiconductor material surface
Diffusion, in slot wedge semi-conducting material, top forms source region；
8) deposit the second dielectric, carries out dry etching, removes part the second dielectric,
In the first dielectric of trenched side-wall exposed portion, the first insulation of erosion removal trench sidewall surface
Medium；
9) the impurity diffusion of the second conduction type is carried out by trenched side-wall bare semiconductor material surface,
In slot wedge semi-conducting material, top forms body contact area；
10) erosion removal the second dielectric, the first insulation of erosion removal trench sidewall surface is situated between
Matter；
11) form metal on surface, carry out lithography corrosion process, remove surface portion metal；
12) carry out back side metallization technology, form metal overleaf.
The groove vertical MOS structure semiconductor device of the present invention, wherein source region uses Alignment Method
Realize, it is to avoid traditional processing technology is returned the risk carving grid polycrystalline silicon beyond source electrode junction depth, carries
The high reliability of device；Eliminate the domain surplus for lithographic line width and lithography registration, also reduce
The size of device cellular, improves the conducting current density of device.
The preparation method of the groove vertical MOS structure semiconductor device of the present invention is with the super gesture manufactured
As a example by building commutator, it is convenient to omit the second time photoetching work of conventional Super barrier rectifier manufacture method
Skill, for the third time photoetching process and four mask technique, the technique that present invention reduces photoetching production is wanted
Ask, production technology simpler production more compact structure, reduce the production cycle of device, reduce device
Production cost.
Accompanying drawing explanation
Fig. 1 is the generalized section of convention trench MOS structure semiconductor device.
Fig. 2 is that the trench MOS structure semiconductor device applications of the present invention is in manufacturing a kind of super potential barrier
The generalized section of commutation diode.
Fig. 3 is that convention trench MOS structure semiconductor device applications is in manufacturing super potential barrier rectification two pole
The generalized section of pipe.
Fig. 4 is the generalized section of one embodiment of the present invention technique second step.
Fig. 5 is the generalized section of one embodiment of the present invention technique the 3rd step.
Fig. 6 is the generalized section of one embodiment of the present invention technique the 5th step.
Fig. 7 is the generalized section of one embodiment of the present invention technique the 6th step.
Fig. 8 is the generalized section of one embodiment of the present invention technique the 6th step.
Fig. 9 is the generalized section of one embodiment of the present invention technique the 7th step..
Figure 10 is the generalized section of one embodiment of the present invention technique the 8th step.
Figure 11 is the generalized section of one embodiment of the present invention technique the 8th step.
Figure 12 is the generalized section of one embodiment of the present invention technique the 9th step.
Figure 13 is the generalized section of one embodiment of the present invention technique the tenth step.
Wherein, 1, substrate layer；2, drain region；3, body district；4, source region；5, grid oxic horizon；6、
Grid polycrystalline silicon；7, body contact area；8, thermal oxide oxide layer；9, silicon nitride；10, upper surface
Metal level；11, lower surface metal layer.
Detailed description of the invention
Embodiment 1
Fig. 2 is that the one of a kind of trench MOS structure semiconductor device manufacture of the application present invention is super
The generalized section of potential barrier commutation diode, describes the quasiconductor dress of the present invention in detail below in conjunction with Fig. 2
Put.
A kind of super potential barrier commutation diode, including: substrate layer 1, for N conductive type semiconductor silicon
Material, at substrate layer 1 lower surface, by lower surface metal layer 11 extraction electrode；Drain region 2, is positioned at
On substrate layer 1, for the semiconductor silicon material of N conduction type；Body district 3, is positioned on drain region 2,
Body district 3 is the semiconductor silicon material of P conduction type；Body contact area 7, be positioned at body district 3 upper surface it
In, for the semiconductor silicon material of the P conduction type of high concentration impurities doping；Source region 4 is positioned at body district 3
Among, for the semiconductor silicon material of N conduction type；Vertical trench is positioned at silicon body, its inner wall section
Growth has grid oxic horizon 5, is filled with grid polycrystalline silicon 6 in groove, in the silicon body of groove avris from
Upper toward being arranged with body contact area 7, source region 4, body district 3 and drain region 2；Device upper surface has upper table
Face metal level 10, draws another electrode for device.
Its processing technology comprises the steps:
The first step, enters on the surface of the N-type semiconductor silicon materials drift layer with N-type substrate layer 1
Row thermal oxidation technology forms thermal oxide oxide layer 8, forms device drain region 2 bottom drift layer；
Second step, carries out a lithography corrosion process, removes part at drift layer semiconductor material surface
Thermal oxide oxide layer 8, as shown in Figure 4；
3rd step, carries out boron impurity injection at exposed semiconductor material surface, is then diffused pushing away
Enter, form the body district 3 of device, as shown in Figure 5；
4th step, carries out etching process, removes thermal oxide oxide layer 8 on surface, trench area to be formed,
Perform etching semiconductor silicon material in formed window region, form groove；
5th step, at the growth grid oxic horizon 5 of trench wall, as shown in Figure 6；
6th step, is deposited grid polycrystalline silicon 6, is etched back to grid polycrystalline silicon 6, exposes
Trenched side-wall certain length grid oxic horizon 5, as it is shown in fig. 7, gate oxidation exposed to trenched side-wall
Layer 5 corrodes, as shown in Figure 8；
7th step, carries out phosphorus impurities diffusion, at groove by trenched side-wall bare semiconductor material surface
Gui Tinei top, edge forms source region 4, as shown in Figure 9；
8th step, deposit silicon nitride 9, carry out dry etching, remove partial silicon nitride 9, at groove
Sidewall exposed portion thermal oxide oxide layer 8, as shown in Figure 10, the hot oxygen of erosion removal trench sidewall surface
Change oxide layer 8, as shown in figure 11；
9th step, carries out boron impurity diffusion, at slot wedge by trenched side-wall bare silicon material surface
In silicon body, top forms body contact area 7, as shown in figure 12；
Tenth step, erosion removal silicon nitride 9, erosion removal trench sidewall surface thermal oxide oxide layer 8,
As shown in figure 13；
11st step, form metal on surface, carry out secondary lithography corrosion process, remove surface portion
Metal, forms device upper surface metal level 10；
12nd step, carries out back side metallization technology, forms metal overleaf, forms device lower surface
Metal level 11, as shown in Figure 2.
As it has been described above, use structure and the preparation method of embodiment 1, compared with prior art, subtract
Lack third photo etching technique, reduced production material cost, shorten the production cycle；On the other hand,
Source region and drain region lithography registration deviation need not be considered, it is not necessary to increase more than the domain being used for deviation of the alignment etc.
Amount, therefore compared with conventional super potential barrier commutation diode, can save single cell density, improves
Electric current density, it is achieved device miniaturization；Source region uses Alignment Method to be formed, it is to avoid traditional system
Make technique is returned the risk carving grid polycrystalline silicon beyond source electrode junction depth.
Elaborate the present invention by examples detailed above, other example can also be used to realize the present invention simultaneously,
The present invention is not limited to above-mentioned instantiation, and therefore the present invention is limited by scope.
Claims (8)
1. a trench MOS structure semiconductor device, it is characterised in that: including:
Multiple grooves are positioned at the first conductive type semiconductor material surface, the bottom of trench wall and sidewall
Lower surface be provided with dielectric, the top of trenched side-wall does not has dielectric, fills in groove
There is gate dielectric；
Between groove or slot wedge semi-conducting material top is provided with the second conductive type semiconductor material
Material constitutes body district, and body district upper surface is provided with dielectric；
Body district internal upper part and abut against groove be provided with high concentration impurities doping the second conduction type partly lead
The body contact area that body material is constituted；
It is positioned at bottom, body contact area in body district and abuts against groove and be provided with the first conductive type semiconductor material
The source region that material is constituted, and between source region and source region, semi-conducting material is body district；
Body contact area, source region, body district and it is provided with from top to bottom in the semi-conducting material of groove avris
The drain region that one conductive type semiconductor material is constituted；
Between groove, mesa surfaces is provided with dielectric, mesa surfaces and device terminal knot between groove
Structure surface has identical dielectric；
Metal level connector district, source region and gate dielectric it is provided with in device trenches.
2. semiconductor device as claimed in claim 1, it is characterised in that: described gate dielectric
For polysilicon.
3. semiconductor device as claimed in claim 1, it is characterised in that: described dielectric
It is the silicon dioxide of thermal oxidation technology formation.
4. semiconductor device as claimed in claim 1, it is characterised in that: described trenched side-wall
The top of dielectric is higher than the bottom of the source region of groove avris.
5. semiconductor device as claimed in claim 1, it is characterised in that: described groove is without absolutely
The sidewall of edge medium is as source region and the ohmic contact regions in body district.
6. the preparation method of trench MOS structure semiconductor device as claimed in claim 1, it is special
Levy and be: comprise the steps:
1) the first conductive type semiconductor material drift in the first conductive type semiconductor material substrate
The surface moving layer forms the first dielectric；
2) carrying out lithography corrosion process, semiconductor material surface removes the first dielectric of part；
3) the body district impurity implantation annealing of the second conduction type is carried out at semiconductor material surface；
4) carry out etching process, remove dielectric on surface, trench area to be formed, at formed window
Mouth region performs etching semi-conducting material, forms groove；
5) gate insulator medium is grown at trench wall；
6) carry out gate dielectric deposit, gate dielectric is etched back to, exposes trenched side-wall certain
Length dielectric, dielectric exposed to trenched side-wall corrodes；
7) the source region impurity of the first conduction type is carried out by trenched side-wall bare semiconductor material surface
Diffusion, in slot wedge semi-conducting material, top forms source region；
8) deposit the second dielectric, performs etching, and removes part the second dielectric,
The first dielectric of trenched side-wall exposed portion, the first insulation of erosion removal trench sidewall surface is situated between
Matter；
9) the impurity diffusion of the second conduction type is carried out by trenched side-wall bare semiconductor material surface,
In slot wedge semi-conducting material, top forms body contact area；
10) erosion removal the second dielectric, the first insulation of erosion removal trench sidewall surface is situated between
Matter；
11) form metal on surface, carry out lithography corrosion process, remove surface portion metal；
12) carry out back side metallization technology, form metal overleaf.
7. preparation method as claimed in claim 6, it is characterised in that: described gate dielectric
Etching is dry etching.
8. preparation method as claimed in claim 6, it is characterised in that: described the second insulation
Medium is silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110159093.9A CN102832242B (en) | 2011-06-13 | A kind of trench MOS structure semiconductor device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110159093.9A CN102832242B (en) | 2011-06-13 | A kind of trench MOS structure semiconductor device and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102832242A CN102832242A (en) | 2012-12-19 |
| CN102832242B true CN102832242B (en) | 2016-12-14 |
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Effective date of registration: 20210427 Address after: Room 301, 3rd floor, building 16, Guangxi Huike Technology Co., Ltd., No. 336, East extension of Beihai Avenue, Beihai Industrial Park, 536000, Guangxi Zhuang Autonomous Region Patentee after: Beihai Huike Semiconductor Technology Co.,Ltd. Address before: Hangzhou City, Zhejiang province Xiasha 310018 six Avenue nokaze Haitian city 27 Building 1 unit 2603 Patentee before: Zhu Jiang |