CN102820304A - Multibit non-volatile memory and operating method and forming method thereof - Google Patents
Multibit non-volatile memory and operating method and forming method thereof Download PDFInfo
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Abstract
The invention provides a multibit non-volatile memory and an operating method and a forming method of the multibit non-volatile memory. The memory comprises a semiconductor substrate; a groove formed in the semiconductor substrate; a source region and a drain region formed on the semiconductor substrate and located on both sides of the groove, wherein materials of the source region and the drain region comprise semiconductor materials with width of an energy gap smaller than that of silicon; and a grate structure formed between the source region and the drain region and formed in the groove, wherein the grate structure comprises tunneling dielectric layers formed on side walls of the source and drain regions and formed on the inner wall of the groove, charge capture layers formed on the tunneling dielectric layers, barrier dielectric layers formed on the charge capture layers and grates formed on the barrier dielectric layers. The non-volatile memory according to the embodiment of the invention has the advantages of low programming power consumption, large programming window, noninterference between two bits, rapid and efficient programming and high operating reliability of the apparatus.
Description
Technical field
The present invention relates to conductor device and technical field of integrated circuits, particularly a kind of multidigit nonvolatile memory and method of operation thereof and formation method.
Background technology
Utilize silicon nitride can be used to solve MIMIS (metal-insulator-metal-insulator-semiconductor as the multi-bit memory cell that electric charge capture layer constitutes; Metal-dielectric layer-metal-dielectric layer-semiconductor) the charge leakage problem in the storage organization improves the reliability of device stores greatly.Along with improve nonvolatile memory high density and jumbo requirement the consumption market, current technological level has got into the 2Xnm node, yet adopts littler device size to be faced with an increasing technology difficult problem.Therefore, (multi-level cell: many-valued storage) technology realizes the multidigit information stores in the single memory cell to need to adopt MLC.But because device size is less, still there is the increase of crosstalking between dibit in the multidigit memory technology, the problem that device fatigue properties and retention performance descend.
NROM and PHINES structure are two kinds of typical two memory cell structures.Wherein the NORM structure is owing to adopt CHE (channel hot electron injection: channel hot electron injects) mode to programme, and device is in opening during programming, and the big efficient of programming power consumption is low, and crosstalking of while device is bigger.Though and PHINES memory cell programming power consumption makes moderate progress; But it utilizes the mode that reads of short channel effect to limit the size of program window on the one hand; Also make two bit informations storing in the device electric charge capture layer when reading, produce serious crosstalking on the other hand, so the operating reliability of this device is relatively poor.In addition; The source-drain area of this device adopts silicon materials, because the energy gap of silicon is 1.119eV, the operating voltage that needs when adopting the band-to-band-tunneling method to programme is higher relatively; So the programming efficiency of device is lower, operation with high pressure simultaneously causes the device reliability variation.
Therefore; Along with reducing and the demand of market of device feature size, develop a kind of non-volatile memory device that is used for the multidigit storage low in energy consumption, that program window is big, program speed is fast, efficient is high, the device operation reliability is high and just seem particularly important for high density, mass storage device.
Summary of the invention
The object of the invention is intended to solve at least one of above-mentioned technological deficiency; A kind of multidigit nonvolatile memory and method of operation thereof and formation method particularly are provided, and existing multi-bit memory device program speed efficient is low, power consumption is high to solve, read between young and two bits of program window that voltage obtains and have the shortcoming of crosstalking.
For achieving the above object, first aspect present invention provides a kind of multidigit nonvolatile memory, and this memory comprises: Semiconductor substrate; Be formed on source region and drain region on the said Semiconductor substrate, the material in said source region and drain region comprises the semi-conducting material of energy gap less than said Semiconductor substrate; Be formed in the said Semiconductor substrate and the groove between said source region and drain region; With the grid structure that is formed in the said groove, said grid structure comprises: be formed on said trench wall tunneling medium layer, be formed on electric charge capture layer on the said tunneling medium layer, be formed on block media layer on the said electric charge capture layer, be formed on the grid on the said block media layer.
In one embodiment of the invention, the material of said Semiconductor substrate comprises silicon, and the material in said source region and drain region comprises germanium or germanium silicon.
In one embodiment of the invention, be formed with first kind doped well region in the said Semiconductor substrate, said groove is formed in the said first kind doped well region, and said source region and drain region are formed on the said first kind doped well region.
In one embodiment of the invention, the semiconductor substrate region near said channel bottom is the second type doped region.
Second aspect present invention provides a kind of method of operation of the multidigit nonvolatile memory according to first aspect present invention; This method comprises: programming operation; Comprise: said grid is applied first negative voltage; One of said source region or drain region are applied first positive voltage, make another the floating sky or the ground connection in said source region or drain region; Read operation comprises: said grid is applied second voltage, one of said source region or drain region are applied second positive voltage, make another ground connection in said source region or drain region; Erase operation comprises: said grid is applied the 3rd positive voltage, make floating sky in said source region and drain region or ground connection.
In one embodiment of the invention, in said programming operation, read operation and erase operation, said Semiconductor substrate ground connection.
In one embodiment of the invention, the scope of said first negative voltage is-and 4V is to-15V, and the scope of said first positive voltage is 2V to 6V.
In one embodiment of the invention, the scope of said second voltage is-5V to 5V that the scope of said second positive voltage is 1V to 4V.
In one embodiment of the invention, the scope of said the 3rd positive voltage is 5V to 20V.
Third aspect present invention provides a kind of formation method of multidigit nonvolatile memory, comprising: Semiconductor substrate is provided; On said Semiconductor substrate or in the said Semiconductor substrate, form source-drain layer, the material of said source-drain layer comprises the semi-conducting material of energy gap less than said Semiconductor substrate; Said source-drain layer of etching and said Semiconductor substrate are to form groove; With form tunneling medium layer at said trench wall, on said tunneling medium layer, form electric charge capture layer, on said electric charge capture layer, form the block media layer, on said block media layer, form grid.
In one embodiment of the invention, the material of said Semiconductor substrate comprises silicon, and the material in said source region and drain region comprises germanium or germanium silicon.
In one embodiment of the invention, forming said source-drain layer comprises: said Semiconductor substrate is carried out Ge-doped in said Semiconductor substrate, to form germanium silicon source-drain layer.
In one embodiment of the invention, before forming said source-drain layer, also comprise: said Semiconductor substrate is carried out the first kind mix, and said groove is formed in the said first kind doped well region with formation first kind doped well region.
In one embodiment of the invention, after forming said groove, also comprise: form the second type doped region in semiconductor substrate region near said channel bottom.
In one embodiment of the invention, form after the said source-drain layer, also comprise: said source-drain layer is carried out planarization.
In one embodiment of the invention, form after the said source-drain layer, also comprise: said source-drain layer is carried out planarization.
In one embodiment of the invention, the mode of the said source-drain layer of formation comprises on said Semiconductor substrate: deposit, epitaxial growth, rotary coating, evaporation and sputter.
The present invention provides a kind of multidigit nonvolatile memory and method of operation and formation method; Nonvolatile memory according to the embodiment of the invention; Adopt band-to-band-tunneling hot hole injecting principle to realize programming operation; Adopt the F-N tunnel to realize erase operation, have that programming power consumption is low, program window big, a glitch-free advantage between two bits.And through use energy gap less than the semi-conducting material of Semiconductor substrate as the source-drain area material, further improve program speed and efficient, and the operating reliability that improves device, thereby realize the low-voltage high-efficiency programming.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the section of structure of the multidigit nonvolatile memory of the embodiment of the invention;
Fig. 2 is each bias voltage sketch map during to the drain region information bit programming operation of the multidigit nonvolatile memory of the embodiment of the invention;
Fig. 3 be during to the drain region information bit programming operation of the multidigit nonvolatile memory of the embodiment of the invention before and after the injected hole of drain region the raceway groove band structure change sketch map;
Fig. 4 is along the band structure sketch map of drain region and tunnelling silicon dioxide layer direction during to the drain region information bit programming operation of the multidigit nonvolatile memory of the embodiment of the invention;
When Fig. 5 is the drain region information bit programming operation that has based on the multidigit nonvolatile memory of the source-drain area of silicon materials along the band structure sketch map of drain region and tunnelling silicon dioxide layer direction;
Fig. 6 is each bias voltage sketch map during to the drain region information bit read operation of the multidigit nonvolatile memory of the embodiment of the invention;
Fig. 7 is each bias voltage sketch map during to the source region of the multidigit nonvolatile memory of the embodiment of the invention and drain region information bit erase operation;
Shown in Figure 8 is the formation method flow diagram of the multidigit nonvolatile memory of the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
In description of the invention; It will be appreciated that; The orientation of indications such as term " " center ", " vertically ", " laterally ", " on ", D score, " preceding ", " back ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward " or position relation are for based on orientation shown in the drawings or position relation; only be to describe with simplifying for the ease of describing the present invention; rather than the device or the element of indication or hint indication must have specific orientation, with specific azimuth configuration and operation, therefore can not be interpreted as limitation of the present invention.
Fig. 1 is the section of structure of the multidigit nonvolatile memory of the embodiment of the invention.As shown in Figure 1; This memory comprises: Semiconductor substrate 411; Be formed on source region 408 and drain region 409 on the Semiconductor substrate 411, be formed in the Semiconductor substrate 411 and the groove 402 between source region 408 and drain region 409 and be formed on the grid structure in the groove 402.
In the present embodiment, the material of Semiconductor substrate 411 can be a silicon, and Semiconductor substrate 411 can be known P type or N type semiconductor substrate, can comprise the configuration of mixing alternatively, is for example mixed to form P trap or N trap by P type or N type.For the purpose of describing conveniently, in each embodiment of the present invention, be example with P type semiconductor substrate 411 with P trap 410.Those skilled in the art should understand that; Above-mentionedly only be used to explain the present invention for example, be not limited to protection scope of the present invention, for having the multidigit nonvolatile memory that forms on the N type semiconductor substrate of N trap; Can carry out with reference to the embodiment of the invention, repeat no more at this.
In the present embodiment, source region 408 is formed on the P trap 401 with drain region 409, and source region 408 is the information stores position with drain region 409 corresponding charge trapping regions, so this device is the nonvolatile memory that can be used for the dibit storage.Wherein, the material in source region 408 and drain region 409 comprises the semi-conducting material of energy gap less than silicon, for example germanium or germanium silicon.Should be understood that; In various embodiments of the present invention; As just example the present invention is described as the material in source region 408 and drain region 409 with germanium; Can not be interpreted as limitation of the present invention, any energy gap all is included in protection scope of the present invention less than the semi-conducting material of semiconductor substrate materials.The energy gap of germanium is 0.66eV, is 1.119eV less than the energy gap of silicon.Because the district 408 of device adopts the less semi-conducting material of energy gap with drain region 409; With compare as the device of source-drain area material with silicon, on the one hand, under identical operations voltage; More be easy to generate electron hole pair, help the raising of device programming speed and efficient; On the other hand,, then can adopt relatively low program voltage, help improving the reliability of device for identical programming efficiency.
Groove 402 can be rectangle, trapezoidal, shape of reverse omega, hemisphere or other shape.Present embodiment is an example with rectangle groove 402.Groove 402 is formed in the P trap 410 of Semiconductor substrate 411.In the preferred embodiment of the invention, also comprise N type doped region 403 in the Semiconductor substrate 411 near groove 402 bottoms, this N type doped region is a light dope, can the isolation source leaks the programming of two client informations and reads and crosstalk, and helps reading the increase of window.
The grid structure is formed in the space that is made up of the source region that promotes 408 and drain region 409 and recessed groove 402.The grid structure comprises: be formed on source region 408 and drain region 409 sidewalls and groove 402 inwalls tunneling medium layer 404, be formed on electric charge capture layer 405 on the tunneling medium layer 404, be formed on the block media layer 406 on the electric charge capture layer 405 and be formed on the grid 407 on the block media layer 406.In the present embodiment, the material of tunneling medium layer 404 can silicon dioxide; The material of electric charge capture layer 405 can be a silicon nitride; Block media layer 406 is used for block charge and between electric charge capture layer 405 and polysilicon gate 407, moves, and the material of block media layer 406 can be that silicon dioxide or other have the dielectric material of electric charge blocking capability; Grid 407 is used to control conducting and the disconnection between source region 408 and the drain region 409, and the material of grid 407 can be a polysilicon.Voltage on being applied to polysilicon gate 407 is during less than on state threshold voltage, the not conducting of two P type channel regions of groove 402 both sides, and this moment, this non-volatile memory device was not opened, and did not have electric current to flow through between source region 408 and the drain region 409; Voltage on being applied to polysilicon gate 407 is during greater than on state threshold voltage, and two P type channel region transoids of groove 402 both sides form N type communication channel, and this moment, this non-volatile memory device was opened.Wherein, said on state threshold voltage can be that positive voltage can be a negative voltage also, and receives the influence of programming operation and erase operation iunjected charge and change.
Below in conjunction with Fig. 2-7, programming operation, erase operation and the read operation bias voltage of the multidigit nonvolatile memory of the embodiment of the invention applied mode and can be with to distribute describe.
Fig. 2 is each bias voltage sketch map during to the drain region information bit programming operation of the multidigit nonvolatile memory of the embodiment of the invention.Programming operation is based on band-to-band-tunneling hot hole injection effect.In the present embodiment, each bias voltage is following in the programming operation: drain region 409 applies first positive voltage, preferably 2V to 6V; Source region 408 floating empty or ground connection; Polysilicon gate 407 applies first negative voltage, preferably-and 4V is to-15V; Semiconductor substrate 411 ground connection.
Fig. 3 be during to the drain region information bit programming operation of the multidigit nonvolatile memory of the embodiment of the invention before and after the injected hole of drain region the raceway groove band structure change sketch map.Shown in Fig. 3, E
C, E
F, E
VRepresent conduction level, Fermi level and valence-band level respectively.601 ' for injecting preceding hole change curve, 602 ' for injecting back cavitation change curve, the 603 ' variation for the voltage threshold of injected holes formation.Band structure shown in Figure 3 is the band structure of double arrowed line 604 ' institute's contoured regions.When drain region 409 applies positive voltage, when grid 407 connects higher negative voltage and substrate ground connection, set up a high longitudinal electric field at the crossover area in grid structure and drain region 409, the pn knot of drain junction and substrate then is biased under the high reverse landscape electric field.Under the acting in conjunction of longitudinal electric field and transverse electric field, being with of drain junction limit is bent upwards, and takes place to exhaust deeply.When band curvature amount during greater than the energy gap of germanium, electronics can pass through can be with to be tunneling to and form electron-hole pair in the conduction band in the valence band, and the band-to-band-tunneling effect has promptly taken place.The hole is injected in the silicon nitride layer 405 of 409 tops, drain region; Because the injection in hole can change by band along raceway groove; The part corresponding with the hole injection zone can be with downwarping, and the break-over of device threshold voltage reduces, thereby realized the programming operation of drain region information bit.What need explanation is, the programming operation of source region information bit with similar to the programming operation of drain region information bit, applied relation with the voltage in source region 408 and drain region 409 and exchanges and get final product, and repeats no more at this.
Fig. 4 be during to the drain region information bit programming operation of the multidigit nonvolatile memory of the embodiment of the invention along the drain region 409 with the band structure sketch map of tunnelling silicon dioxide layer 404 directions.Shown in Fig. 4, E
C, E
F, E
VRepresent conduction level, Fermi level and valence-band level respectively.Zone 601 for when programming tunnelling silicon dioxide layer 404 corresponding can regions, zone 602 during for programming drain region 409 corresponding can be with, zone 603 being with of silicon nitride layer 405 correspondences when programming.Band structure sketch map shown in Fig. 4 right-of-center in political views figure is corresponding to the 604 indicated zones of double arrowed line among the left figure.When can be with 602 amount of bow during greater than the energy gap of germanium, electronics can pass through the forbidden band and is tunneling to and forms electron-hole pair in the conduction band in the valence band, and the band-to-band-tunneling effect has promptly taken place.The electronics that band-to-band-tunneling produces will be collected and hole major part under the acceleration of pn knot transverse electric field can be crossed the interface and collected by substrate by drain region 409; Wherein lack the higher hole of portion of energy and under the attraction of gate regions electric field, can cross germanium/silicon dioxide potential barrier and be injected in the silicon nitride layer 405, the injection of band-to-band-tunneling hot hole has promptly taken place.Because the energy gap of germanium material is narrower, is merely 0.66eV, so the band curvature amount just enough produces the electron hole pair that is fit under low voltage, the band band can take place wear phenomenon then.Realize under this low pressure being with the method for wearing programming then, can reduce the electric field stress in the tunneling oxide layer, reduce generation of defects, thereby improved the retention performance and the fatigue properties of device.
When Fig. 5 is the drain region information bit programming operation that has based on the multidigit nonvolatile memory of the source-drain area of silicon materials along the band structure sketch map of drain region and tunnelling silicon dioxide layer direction.Be pointed out that; The multidigit nonvolatile memory similar that multidigit nonvolatile memory shown in Figure 5 and present embodiment shown in Figure 1 provide; Difference only is that the material of source-drain area (only showing drain region 109 among Fig. 5) is a silicon, so its concrete structure is repeated no more at this.As shown in Figure 5, E
C, E
F, E
VRepresent conduction level, Fermi level and valence-band level respectively.Zone 701 for when programming the tunnelling silicon dioxide layer corresponding can the region, zone 702 during for programming the drain region corresponding can be with, zone 703 being with of silicon nitride layer correspondence when programming.Band structure sketch map shown in Fig. 5 right-of-center in political views figure is corresponding to the 704 indicated zones of double arrowed line among the left figure.The silicon materials of energy gap greater than germanium are adopted in the source region of device and drain region, and energy gap is 1.119eV, is approximately the twice of germanium material.Fig. 4 and Fig. 5 contrast can be known, according to the multidigit nonvolatile memory of the embodiment of the invention, on the one hand, under identical program voltage, band-to-band-tunneling takes place more easily, it is right to produce more hot electron hole, helps the raising of device programming efficient and speed; On the other hand,, then can adopt relatively low program voltage, help improving the reliability of device for identical programming efficiency.Therefore can realize the programming operation of low-voltage high-efficiency according to the multidigit nonvolatile memory of the embodiment of the invention.
In addition; Because device is not opened when adopting the band-to-band-tunneling hot hole to inject; So power consumption is very little during device programming, two bits of device lay respectively at the groove both sides simultaneously, and have N type doped region 403 (being the N-district) to inject isolation; Can avoid crosstalking between dibit to a great extent, help reducing of device size.And the change of device threshold voltage places one's entire reliance upon injected holes to the effect of channel region surface level, thus can have the very big window that reads according to the device of the embodiment of the invention, thus improve the reliability of device operation.
Fig. 6 is each bias voltage sketch map during to the drain region information bit read operation of the multidigit nonvolatile memory of the embodiment of the invention.Read operation is based on reverse read.In the present embodiment, each bias voltage is following in the read operation: source region 408 applies second positive voltage, preferably 1V to 4V; Make drain region 409 ground connection; Polysilicon gate 407 applies second voltage, is preferably-5V to 5V; Semiconductor substrate 411 ground connection.Under the voltage bias condition that applies, source region 408 is owing to applied big positive voltage, so the information conductively-closed in source region 408 is fallen, the result that read this moment is drain region 409 canned datas.What need explanation is, the read operation of source region information bit with similar to the read operation of drain region information bit, applied relation with the voltage in source region 408 and drain region 409 and exchanges and get final product, and repeats no more at this.
Fig. 7 is each bias voltage sketch map during to the source region of the multidigit nonvolatile memory of the embodiment of the invention and drain region information bit erase operation.The erase operation method is based on raceway groove F-N tunneling effect.In the present embodiment, each bias voltage is following in the erase operation: source region 408 and drain region 409 ground connection; Polysilicon gate 407 applies the 3rd positive voltage, is preferably 5V to 20V; Semiconductor substrate 411 ground connection.In erase process, there is electronics to inject silicon nitride layer 405, cause device threshold voltage to raise, thereby realized the erase operation of source region and drain region information bit.
The embodiment of the invention further provides a kind of formation method of above-mentioned multidigit nonvolatile memory.Flow chart for this formation method shown in Figure 8, this method may further comprise the steps:
Step S01: Semiconductor substrate is provided.Preferably, Semiconductor substrate can be known P type or N type semiconductor substrate, can comprise the configuration of mixing alternatively, is for example mixed to form P trap or N trap by P type or N type.In the present embodiment, the material of Semiconductor substrate can be a silicon, and Semiconductor substrate is carried out the P type mix to form the P trap.
Step S02: on Semiconductor substrate or in the said Semiconductor substrate, form source-drain layer, the material of source-drain layer comprises the semi-conducting material of energy gap less than Semiconductor substrate.In the present embodiment, because the material of Semiconductor substrate is a silicon, so the material of source-drain layer can be chosen as germanium or germanium silicon.Material for Semiconductor substrate is a silicon, and the material of source-drain layer is the situation of germanium silicon, and the mode that forms source-drain layer can comprise: Semiconductor substrate is carried out Ge-doped in Semiconductor substrate, to form germanium silicon source-drain layer.In a further embodiment, can also pass through: modes such as deposit, epitaxial growth, rotary coating, evaporation and sputter form source-drain layer on Semiconductor substrate.Preferably, form after the source-drain layer, also comprise: source-drain layer is mixed, for example carry out N+ in the present embodiment and mix, can also carry out planarization to source-drain layer then, be beneficial to form source-drain area.
Step S03: etching source-drain layer and Semiconductor substrate are to form groove.The source-drain layer part that is positioned at the groove both sides promptly is respectively source region and drain region.Groove can be rectangle, trapezoidal, shape of reverse omega, hemisphere or other shape.Present embodiment is example with the rectangle groove.Groove is formed in the P trap of Semiconductor substrate.In the preferred embodiment of the invention, forming N type doped region near the semiconductor substrate region of channel bottom, this N type doped region can be a light dope, can isolate the programming of source-drain area two client informations and reads and crosstalk, and helps reading the increase of window.
Step S04: form tunneling medium layer at trench wall, on tunneling medium layer, form electric charge capture layer, on electric charge capture layer, form the block media layer, on the block media layer, form grid.The tunneling medium layer, electric charge capture layer, block media layer and the grid that are formed in the space that source-drain area and groove constitute constitute the grid structure.In the present embodiment, the material of tunneling medium layer can silicon dioxide; The material of electric charge capture layer can be a silicon nitride; The material of block media layer can be that silicon dioxide or other have the dielectric material of electric charge blocking capability; The material of grid can be a polysilicon.The formation of each layer can adopt conventional depositing technics to form in the grid structure, for example chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposit (PEALD) or additive method.
The present invention provides a kind of groove-shaped nonvolatile memory and method of operation and formation method that is used for the multidigit storage; Nonvolatile memory according to the embodiment of the invention; Adopt band-to-band-tunneling hot hole injecting principle to realize programming operation; Adopt the F-N tunnel to realize erase operation, have that programming power consumption is low, program window big, a glitch-free advantage between two bits.And through use energy gap less than the semi-conducting material of Semiconductor substrate as the source-drain area material, further improve program speed and efficient, and the operating reliability that improves device, thereby realize the low-voltage high-efficiency programming.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means the concrete characteristic, structure, material or the characteristics that combine this embodiment or example to describe and is contained at least one embodiment of the present invention or the example.In this manual, the schematic statement to above-mentioned term not necessarily refers to identical embodiment or example.And concrete characteristic, structure, material or the characteristics of description can combine with suitable manner in any one or more embodiment or example.
Although illustrated and described embodiments of the invention; For those of ordinary skill in the art; Be appreciated that under the situation that does not break away from principle of the present invention and spirit and can carry out multiple variation, modification, replacement and modification that scope of the present invention is accompanying claims and be equal to and limit to these embodiment.
Claims (16)
1. a multidigit nonvolatile memory is characterized in that, comprising:
Semiconductor substrate;
Be formed on source region and drain region on the said Semiconductor substrate, the material in said source region and drain region comprises the semi-conducting material of energy gap less than said Semiconductor substrate;
Be formed in the said Semiconductor substrate and the groove between said source region and drain region; With
Be formed on the grid structure in the said groove, said grid structure comprises: be formed on said trench wall tunneling medium layer, be formed on electric charge capture layer on the said tunneling medium layer, be formed on block media layer on the said electric charge capture layer, be formed on the grid on the said block media layer.
2. multidigit nonvolatile memory as claimed in claim 1 is characterized in that the material of said Semiconductor substrate comprises silicon, and the material in said source region and drain region comprises germanium or germanium silicon.
3. like claim 1 and 2 described multidigit nonvolatile memories; It is characterized in that; Be formed with first kind doped well region in the said Semiconductor substrate, said groove is formed in the said first kind doped well region, and said source region and drain region are formed on the said first kind doped well region.
4. like the described multidigit nonvolatile memory of claim 1-3, it is characterized in that, is the second type doped region near the semiconductor substrate region of said channel bottom.
5. the method for operation like each described multidigit nonvolatile memory of claim 1-4 is characterized in that, comprising:
Programming operation comprises: said grid is applied first negative voltage, one of said source region or drain region are applied first positive voltage, make another the floating sky or the ground connection in said source region or drain region;
Read operation comprises: said grid is applied second voltage, one of said source region or drain region are applied second positive voltage, make another ground connection in said source region or drain region;
Erase operation comprises: said grid is applied the 3rd positive voltage, make floating sky in said source region and drain region or ground connection.
6. the method for operation of multidigit nonvolatile memory as claimed in claim 5 is characterized in that, in said programming operation, read operation and erase operation, and said Semiconductor substrate ground connection.
7. the method for operation of multidigit nonvolatile memory as claimed in claim 6 is characterized in that, and the scope of said first negative voltage is-and 4V is to-15V, and the scope of said first positive voltage is 2V to 6V.
8. the method for operation of multidigit nonvolatile memory as claimed in claim 6 is characterized in that, the scope of said second voltage is-5V to 5V that the scope of said second positive voltage is 1V to 4V.
9. the method for operation of multidigit nonvolatile memory as claimed in claim 6 is characterized in that, the scope of said the 3rd positive voltage is 5V to 20V.
10. the formation method of a multidigit nonvolatile memory is characterized in that, comprising:
Semiconductor substrate is provided;
On said Semiconductor substrate or in the said Semiconductor substrate, form source-drain layer, the material of said source-drain layer comprises the semi-conducting material of energy gap less than said Semiconductor substrate;
Said source-drain layer of etching and said Semiconductor substrate are to form groove; With
Form tunneling medium layer at said trench wall, on said tunneling medium layer, form electric charge capture layer, on said electric charge capture layer, form the block media layer, on said block media layer, form grid.
11. the formation method of multidigit nonvolatile memory as claimed in claim 10 is characterized in that the material of said Semiconductor substrate comprises silicon, the material of said source-drain layer comprises germanium or germanium silicon.
12. the formation method of multidigit nonvolatile memory as claimed in claim 11 is characterized in that, forms said source-drain layer and comprises: said Semiconductor substrate is carried out Ge-doped in said Semiconductor substrate, to form germanium silicon source-drain layer.
13. the formation method of multidigit nonvolatile memory as claimed in claim 10; It is characterized in that; Before forming said source-drain layer; Also comprise: said Semiconductor substrate is carried out the first kind mix, and said groove is formed in the said first kind doped well region with formation first kind doped well region.
14. the formation method like claim 10 and 13 described multidigit nonvolatile memories is characterized in that, after forming said groove, also comprises: form the second type doped region in the semiconductor substrate region near said channel bottom.
15. the formation method of multidigit nonvolatile memory as claimed in claim 10 is characterized in that, forms after the said source-drain layer, also comprises: said source-drain layer is carried out planarization.
16. the formation method of multidigit nonvolatile memory as claimed in claim 10 is characterized in that, the mode that on said Semiconductor substrate, forms said source-drain layer comprises: deposit, epitaxial growth, rotary coating, evaporation and sputter.
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