CN100386883C - Non-volatile memory unit and its operating method and non-volatile internal memory - Google Patents
Non-volatile memory unit and its operating method and non-volatile internal memory Download PDFInfo
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- CN100386883C CN100386883C CNB2004101012040A CN200410101204A CN100386883C CN 100386883 C CN100386883 C CN 100386883C CN B2004101012040 A CNB2004101012040 A CN B2004101012040A CN 200410101204 A CN200410101204 A CN 200410101204A CN 100386883 C CN100386883 C CN 100386883C
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Abstract
The present invention relates to a non-volatile memory unit, which comprises a base, an electric charge trapping layer, a control grid, a source in first conduction state, a drain, a shallow doping region and a pocket doping region in second conduction state, wherein the electric charge trapping layer is on the base, the control grid is on the electric charge trapping layer, and dielectric layers are arranged between the base and the control grid and between the electric charge trapping layer and the control grid respectively. The source and the drain are respectively arranged in the base on both sides of the electric charge trapping layer, the shallow doping region is positioned on the surface of the base between the source and the electric charge trapping layer, and the pocket doping region is positioned in the base between the drain and the electric charge trapping layer. Because the present invention has asymmetric implanted structures with different electric conduction states, the programming speed of the memory unit can be accelerated, the disturbance of near memory units can be prevented, and the additional occupation area of bit-line selection transistors can be reduced.
Description
Technical field
The present invention relates to a kind of non-volatile memory device, and particularly relevant for a kind of non-volatile memory cells and method of operation and Nonvolatile memory that in non-volatile memory cells, forms asymmetric doped structure.
Background technology
In various Nonvolatile memory products, have can carry out repeatedly the depositing in of data, read, operation such as deletion, and the advantage that the data that deposits in also can not disappear after outage can electricity deletion and programmable read only memory (EEPROM), become extensively a kind of memory subassembly of employing of personal computer and electronic equipment institute.
Typically can electricity deletion and programmable read only memory be to make floating grid (floating gate) and control grid (control gate) with the polysilicon that mixes.When internal memory was programmed (program), the electronics that injects floating grid can be uniformly distributed among the whole polysilicon floating gate layer.Yet the tunnel oxide (tunneling oxide) below the polysilicon floating gate layer just causes the leakage current of assembly when defectiveness exists easily, influences the reliability of assembly.
Therefore, developed at present and a kind ofly borrowed hot hole to inject nitrogenize electron storage device so that the flash memory cell of programme (programming by hot hole injection nitride electron storage is abbreviated as PHINES), as Fig. 1.
Fig. 1 is the profile that illustrates known a kind of PHINES type flash memory cell, please refer to Fig. 1, this flash memory cell 10 is normally by source electrode 130a that is positioned at one on the substrate 100 control grid 120, substrate 100 and drain electrode 130b and control grid 120 and 110 on the silicon monoxide-silicon-nitride and silicon oxide layer (ONO layer) of 100 of substrates is formed, silica-silicon-nitride and silicon oxide layer (ONOlayer) the 110th wherein is made up of two-layer silicon oxide layer 112 and 116 folders, one silicon nitride layer 114, and silicon nitride layer 114 uses as charge immersing layer in this.
And the method for operation of the PHINES type flash memory cell of Fig. 1 mainly is to utilize locally can interband tunnelling hot hole (band to band tunneling hot hole, BTBT HH) to programme and utilize uniform raceway groove F-N (channel Fowler-Nordheim) to delete.
Though this PHINES type flash memory cell has advantages such as low power consumption, low electric leakage problem and simplification processing procedure, this memory cell still has some inevitable shortcoming.For instance, a PHINES type flash memory cell can respectively store a position in drain electrode and source side basically.Yet,, can when carrying out reverse reading (reverse read), produce second effect (2 if drain side has stored one
NdBit effect), (threshold voltage Vt) reduces, so need the high bias voltage that reads, but therefore causes the serious interference problem that reads and cause the reverse starting voltage that reads.Moreover PHINES type flash memory cell also has the slow problem of program speed to solve.In addition, general PHINES type flash memory cell need the three groups of bit line selection transistor that is used to programme (bit lineselection transistor, BLT), thus the big shortcoming of additional areas (overhead effect) had, and the density of storage array is diminished.
Summary of the invention
Purpose of the present invention is providing a kind of non-volatile memory cells exactly, increasing the program speed of memory cell, and prevents the interference between adjoining memory cell.
A further object of the present invention provides a kind of Nonvolatile memory, not only can increase the program speed of memory cell, also can reduce the shared additional areas of bit line selection transistor.
Another object of the present invention provides a kind of method of operation of Nonvolatile memory, can avoid complicated operations, and then reduces the number of bit line selection transistor.
The present invention proposes a kind of non-volatile memory cells, comprises a substrate, in the charge immersing layer on the substrate, at one on charge immersing layer control grid, at first dielectric layer between substrate and the charge immersing layer, second dielectric layer between control grid and charge immersing layer, source electrode and drain electrode, the shallow doped region of tool first conductive state and the pocket doped region of tool second conductive state of first conductive state.Wherein, source electrode is to lay respectively in the substrate of charge immersing layer both sides with drain electrode.And the shallow doped region of first conductive state is in the substrate between source electrode and charge immersing layer, and the pocket doped region of second conductive state then is in the substrate between drain electrode and charge immersing layer.
According to the described non-volatile memory cells of the first embodiment of the present invention, above-mentioned charge immersing layer can be silicon nitride layer or other material layers that is fit to.
According to the described non-volatile memory cells of the first embodiment of the present invention, above-mentioned first conductive state is that the N type and second conductive state are the P type.
The present invention reintroduces a kind of Nonvolatile memory, comprises several embedded type bit line of a substrate, first conductive state in substrate, on the substrate and across the character line of embedded type bit line, in the substrate between embedded type bit line and the charge immersing layer between the character line, at first dielectric layer between charge immersing layer and the substrate, second dielectric layer between character line and charge immersing layer, the shallow doped region of tool first conductive state and the pocket doped region of tool second conductive state.Wherein, shallow doped region is the substrate that is positioned at a side of each embedded type bit line, and the pocket doped region then is arranged in the substrate of the opposite side of each embedded type bit line.
According to the described Nonvolatile memory of the second embodiment of the present invention, above-mentioned charge immersing layer can be silicon nitride layer or other material layers that is fit to.
According to the described Nonvolatile memory of the second embodiment of the present invention, above-mentioned first conductive state is that the N type and second conductive state are the P type.
According to the described Nonvolatile memory of the second embodiment of the present invention, also comprise two bit line selection transistors, be electrical connected with embedded type bit line.
The present invention reintroduces a kind of method of operation of non-volatile memory cells, and wherein non-volatile memory cells comprises one first drain electrode of one first conductive state that is positioned at a substrate, one second drain electrode and one source pole, on substrate and across first, one character line of second drain electrode and source electrode, be positioned at first, substrate between second drain electrode and source electrode and several charge immersing layer between the character line, one first dielectric layer between each charge immersing layer and substrate, one second dielectric layer between character line and each charge immersing layer, a pocket doped region of one second conductive state that is positioned at a shallow doped region of each drain electrode and first conductive state of the substrate of a side of source electrode and is positioned at the opposite side of each drain electrode and source electrode.This method of operation comprises when carrying out a programming operation, apply one first bias voltage in character line, apply one second bias voltage in source electrode, and first drain electrode is floating state for ground state and second drains, wherein the magnitude of voltage of first bias voltage is lower than the magnitude of voltage of second bias voltage.
Method of operation according to the described non-volatile memory cells of the second embodiment of the present invention, also comprise when carrying out a deletion action, apply the bias voltage that is used for carrying out raceway groove F-N deletion at character line, first drain electrode is a ground state with source electrode, and second drain electrode is floating state.
Method of operation according to the described non-volatile memory cells of the second embodiment of the present invention, also comprise when carrying out a read operation, apply one the 3rd bias voltage, apply the voltage that is lower than the 3rd bias voltage relatively in first drain electrode at character line, source electrode is a ground state, and second drain electrode is floating state.
The present invention is applied to borrow hot hole to inject nitrogenize electron storage device so that the non-volatile memory cells of programming because of the implant infrastructure with asymmetric and different conductive states, therefore can increase program speed by the implant dosage that increases the pocket doped region, and can not lose reading capability.And, adopt the lower bias voltage that reads to read by the shallow doped region among the present invention via higher start voltage (Vt) raceway groove, more can prevent the interference that adjoining memory cell is caused because of programming.In addition, shallow doped region also can reduce channel hot electron (channel hot electron, generation CHE), and then reduce the distribution problem that reads during reverse the reading.Moreover structure of the present invention need not be provided with isolated line (isolationline) between memory cell, thereby can simplify programing system and circuit is oversimplified.In addition, because non-volatile memory cells of the present invention only need be controlled one group of bit line when programming, therefore also can reduce the shared additional areas of bit line selection transistor (BLT).For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the profile of known a kind of PHINES type flash memory cell.
Fig. 2 is the generalized section according to a kind of non-volatile memory cells of the first embodiment of the present invention.
Fig. 3 A is the circuit diagram according to a kind of Nonvolatile memory of the second embodiment of the present invention.
Fig. 3 B is the generalized section of the Nonvolatile memory of the B part shown in Fig. 3 A.
Fig. 3 C is the generalized section of another Nonvolatile memory of the B part shown in Fig. 3 A.
Symbol description
10: flash memory cell 20: non-volatile memory cells
100,200,300: substrate 110: silica-silicon-nitride and silicon oxide layer
112,116: silicon oxide layer 114: silicon nitride layer
120,220: control grid 130a, 230a: source electrode
130b, 230b: drain electrode 202,302: shallow doped region
204,304: pocket doped region 212,216,306,312,316: dielectric layer
214,314: charge immersing layer 320: character line
330: embedded type bit line 350: bit line selection transistor
Embodiment
According to the present invention, non-volatile memory cells and the method for operation and the Nonvolatile memory of a kind of " borrowing hot hole to inject nitrogenize electron storage device with programming (programming by hot hole injection nitride electron storage is abbreviated as PHINES) " are provided.
First embodiment
Fig. 2 is the generalized section according to the non-volatile memory cells of the first embodiment of the present invention.Please refer to Fig. 2, the non-volatile memory cells 20 of present embodiment comprises a substrate 200, be positioned at the charge immersing layer 214 on the substrate 200, be positioned at the control of one on the charge immersing layer 214 grid 220, first dielectric layer 212 between substrate 200 and charge immersing layer 214, second dielectric layer 216 between control grid 220 and charge immersing layer 214, the source electrode 230a of first conductive state and drain electrode 230b, the pocket doped region 204 of the shallow doped region 202 of tool first conductive state and tool second conductive state, wherein first conductive state for example is that the N type and second conductive state for example are the P types.And source electrode 230a lays respectively in the substrate 200 of charge immersing layer 214 both sides with drain electrode 230b, and can form a channel region (not illustrating) in the substrate 200 between source electrode 230a and drain electrode 230b.And the shallow doped region 202 of first conductive state is in the substrate 200 between source electrode 230a and charge immersing layer 214, and 204 of the pocket doped regions of second conductive state are in the substrate between drain electrode 230b and charge immersing layer 214.And described substrate 202 can comprise traditional semi-conducting material such as silicon, and charge immersing layer 214 can be silicon nitride layer or other material layers that is fit to.And first dielectric layer 212 and second dielectric layer 216 for example comprise silicon oxide layer or other material layers that is fit to, and also can be different material layers.
Please continue with reference to Fig. 2, when being presented at memory cell 20 among the figure and being programmed in charge immersing layer 214 distribution profile (distribution profile) in electronics and hole.The method of operation of the non-volatile memory cells 20 of Fig. 2 mainly is to utilize locally can interband tunnelling hot hole (BTBT HH) to programme and utilize uniform raceway groove F-N to delete.In addition, the memory cell 20 of present embodiment also can be applicable to (multi-bit-per-cell) system; That is to say, can by can interband the tunnelling hot hole on the right side of non-volatile memory cells 20 with the start voltage of multiple grade, to obtain more store statuss.For instance, the design of a kind of 4 kinds of grade start voltages (4-level Vt) can be produced the store status that each unit has 2.Yet described as can be known " left side " and " right side " be just according to the configuration of memory cell and fixed a kind of relative term, and this term can be replaced with the relative position of shallow doped region 202 and pocket doped region 204, and do not influence the function of memory cell.
When the memory cell 20 of present embodiment is operated in described PHINES mode, drain electrode 230b with pocket doped region 204 can promote energy interband tunnelling hot hole programming efficiency significantly and program speed is faster arranged under suitable bias voltage, the source electrode 230a with shallow doped region 202 then can suppress the generation of energy interband tunnelling hot hole.Therefore, non-volatile memory cells of the present invention will not need the known method that is used for suppressing the position.
In addition, the non-volatile memory cells 20 that present embodiment has an asymmetric doped structure can reach by the implant dosage that increases pocket doped region 204 and prevent that shallow doped region 202 from puncturing the problem of (punchthrough), and the while also can promote the program speed of memory cell in the lump.
Second embodiment
Fig. 3 A is the circuit diagram according to a kind of Nonvolatile memory of the second embodiment of the present invention; Fig. 3 B then is that generalized section, Fig. 3 C of the Nonvolatile memory of the B part shown in Fig. 3 A then is the generalized section of the another kind of Nonvolatile memory of the B part shown in Fig. 3 A.
Please earlier with reference to Fig. 3 A and Fig. 3 B, the Nonvolatile memory of present embodiment mainly is by a substrate 300, be positioned at several embedded type bit line 330 of first conductive state of substrate 300, on substrate 300 and across the character line 320 of embedded type bit line 330, in the substrate 300 of 330 of embedded type bit line and the charge immersing layer 314 between the character line 320, first dielectric layer 312 between charge immersing layer 314 and substrate 300, second dielectric layer 316 between character line 320 and charge immersing layer 314, the pocket doped region 304 of the shallow doped region 302 of tool first conductive state and tool second conductive state, wherein first conductive state for example is that the N type and second conductive state for example are the P types.And shallow doped region 304 is the substrates 300 that are positioned at a side of each embedded type bit line 330, and 304 of pocket doped regions are arranged in the substrate 300 of the opposite side of each embedded type bit line 330.
In addition, please refer to Fig. 3 B and Fig. 3 C, can between charge immersing layer 314 and character line 320, fill up dielectric layer 306, shown in Fig. 3 B, to completely cut off both; Or be shown in Fig. 3 C, charge immersing layer 314, first dielectric layer 312 and second dielectric layer 316 are extended on whole the substrate 300.
In addition,, in Fig. 3 A, also show two bit line selection transistors (BLT) 350, be electrical connected with embedded type bit line 330 and character line 320 in order to operate internal memory.
Please continue with reference to Fig. 3 A and Fig. 3 B, when wanting that the BS among the figure source electrode of embedded type bit line 330 (promptly as) left side carried out a programming operation, apply one first bias voltage at WL (being character line 320), and apply one second bias voltage in BS, BDL (promptly draining as first of embedded type bit line 330) is ground connection (ground) state, then for floating (floating) state, wherein the magnitude of voltage of first bias voltage is lower than the magnitude of voltage of second bias voltage to BDR (promptly draining as second of embedded type bit line 330).At the same time, the position on BS right side will be floating state and have the shallow doped region 304 of n type to be suppressed because of BDR.Yet aforesaid as can be known " left side " and " right side " be just according to the configuration of memory cell and fixed a kind of relative term, and this term can be replaced with the relative position of shallow doped region 302 and pocket doped region 304, and do not influence the function of memory cell.
When wanting that memory cell carried out deletion action, as long as apply in order to carrying out the bias voltage of raceway groove F-N deletion at WL, and to make BDL and BS be ground state, and BDR is a floating state.As a result, charge immersing layer 314 will be full of electronics.
When carrying out a read operation, can apply one the 3rd bias voltage in WL by reverse read method, and apply the voltage that is lower than the 3rd bias voltage relatively in BDL, can make BS simultaneously is ground state, and BDR still is a floating state.
Following table one is to use the magnitude of voltage of the bias voltage that the Nonvolatile memory of present embodiment operates.As shown in Table 1, only need two bit line selection transistors 350 to handle one group of character line WL and one group of bit line BS when programming operation is carried out in the interior existence of present embodiment, and the bias voltage of BDL is only needed can read than 1.6V is little.
Table one (unit: V)
| BDL | BS | BDR | WL | |
| The FN-deletion | 0 | 0 | Float | -20 |
| The HH-programming | 0 | 5 | Float | -5 |
| Read | ＜1.6 | 0 | Float | 5 |
In sum, be in characteristics of the present invention:
1. the present invention is applied to borrow hot hole to inject nitrogenize electron storage device so that the non-volatile memory cells of programming because of the implant infrastructure with asymmetric and different conductive states, therefore can increase program speed by the implant dosage that increases the pocket doped region, and can not lose reading capability, and because the introducing of shallow doped region more can prevent the interference that adjoining memory cell is caused because of programming.
2. the present invention adopts the lower bias voltage that reads by the shallow doped region in its structure, and can read via higher start voltage (Vt) raceway groove.In addition, shallow doped region also can reduce channel hot electron (channel hot electron, generation CHE), and then reduce the distribution problem that reads during reverse the reading.
3. structure of the present invention need not be provided with isolated line (isolation line) between memory cell, thereby can simplify programing system and circuit is oversimplified.
4. non-volatile memory cells of the present invention only need be controlled one group of bit line when programming, therefore also can reduce the shared additional areas of bit line selection transistor (BLT), and then increases the density of storage array.
Though the present invention with preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly has the knack of this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion according to the person of defining in the claim.
Claims (15)
1. non-volatile memory cells is characterized in that: comprising:
One substrate;
One charge immersing layer is positioned on this substrate;
One control grid is positioned on this charge immersing layer;
One first dielectric layer is between this substrate and charge immersing layer;
One second dielectric layer is between this control grid and charge immersing layer;
The one source pole of one first conductive state and a drain electrode lay respectively in the substrate of charge immersing layer both sides;
One shallow doped region of this first conductive state of tool is in the substrate between this source electrode and charge immersing layer; And
One pocket doped region of tool one second conductive state, in this substrate between this drain electrode and charge immersing layer, wherein, the degree of depth of the second conductive state pocket doped region is set for dark than the degree of depth of the shallow doped region of first conductive state.
2. non-volatile memory cells as claimed in claim 1 is characterized in that: this charge immersing layer comprises silicon nitride layer.
3. non-volatile memory cells as claimed in claim 1 is characterized in that: this first conductive state is the N type.
4. non-volatile memory cells as claimed in claim 1 is characterized in that: this second conductive state is the P type.
5. non-volatile memory cells as claimed in claim 1 is characterized in that: also comprising a channel region, is the substrate that is positioned between this source electrode and drain electrode.
6. Nonvolatile memory is characterized in that: comprising:
One substrate;
Most bar embedded type bit line of one first conductive state are positioned at this substrate;
Many character lines are on this substrate and across these embedded type bit line;
One charge immersing layer is at this substrate between this embedded type bit line respectively and respectively between this character line;
One first dielectric layer is between this charge immersing layer and this substrate;
One second dielectric layer is respectively between this character line and this charge immersing layer;
One shallow doped region of this first conductive state of tool is positioned at respectively this substrate of a side of this embedded type bit line; And
One pocket doped region of tool one second conductive state is arranged in respectively this substrate of the opposite side of this embedded type bit line, and wherein, the degree of depth of the second conductive state pocket doped region is set for dark than the degree of depth of the shallow doped region of first conductive state.
7. Nonvolatile memory as claimed in claim 6 is characterized in that: this charge immersing layer comprises silicon nitride layer.
8. Nonvolatile memory as claimed in claim 6 is characterized in that: this first conductive state is the N type.
9. as claim 6 a described Nonvolatile memory, it is characterized in that: this second conductive state is the P type.
10. Nonvolatile memory as claimed in claim 6 is characterized in that: also comprising a channel region, is this substrate that is positioned between these embedded type bit line.
11. Nonvolatile memory as claimed in claim 6 is characterized in that: also comprise two bit line selection transistors, be electrical connected with these embedded type bit line.
12. Nonvolatile memory as claimed in claim 6 is characterized in that: this charge immersing layer, this first dielectric layer and second dielectric layer also comprise on this substrate that extends whole.
13. the method for operation of a non-volatile memory cells, it is characterized in that: this non-volatile memory cells comprises first drain electrode of first conductive state that is positioned at a substrate, second drain electrode and the one source pole, on this substrate and across this first, one character line of second drain electrode and source electrode, be positioned at this first, this substrate between second drain electrode and source electrode and the charge immersing layer between this character line, one first dielectric layer between this charge immersing layer and this substrate, one second dielectric layer between this character line and this charge immersing layer, be positioned at each this first, one shallow doped region of this first conductive state in this substrate of second drain electrode and a side of source electrode and be positioned at each first, one pocket doped region of one second conductive state of the opposite side of second drain electrode and source electrode, this method of operation comprises:
When carrying out a programming operation, apply one first bias voltage at this character line, apply one second bias voltage at this source electrode, and first drain electrode is that ground state and this second drain electrode are floating state, wherein the magnitude of voltage of this first bias voltage is lower than the magnitude of voltage of this second bias voltage.
14. the method for operation of non-volatile memory cells as claimed in claim 13 is characterized in that: also comprise:
When carrying out a deletion action, apply the bias voltage of carrying out raceway groove F-N deletion at this character line, this first drain electrode is a ground state with source electrode, and second drain electrode is floating state.
15. the method for operation of non-volatile memory cells as claimed in claim 13 is characterized in that: also comprise:
When carrying out a read operation, apply one the 3rd bias voltage at character line, apply the voltage that is lower than the 3rd bias voltage relatively in this first drain electrode, this source electrode is a ground state, and second drain electrode is floating state.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6211011B1 (en) * | 1997-03-05 | 2001-04-03 | Macronix International Co., Ltd. | Method for fabricating asymmetric virtual ground P-channel flash cell |
| US6215148B1 (en) * | 1998-05-20 | 2001-04-10 | Saifun Semiconductors Ltd. | NROM cell with improved programming, erasing and cycling |
| US6482706B1 (en) * | 2001-12-10 | 2002-11-19 | Macronix International Co., Ltd. | Method to scale down device dimension using spacer to confine buried drain implant |
| US20020182829A1 (en) * | 2001-05-31 | 2002-12-05 | Chia-Hsing Chen | Method for forming nitride read only memory with indium pocket region |
| CN1393934A (en) * | 2001-06-25 | 2003-01-29 | 旺宏电子股份有限公司 | Flash memory structure |
| CN1421917A (en) * | 2001-11-28 | 2003-06-04 | 旺宏电子股份有限公司 | Manufacture of non-volatile memory |
| CN1424765A (en) * | 2001-12-11 | 2003-06-18 | 旺宏电子股份有限公司 | Non-valatile memory structure with nitride tunnel penetrating layer |
-
2004
- 2004-12-15 CN CNB2004101012040A patent/CN100386883C/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6211011B1 (en) * | 1997-03-05 | 2001-04-03 | Macronix International Co., Ltd. | Method for fabricating asymmetric virtual ground P-channel flash cell |
| US6215148B1 (en) * | 1998-05-20 | 2001-04-10 | Saifun Semiconductors Ltd. | NROM cell with improved programming, erasing and cycling |
| US20020182829A1 (en) * | 2001-05-31 | 2002-12-05 | Chia-Hsing Chen | Method for forming nitride read only memory with indium pocket region |
| CN1393934A (en) * | 2001-06-25 | 2003-01-29 | 旺宏电子股份有限公司 | Flash memory structure |
| CN1421917A (en) * | 2001-11-28 | 2003-06-04 | 旺宏电子股份有限公司 | Manufacture of non-volatile memory |
| US6482706B1 (en) * | 2001-12-10 | 2002-11-19 | Macronix International Co., Ltd. | Method to scale down device dimension using spacer to confine buried drain implant |
| CN1424765A (en) * | 2001-12-11 | 2003-06-18 | 旺宏电子股份有限公司 | Non-valatile memory structure with nitride tunnel penetrating layer |
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