CN108695338A - Vertical stacking memory device - Google Patents
Vertical stacking memory device Download PDFInfo
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- CN108695338A CN108695338A CN201810268318.6A CN201810268318A CN108695338A CN 108695338 A CN108695338 A CN 108695338A CN 201810268318 A CN201810268318 A CN 201810268318A CN 108695338 A CN108695338 A CN 108695338A
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
Vertical stacking memory device includes dope semiconductor substrates, and the dope semiconductor substrates have the low band gap layers for being applied with the public source of source electrode electric power and being spaced apart with public source, and the low band gap layers include low strap gap material.Stacked gate architectures have alternately and is vertically stacked at layer pattern between the gate electrode on substrate and insulation along first direction.Channel structure penetrates stacked gate architectures along first direction.Channel structure is contacted with low band gap layers.Charge storage structure is between stacked gate architectures and channel structure.Charge storage structure is configured to selectively store charge, and the charge of storage is supplied to storage unit, stacked gate architectures and channel structure.
Description
Cross reference to related applications
This application claims the South Korea patent application No.10-2017- submitted to Korean Intellectual Property Office on April 5th, 2017
The disclosure of 0044279 priority, this application is incorporated herein by being cited in full text.
Technical field
This disclosure relates to a kind of memory device, more particularly to a kind of vertical stacking memory device.
Background technology
NAND flash memory device usually stores data wherein by programming operation.It can be by erasing operation from flash memory device
It is middle to remove stored data.In plane nand flash memory memory device, data erasing operation is usually operated by bulk erasure
It executes, in bulk erasure operation, applies back bias voltage to the control grid of flash cell, and apply to the raceway groove of flash cell
Add positive bias.
However, in the vertical NAND flash memory device of the storage unit vertical stacking of plane nand memory part, pass through
Block erasing operation or GIDL erasing operations are wiped to execute data, this depends on the storage unit in vertical nand memory part
Stacked structure.According to GIDL erasing operations, multiple electron holes can be generated by grid induction drain leakage (GIDL) electric current,
And electron hole can be substituted by the charge in the electric charge capture layer of nand memory part.
Due to being provided with U-shaped unit string in single string by backgate so that vertical in BiCS (bit cost scaling) type
Bulk erasure operation is not executed in nand memory part, therefore the vertical nand memory of BiCS types is wiped by GIDL erasing operations
Cell data in part.On the contrary, because the vertical nand memory part of TCAT (too array of bit cells transistor) type have can be with
The separated raceway groove row of a pair for being connected to identical channel layer and a pair of of the unit string for being connected to corresponding raceway groove row, therefore pass through
GIDL erasing operations or block erasing operation erase the cell data in the vertical nand memory part of TCAT types.
Recently, since modern nand memory part is often vertical nand memory, GIDL erasing operations rather than batch
Amount erasing operation has been more widely used the data in erasing nand memory part.
Invention content
Vertical stacking memory device includes dope semiconductor substrates, and the dope semiconductor substrates, which have, is applied with source electrode electricity
The public source of power and the low band gap layers being spaced apart with public source, and the low band gap layers include low strap gap material.Heap
Folded gate structure has along first direction alternately and is vertically stacked at layer pattern between the gate electrode on substrate and insulation.Raceway groove
Structure penetrates stacked gate architectures along first direction.Channel structure is contacted with low band gap layers.Charge storage structure is between stacking gate
Between pole structure and channel structure, and selectively store charge.Gate electrode, channel structure corresponding with gate electrode and
Charge storage structure is configured in the storage unit of vertical stacking memory device.
Vertical stacking memory device is including with the doped semiconductor including the public source for being configured to receive source electrode electric power
Substrate.Stacked gate architectures have along first direction alternately and be vertically stacked at the gate electrode on substrate and insulation interbed figure
Case.Channel structure penetrates stacked gate architectures along first direction, and passes through the low band gaps through-hole pattern including low strap gap material
It is connected to substrate.Charge storage structure selectively stores charge between stacked gate architectures and channel structure.Grid
Electrode, charge storage structure and channel structure corresponding with gate electrode are configured to the storage list in vertical stacking memory device
In member.
Stacked memory devices include semiconductor substrate.Multiple storage units are vertically stacked in semiconductor substrate.Partly lead
Body substrate includes the public source for multiple storage units.Semiconductor substrate includes comprising one or more low strap gap materials
Low band gap layers.Stacked gate architectures setting is used for multiple storage units.Channel structure setting is used for multiple storage units.Charge is deposited
Storage structure is configured to storage charge, and the charge of storage is supplied to multiple storage units.
Description of the drawings
It is described in detail below so that becoming in terms of the disclosure and its many accompanyings when due to by reference to being considered in conjunction with the accompanying
It must be best understood from, therefore can obtain to the more complete understanding in terms of this disclosure and many accompanyings, in the accompanying drawings:
Fig. 1 is the perspective view for showing vertical stacking memory device according to an exemplary embodiment of the present invention;
Fig. 2 is the plan view for showing vertical stacking memory device shown in FIG. 1;
Fig. 3 is the cross-sectional view of the line I-I ' interceptions along Fig. 2;
Fig. 4 is the figure for the lattice structure for showing the low band gap layers at substrate and its borderline region;
Fig. 5 is the enlarged drawing for the charge storage structure for showing vertical stacking memory device shown in FIG. 1;
Fig. 6 is the first of the vertical stacking memory device shown in FIG. 1 for showing exemplary embodiment according to the present invention
The perspective view of variant;
Fig. 7 is the cross-sectional view intercepted along the bit line of vertical stacking memory device shown in fig. 6;
Fig. 8 is the second of the vertical stacking memory device shown in FIG. 1 for showing exemplary embodiment according to the present invention
The perspective view of variant;
Fig. 9 is the cross-sectional view intercepted along the bit line of vertical stacking memory device shown in Fig. 8;
Figure 10 is the enlarged drawing of the charge storage structure for the memory device for showing the second variant shown in Fig. 8;
Figure 11 is the third for the vertical stacking memory device shown in FIG. 1 for showing exemplary embodiment according to the present invention
The perspective view of variant;
Figure 12 is the cross-sectional view intercepted along the bit line of vertical stacking memory device shown in Figure 11.
Specific implementation mode
When describing the exemplary embodiment of the disclosure shown in the accompanying drawings, specific art is for the sake of clarity used
Language.However, the disclosure is not limited to the specific term so selected, and it is to be understood that each particular element includes with class
All technically equivalent ones operated like mode.In the whole instruction and attached drawing, identical reference numeral may refer to identical
Component.
Fig. 1 is the perspective view for showing vertical stacking memory device according to an exemplary embodiment of the present invention.Fig. 2 is to show
The plan view of vertical stacking memory device shown in FIG. 1.Fig. 3 is the cross-sectional view of the line I-I ' interceptions along Fig. 2.
Hereinafter, the vertical direction substantially upright with substrate is defined as first direction x, it will be substantially flat with substrate
Capable a pair of cross horizontal direction is defined as second direction y and third direction z.Second direction and third direction can substantially that
This is vertical.In addition, describing present inventive concept with reference to vertical NAND flash memory device herein.However, present inventive concept can also
Applied to any other memory device and vertical NAND flash memory device, as long as GIDL erasing operations can be used for wiping unit number
According to.
Referring to figs. 1 to Fig. 3, exemplary embodiment according to the present invention, vertical stacking memory device 1000 may include half
Conductor substrate 100, semiconductor substrate 100 are spaced apart with public source CS and doped with dopant with public source CS
Low band gap layers 110.Low band gap layers 110 include low strap gap material.Vertical stacking memory device 1000 further includes:Piled grids knot
Structure 200, have along first direction x alternately and be vertically stacked at the gate electrode on substrate and insulation interlayer pattern;Channel junction
Structure 300 penetrates stacked gate architectures 200 along first direction x and is contacted with low band gap layers 110;And charge storage structure
400, between stacked gate architectures 200 and channel structure 300.Charge storage structure 400 selectively stores charge, with heap
Folded gate structure 200 and channel structure 300 provide a store for the storage unit C of data together.Detaching groove ST can be along the
Three direction z extend on substrate 100, and multiple stacked gate architectures 200 can be by separation groove ST along second direction y points
From.Source electrode electric power can be applied to public source CS, and drain electrode electric power can be applied to channel structure 300.Bit line structure 500
It is connected to channel structure 300.Source electrode cable architecture can be connected to substrate 100 by detaching groove ST.
Substrate 100 may include the semiconductor substrate with default polarity type.For example, substrate 100 may include:Have
The silicon substrate of monocrystalline silicon or polysilicon (Si), SiGe (SiGe) substrate and silicon-on-insulator (SOI) substrate, it is all in SOI substrate
If the semiconductor layer of insulating layer and such as monocrystalline silicon layer or polysilicon layer on SiGe (SiGe) substrate, substrate is in the insulating layer
On.As being described in more detail below, according to the composition of low band gap layers 110, substrate 100 can have various the Nomenclature Composition and Structure of Complexes.
Public source CS and low band gap layers 110 can together be provided with substrate 100.It is default for having for public source CS
The dopant of polarity type can be entrained at the surface portion of substrate 100, and public source CS can be arranged in substrate
On 100.Source electrode electric power can be applied to public source CS.Low band gap layers 110 can also can be along second according to low band gap layers 110
The structure setting that direction y is spaced apart with public source CS is on substrate 100.
In an exemplary embodiment of the present invention, can by with polarity type impurity or dopant be injected into substrate
In surface portion that can be by detaching groove ST exposures in 100, thus formed on the bottom of separation groove ST public
Source electrode CS.Hereafter, separation groove ST can be filled with insulating materials, and thus insulation line pattern 600 can be along third direction z
Arrangement, and adjacent stacked gate architectures 200 can electricity be exhausted each other by detaching the insulation line pattern 600 in groove ST
Edge.
Public source CS can be formed as the line extended along third direction z.A pair of adjacent public source CS can pass through
The combination of stacked gate architectures 200 and channel structure 300 is separated from each other in a second direction.For example, dopant may include p-type
Impurity (for example, boron (B) and indium (In)) and p-type impurity (for example, phosphorus (P) and arsenic (As)).
Stacked gate architectures 200 can be detached by the insulation line pattern 600 detached in groove ST, and each stacking gate
Pole structure 200 may be used as the vertical unit string of vertical stacking memory device 1000 (for example, vertical NAND flash memory device).
Low band gap layers 110 can be arranged on substrate 100, and can be formed as the line extended along third direction z.Low strap
Gap layer 110 can be spaced apart with y in a second direction with public source CS.Low strap gap material can be injected into substrate 100
At the surface portion of 300 lower section of channel structure, thus low band gap layers 110 can be contacted with channel structure 300.Therefore, Ke Yitong
It crosses bit line structure 500 and applies drain electrode electric power to low band gap layers 110.
For example, raceway groove hole (H) can be disposed through stacked gate architectures 200, and can be in substrate 100
Low band gap layers are formed in the part that can be exposed by raceway groove hole H before filling raceway groove hole H with channel structure 300.It can lead to
Injection technology or depositing operation are crossed using low strap gap material to form low band gap layers 110.It can also be made by epitaxial growth technology
Low band gap layers 110 are formed with low strap gap material.It can be first on the bottom of raceway groove hole H (for example, logical in substrate 100
Cross raceway groove hole H and on the part of exposure) formed include low strap gap material seed layer, and selective epitaxial growth can be passed through
(SEG) Desired Height that technique grows into low band gap layers 110 along raceway groove hole H.
Band gap is the energy gap of the crystalline material with lattice structure between valence band and conduction band.Therefore, crystalline material
Band gap is used as electronics to be transferred to the conductive characteristic for determining crystalline material from the valence band of the insulation characterisitic of determining crystalline material
Conduction band energy barrier.When the band gap of crystalline material is sufficiently small, the electronics in valence band is easy to be moved in crystalline material
Conduction band, therefore crystalline material has conductive characteristic rather than insulation characterisitic.On the contrary, when the band gap of crystalline material is sufficiently large, valence
Electronics in band is difficult to be moved to conduction band in crystalline material, therefore crystalline material has insulation characterisitic rather than conductive characteristic.
As electronics is moved to conduction band in crystalline material from valence band, the quantity of free electron increases in conduction band, and electronics in valence band
The quantity in hole increases, this changes the conductive characteristic of crystalline material.It therefore, can be with when the band gap of crystalline material is sufficiently small
Relatively great amount of electrons and holes are generated under external power identical with crystalline material, and are used and be supplied to crystalline material
The external power of relatively small amount can generate sufficient amount of electrons and holes.
Low band gap layers 110 may include low strap gap material, and the electric power of relatively small amount (such as grid are used in low strap gap material
Pole induced drain leakage (GIDL) electric current), electronics can tend to be moved to conduction band from valence band.For example, low band gap layers 110 is low
Band gap material can be activated by GIDL electric currents, and can generate electron hole wherein.It is deposited only by vertical stacking
The electric power of the relatively small amount of the GIDL electric currents of memory device 1000 can generate sufficient amount of electron hole from low band gap layers 110.
Electron hole can be transferred to the charge storage structure 400 of selected storage unit, and can be from selected storage
Charge is eliminated in unit.For example, can be selected by being wiped from the electron hole that low band gap layers 110 generate by GIDL electric currents
Storage unit C numerical data.
Particularly because the band gap of low band gap layers 110 can be sufficiently small, therefore even if in vertical stacking memory device 1000
In, the intensity of drain electrode electric power and GIDL electric currents to channel structure 300 can be constant, it is possibility to have sufficient amount of electronics is empty
Cave.As a result, greater number of electron hole can be transferred to selected unit, and can be simultaneously by greater number of electricity
Lotus is combined with the electron hole in the charge storage structure 400 of selected unit, to improve vertical stacking memory device
The efficiency of GIDL erasing operations in 1000 selected unit.
Therefore, under the identical or constant drain electrode electric power of vertical stacking memory device 1000, the generation speed of electron hole
The efficiency of rate and GIDL erasing operations can increase.For example, appointing not increasing to the channel structure of vertical stacking memory device 1000
In the case of what electric power, the efficiency of erasing of vertical stacking memory device 1000 can increase.
For example, the example of the low strap gap material for low band gap layers 110 may include SiGe (SiGe), germanium (Ge), arsenic
Indium (InAs), gallium antimonide (GaSb) etc..These materials can be used alone or be applied in combination.
For example, low band gap layers 110 can be more than the lattice knot of the interatomic distance of substrate 100 with interatomic distance
Structure.Therefore, compression can be applied to the low band gap layers 110 at the borderline region between substrate 100 and low band gap layers 110,
It is possible thereby to reduce the effective mass of each electron hole by compression.Therefore, pass through vertical stacking memory device 1000
Identical control grid bias, a greater amount of electron holes can be transferred to selected unit, thus increase GIDL wipe
The transfer efficiency of electron hole in division operation.
Electrons and holes can be generated by the GIDL electric currents leaked from the drain electrode of ground connection selection transistor, the ground connection choosing
Select among the transistor that transistor is the unit string in vertical stacking memory device 1000 can be closest to the crystal of substrate 100
Pipe.
Therefore, low band gap layers 110 may substrate 100 surface portion everywhere under compression.
Fig. 4 is the diagram for the lattice structure for showing the low band gap layers at substrate and its borderline region.In Fig. 4, silicon
(Si) substrate may serve as substrate 100, and SiGe (SiGe) layer may serve as low band gap layers 110.However, the present invention is not
It is limited to this specific structure, and other materials can be used in substrate 100 and low band gap layers 110.
With reference to figure 4, since the interatomic distance d1 of the lattice structure of SiGe (SiGe) can be than the character structure of silicon (Si)
Interatomic distance d2 it is much bigger, therefore compression can be applied to adjacent silicon (Si) atom and germanium of low band gap layers 110
(Ge) between atom, and tensile stress can be applied in substrate 100 in the boundary of substrate 100 and low band gap layers 110
Between adjacent silicon (Si) atom at region.
Compression between adjacent silicon (Si) atom and germanium (Ge) atom of low band gap layers 110 can be to enable amount-dynamics
Scheme the shape distortion of (E-K figures), this can reduce the effective mass and band gap of the tunnels F-N charge.Therefore, GIDL electricity can be passed through
It flows and may also reduce from the effective mass for the electron hole that low band gap layers 110 generate due to compression, thus electron hole
It can be transferred to the charge storage structure 400 of selected unit in a relatively short period of time.For example, due to low band gap layers 110
The transfer efficiency of compression, electron hole can increase.
Therefore, because low band gaps can generate a greater amount of electron holes from low band gap layers 110, and control can be passed through
The interatomic distance of low band gap layers 110 increases the transfer efficiency of electron hole, thus improves vertical stacking memory device 1000
In GIDL erasing operations efficiency.
Multiple stacked gate architectures 200 can be described to be configured to deployment arrangements as follows on substrate 100:Phase
Adjacent stacked gate architectures 200 can be detached along second direction y with the insulation line pattern 600 detached in groove ST, and every
A stacked gate architectures 200 can extend along third direction z.Stacked gate architectures 200 may include gate structure 210 and surround
The insulating pattern 220 of gate structure 210, gate structure 210 and insulating pattern 220 can be alternately stacked into x along a first direction
On substrate 100.
Referring again to Fig. 1 to Fig. 3, gate structure 210 may include the multiple grid that can be vertically stacked on substrate 100
Electrode 211 to 216, and insulating pattern 220 may include multiple insulation for making gate electrode 211 to 216 be electrically insulated from each other
Between layer pattern 221 to 226.For example, layer pattern 221 can be arranged on substrate 100 between the first insulation, and first gate electrode is extremely
6th gate electrode 211 to 216 can between the second insulation layer pattern it is alternately vertical to layer pattern 222 to 226 between the 6th insulation
Ground is arranged between the first insulation on layer pattern 221.
For example, gate structure 210 may include doped silicon, low resistive metal (for example, tungsten (W), titanium (Ti), tantalum (Ta) and
Platinum (Pt)), metal nitride, metal silicide and combinations thereof.It can also be set between gate structure 210 and insulating pattern 220
Barrier layer (not shown) is set, to prevent the metal of gate structure 210 from spreading.
Although first gate electrode to the 6th gate electrode 211 to 216 can be stacked on substrate 100, there may be more
In or less than six gate electrodes be used as gate structure 210.The quantity of used gate electrode can depend on vertical heap
The performance and device property of folded memory device 1000.
First gate electrode 211 can be set to the gate electrode for being grounded selection transistor (GST), and the 6th grid electricity
Pole 216 can be set to the gate electrode for string select transistor (SST).Second gate electrode to the 5th gate electrode 212 to 215
It can be set to the gate electrode of cell transistor (CT).GST, CT and SST can vertically be connected cloth with x along a first direction
It sets, and can be arranged in the vertical unit string of the NAND flash memory device of vertical stacking.A pair of vertical unit string can be with ditch
Road structure 300 combines.
The gate electrode 211 to 216 of vertical stacking can be electrically insulated by insulating pattern 220.Layer pattern 221 between first insulation
It can be between substrate 100 and first gate electrode 211.Second insulation between layer pattern to the 6th insulation between layer pattern 222 to 226
It can be between the gate electrode of vertical stacking.Insulation interbed figure can be selected according to the used quantity for stacking gate electrode
The quantity of case.Insulating pattern 220 may include silica.
The thickness of layer pattern can be according to the device property and manufacture item of vertical stacking memory device 1000 between each insulation
Part and change.Particularly, layer pattern 221 can have than layer pattern between the second insulation to the 6th insulation interbed figure between the first insulation
The smaller thickness of thickness of case 222 to 226.
Channel structure 300 can extend through stacked gate architectures 200, and multiple channel structures 300 along first direction x
It can be arranged along third direction z according to identical clearance distance.Therefore, channel structure 300 can be set to along third party
To the raceway groove string (channel series) of z, and adjacent raceway groove string can be by detaching the insulation line pattern in groove ST
600 and be spaced apart.
The multiple raceway groove strings extended along third direction z can be separated from each other with y in a second direction.Multiple channel structures 300
It can with a matrix type be arranged on the surface limited by second direction y and third direction z, in vertical stacking memory
Channel array is set on the surfaces y-z of part 1000.
For example, channel structure 300 can fill the raceway groove hole H by gate structure 210 and insulating pattern 220, and reach
Low band gap layers 110.Therefore, the lower part of channel structure 300 can be contacted with low band gap layers 110, and the top of channel structure 300
It can be contacted with bit line structure 500.Can engagement pad 390 further be set on the top of channel structure 300, to reduce raceway groove
Contact resistance between structure 300 and bit line structure 500.
Channel structure 300 may include semiconductor layer 310, and semiconductor layer 310 may include semi-conducting material and can be with
It is arranged on the side wall of raceway groove hole H.Semiconductor layer 310 may include first layer 311 and the second layer that is arranged on first layer 311
312.First layer 311 can be contacted with charge storage structure 400, and the second layer 312 can be arranged on first layer 311.The
One layer of 311 spacer that may serve as covering charge storage structure 400, and the second layer 312 can cover first layer
311 and low band gap layers 110.Semiconductor layer 310 may include the silicon layer doped with dopant, and may serve as vertical stacking
The channel layer of memory device 1000.
Channel structure 300 can be formed the wherein cylindrical layer with central space.In this case, cylindrical
The central space of layer can be filled with insulation filler 380 (for example, silica-filled object).Alternatively, channel structure 300 can be with
It is formed the column for not having central space wherein.In this case, raceway groove hole H can be only filled with semiconductor layer 310.
The top of raceway groove hole H can be filled with the engagement pad 390 that can be contacted with bit line structure 500.Therefore, semiconductor layer
The contact area contacted with engagement pad 390 in 310 may be used as the drain junction region of non-vertical stacking memory device 1000.Half
The raceway groove that may serve as storage unit C with each adjacent channel region in gate electrode 211 to 216 in conductor layer 310
Layer, corresponding gate electrode may serve as control grid in the storage unit C.
Therefore, channel structure 300 can contact on top with bit line structure 500, and can be in lower part and low band gap layers
110 contacts.Low band gap layers 110 can be arranged in around the public source CS in substrate 100.Therefore, when can be to channel structure
When 300 applications are by drain electrode electric power, the application of low band gap layers 110 can be generated from the drain junction of the GST closest to substrate 100
GIDL electric currents, and the electron hole of sufficient amount can be generated from low band gap layers 110.
Reverse biased can be applied at least one of second gate electrode to the 5th gate electrode 212 to 215, and can be with
At least one of storage unit, which is selected as, to wipe the selecting unit of data from it.The electron hole of low band gap layers 110
It can be transferred to the charge storage structure 400 of selecting unit, and can be with the charge bonded in charge storage structure 400.
For example, can be by GIDL erasing operations using selecting unit can be wiped from the electron hole that low band gap layers 110 shift
Numerical data.
Particularly, due to low strap gap material, a greater amount of electron holes can be generated from low band gap layers 110, and due to
The transfer efficiency of the lattice structure of low band gap layers 110, electron hole to selecting unit can increase, this can fully improve perpendicular
The GIDL efficiency of erasing of straight stacked memory devices 1000.
Charge storage structure 400 can be between stacked gate architectures 200 and channel structure 300, and can pass through
Charge storage structure 400 selectively captures charge.
Fig. 5 is the enlarged drawing for the charge storage structure for showing vertical stacking memory device shown in FIG. 1.Particularly, Fig. 5
In the storage unit C of vertical stacking memory device 1000 is shown in detail.
With reference to figure 5, charge storage structure 400 may include:Barrier pattern 410 extends along first direction x and covers heap
Folded gate structure 200;Runnel insulator pattern 430 extends in a first direction and surrounds channel structure 300;Electric charge capture pattern
420, capture between barrier pattern 410 and runnel insulator pattern 430 and selectively charge.
Barrier pattern 410 may include the high dielectric layer with opposite high-k.For example, barrier pattern 410 can be with
Include the single layer comprising silica, aluminium oxide, hafnium oxide or high-g value or silicon oxide layer and high-k layer can be stacked wherein
Multilayer.
Electric charge capture pattern 420 can be contacted with barrier pattern 410, and can continuously or not be connected along first direction x
Continuous ground (intermittently) extends.It can be deposited selectively by electric charge capture in electric charge capture pattern 420 to program data into
In storage unit C.Charge can be selectively eliminated from electric charge capture pattern, to wipe data from storage unit C.Example
Such as, electric charge capture pattern 420 may include the nitride of such as silicon nitride and/or silicon oxynitride.
Runnel insulator pattern 430 can be contacted with the outer surface of channel structure 300, and can be extended along first direction x.
Therefore, runnel insulator pattern 430 can be formed the openable cylinder in bottom.Runnel insulator pattern 430 may include all
Such as the oxide of silica.
Gate electrode 211 to 216 can be electrically connected to one another in series between bit line structure 500 and source cable architecture, therefore grid electricity
The vertical string of pole 211 to 216 may serve as the individual unit string of vertical stacking memory device 1000, and the two of the individual unit string
End may be coupled to bit line structure 500 and source electrode cable architecture.Individual unit string may include a SST, a GST and can be with
The multiple CT contacted simultaneously with channel structure 300.
GST may include may be coupled to ground connection selection line (GSL) first gate electrode 211, and SST may include can
To be connected to the 6th gate electrode 216 of string selection line (SSL).CT may include the second gate electrode that may be coupled to wordline (WL)
To the 5th gate electrode 212 to 215.
Bit line structure 500 may include:Bit line plugs 510 are contacted with engagement pad 390;And bit line 520, it is inserted with bit line
510 contact of plug and y extensions in a second direction.
Public source CS can be arranged in the bottom of separation groove ST.Detaching groove ST and being filled with has vertical spacing
The insulation line pattern 600 of object 610 and device isolation pattern 620.Vertical spacing object 610 can extend along first direction x, and can
To cover stacked gate architectures 200.Vertical spacing object 610 may include insulating materials, for example, silica, silicon nitride, nitrogen oxidation
Silicon and aluminium oxide.These materials can be used alone or be applied in combination.In the separation groove ST limited by vertical spacing object 610
Portion space can be filled with device isolation pattern 620.
Source electrode cable architecture may include source electrode connectors 710 and be connected to the source electrode line 720 of source electrode connectors 710.Source electrode
Connectors 710 can extend through device isolation pattern 620 along first direction x, and can be contacted with public source CS.Source electrode
Line 720 can extend in 620 upper edge third direction z of device isolation pattern, and may be coupled to source electrode connectors 710.It is multiple
Source electrode line 720 can be connected to single common source polar curve CSL by source contact 721.Common source polar curve CSL can be along second party
Extend to y.
Multiple source electrode connectors 710 can along third direction z arranged in series, and can according to identical clearance distance that
This is spaced apart.For example, source electrode connectors 710 may include source electrode plug 711 and the source electrode barrier layer around source electrode plug 711
712。
Bit line 520 can be arranged in 720 top of source electrode line, and can be parallel with common source polar curve CSL along second party
Extend to y.
The leakage close to GST in substrate 100 can be arranged in exemplary embodiment according to the present invention, low band gap layers 110
At the surface portion in polar region domain, therefore the electronics that can generate sufficient amount from low band gap layers 110 by small GIDL electric currents is empty
Cave.Therefore, electron hole can be generated in the case where not increasing drain electrode electric power, and further amounts of electron hole can be passed
It is delivered to selecting unit, this can improve GIDL efficiency of erasing.
In addition, low band gap layers 110 may include the atom that interatomic distance can be more than periphery object (for example, substrate 100)
Between distance lattice structure, therefore can in low band gap layers 110 the atom of forntier region apply compression.Therefore, because
The effective mass of compression, electron hole can reduce, and under identical control grid bias, a greater amount of electron holes
It can be passed to selecting unit, thus improve GIDL efficiency of erasing.
Fig. 6 is the perspective view for the first variant for showing vertical stacking memory device shown in FIG. 1.Fig. 7 is along Fig. 6 institutes
The cross-sectional view of the bit line interception of the vertical stacking memory device shown.
In figure 6 and figure 7, the memory device 1001 of the first variant can have and 1000 essence of vertical stacking memory device
Upper identical structure, other than the low resistance pattern between low band gap layers 110 and channel structure 300.Therefore, in Fig. 6
In Fig. 7, identical reference numeral indicates the similar elements in Fig. 1, and will omit about any further of similar elements
Detailed description.
With reference to figure 6 and Fig. 7, the memory device 1001 of the first variant can also include can be between low band gap layers 110 and ditch
Low resistance pattern 150 between road structure 300.Therefore, can by low resistance pattern 150 fully reduce low band gap layers 110 with
Contact resistance between channel structure 300.
For example, low resistance pattern 150 may include the extension pattern in low band gap layers 110.It first can be in low band gap layers
Seed layer is formed on 110, then making low resistance pattern 150 by selective epitaxial growth (SEG) technique, x gives birth to along a first direction
Grow to Desired Height.The Nomenclature Composition and Structure of Complexes of low resistance pattern 150 can be according to the composition of low band gap layers 110 and channel structure 300
And channel structure 300 structure feature and change.
Here, low resistance pattern 150 may include monocrystalline silicon (Si) or single-crystal silicon Germanium (SiGe).When needed, Ke Yixuan
Selecting property some dopants are doped in low resistance pattern 150.Low resistance pattern 150 can be formed column, such as round
Column, cylindroid person rectangular column and pillars.
The height of low resistance pattern 150 can be controlled by the growth rate of SEG techniques.For example, low resistance pattern 150
Such height can be grown into:The upper surface of low resistance pattern 150 can be less than the bottom surface or second of the second gate electrode 212
The upper surface of layer pattern 222 between insulation.
For example, when low band gap layers 110 may serve as the seed layer for low resistance pattern 150, low resistance pattern 150
It can also include low strap gap material.In this case, low band gap layers 110 can substantially prolong in first gate electrode 211
It stretches, is used as the gate electrode of GST.
Therefore, the memory device 1001 of the first variant can provide more rich low strap gap material, and it is empty thus to improve electronics
The formation efficiency in cave.For example, the low band gap layers that the gate electrode of GST can be extended fully cover, and therefore in the first variant
Memory device 1001 in, GIDL erasing Operational Figure Of Merit can increase.
Fig. 8 is the perspective view for the second variant for showing vertical stacking memory device shown in FIG. 1.Fig. 9 is along Fig. 8 institutes
The cross-sectional view of the bit line interception of the vertical stacking memory device shown, and Figure 10 shows the second variant shown in Fig. 8
The enlarged drawing of the charge storage structure of memory device.For example, the memory device for the second variant being shown in detail in Figure 10 in Fig. 9
1002 storage unit C.
In figure 8 and figure 10, the memory device 1002 of the second variant can have and Fig. 6 and the first variant shown in Fig. 7
Substantially the same structure of memory device 1001, other than channel structure 300 includes low strap gap material.Therefore, Fig. 8 extremely
In Figure 10, identical reference numeral can indicate the similar elements in Fig. 6 and Fig. 7, and can it is assumed that these elements with
Through under the substantially identical degree of disclosed counter element, element is described in further detail in omission.
With reference to figure 8 to Figure 10, the memory device 1002 of the second variant may include low band gap channel 330, low band gap channel
330 may include low strap gap material and can be contacted with low resistance pattern 150.
For example, low band gap channel 330 may include semiconductor layer 331 and the low band gaps film that is arranged on semiconductor layer 331
332.Semiconductor layer 331 can extend along first direction x on the side wall of raceway groove hole H as follows:Charge storage structure 400
It can be covered by semiconductor layer 331, and low resistance pattern can be partially exposed by semiconductor layer 331.It can be with low strap
Low strap gap material can be deposited to semiconductor layer by gap material in a manner of fully covering semiconductor layer 331 and low resistance pattern 150
On 331, to form low band gaps film 332 on semiconductor layer 331 and low resistance pattern 150.Semiconductor layer 331 may include mixing
The miscellaneous silicon layer for having dopant, and low band gaps film 332 may include low strap gap material.
Therefore, semiconductor layer 331 may serve as the semiconductor for covering charge storage structure 400 along first direction x
Spacer, and low band gaps film 332 can be arranged on semiconductor isolation object and low resistance pattern 150.Low band gap channel 330 can
To function as the channel layer of the memory device 1002 of the second variant in the H of raceway groove hole.
Although disclosing the half of the memory device 1001 that can use 332 alternate figures 6 of band gap film and the first variant shown in Fig. 7
The second layer 312 of conductor layer 310, but Fig. 1 to vertical stacking memory device 1000 shown in fig. 5 semiconductor layer 310
Two layer 312 may include low strap gap material.
In this case, first layer 311 may include doped silicon layer, and the second layer 312 can be as low band gaps film
332 include low strap gap material like that.Therefore, low strap gap material can be utilized to cover first layer from the top-to-bottom of raceway groove hole H
311.Therefore, the channel structure 300 of vertical stacking memory device 1000 can also be arranged in the H of raceway groove hole extend to it is low
The low band gap channel of band gap layer 110.
Therefore, the channel structure 300 of vertical stacking memory device 1000 and the memory device 1001 of the first variant can wrap
Include low strap gap material.Low strap gap material for channel structure 300 can with the low band gaps material identicals of low band gap layers 110 or not
Together.When channel structure 300 includes low strap gap material identical with low band gap layers 110, low band gap layers 110 can substantially extend
To the top of raceway groove hole H.Therefore, a large amount of electron hole can be generated from low band gap layers 110 and low band gap channel 330, thus
Improve GIDL efficiency of erasing.
For example, when no insulation filler can use low strap gap material to fill raceway groove hole H, it can be by low strap
Gap raceway groove 330 is formed to the low band gaps pillars in the H of raceway groove hole, and due to a large amount of low strap gap material in the H of raceway groove hole,
GIDL efficiency of erasing can be improved substantially.
Figure 11 is the perspective view for the third variant for showing vertical stacking memory device shown in FIG. 1, and Figure 12 is edge
The cross-sectional view of the bit line interception of vertical stacking memory device shown in Figure 11.
In Figure 11 and Figure 12, the memory device 1003 of third variant may include being arranged in substrate 100 and channel structure
Low band gaps through-hole pattern 170 between 300, therefore the footprint area of the low strap gap material in memory device can be made to minimize,
To improve the integrated level of memory device.
With reference to figure 11 and Figure 12, the memory device 1003 of third variant may include doped with dopant and with can be with
It is applied in the semiconductor substrate 100 of the public source CS of source electrode electric power.Stacked gate architectures 200 can have along first direction x
Layer pattern alternately and between the gate electrode being vertically stacked on substrate 100 and insulation.Channel structure 300 is worn along first direction x
Saturating stacked gate architectures 200, and substrate 100 is connected to by the low band gaps through-hole pattern 170 including low strap gap material.Charge
Storage organization 400 is between stacked gate architectures 200 and channel structure 300.Charge storage structure 400 selectively stores electricity
Lotus, to provide enough electricity to the storage unit C for storing data together with stacked gate architectures 200 and channel structure 300
Lotus.
Low strap gap material can be arranged in the lower section of the channel structure 300 on substrate 100, be used as by channel structure
300 through-hole patterns 170 interconnected with substrate 100.The footprint area of low strap gap material can have the cross section surface with raceway groove hole H
Identical size.
Substrate 100, stacked gate architectures 200, channel structure 300 and charge storage structure 400 can have and Fig. 1 to figure
Substantially the same structure of element those of in vertical stacking memory device 1000 shown in 3, thus it can be assumed that:Substrate
100, stacked gate architectures 200, the detailed description of channel structure 300 and charge storage structure 400 and those described above counter element
It is substantially the same.
Substrate 100 can be partially exposed to penetrate the raceway groove hole H of stacked gate architectures 200, and seed layer can be with shape
At on the bottom of raceway groove hole H.Seed layer may include low strap gap material.
It is then possible to selective epitaxial growth (SEG) technique is executed to seed layer, it is desired to be realized in the H of raceway groove hole
Highly, to form low band gaps through-hole pattern 170 at the lower part of raceway groove hole H.
Low strap gap material can be downwards diffused into substrate 100 with SEG techniques, and low band gaps through-hole pattern 170
Lower part can expand in the surface portion of substrate 100, to form the expansion 172 of low band gaps through-hole pattern 170.Example
Such as, low band gaps through-hole pattern 170 can be formed can to grow up from the surface portion of substrate 100 in the H of raceway groove hole
Extension pattern.
Therefore, the surface profile of low band gaps through-hole pattern 170 can be with the substantial phase of surface profile of the side wall of raceway groove hole H
Together, and the footprint area of low strap material can be substantially the same with the cross section surface of raceway groove hole H.
The height that low band gaps through-hole pattern 170 is originated from substrate 100 can be by be at least similar to low resistance pattern 150
Mode control the process conditions of SEG techniques to change.
Low band gaps through-hole pattern 170 can also be identical with the low band gap layers of vertical stacking memory device 1,000 110 low
Band gap material.The example of low strap gap material for low band gaps through-hole pattern 170 may include SiGe (SiGe), germanium (Ge), arsenic
Change indium (InAs), gallium antimonide (GaSb) etc..These materials can be used alone or be applied in combination.
Therefore, can same drain electric power or do not increase drain electrode electric power in the case of from low band gaps through-hole pattern 170 produce
Raw larger amount of electron hole, the GIDL efficiency of erasing in memory device 1003 to improve third variant.For example, due to
The cross-sectional area of low band gaps through-hole pattern 170 can be identical as the cross section surface of raceway groove hole H, therefore from low band gaps through-hole figure
The transfer path of case 170 to the electron hole of selection cell can be shortened.Furthermore, it is possible to only by low in the H of raceway groove hole
The height of band gap through-hole pattern 170 is changed to control the hole density of low band gaps through-hole pattern 170.
In addition, the depth of the diffusion part 172 of low band gaps through-hole pattern 170 can reduce the effective mass of electron hole,
Therefore it is single from low band gaps through-hole pattern 170 to selection only electron hole can be controlled by changing the depth of diffusion part 172
The transfer efficiency of member.
When silicon (Si) substrate can be set to substrate 100, low band gaps through-hole pattern 170 can have such lattice
Structure:The interatomic distance of low band gaps through-hole pattern 170 can be bigger than the interatomic distance of silicon substrate.It therefore, can be in substrate
100 and low band gaps through-hole pattern 170 borderline region at compression is applied to low band gaps through-hole pattern 170, and electronics is empty
The effective mass in cave can be decreased sufficiently.
The borderline region of low band gaps through-hole pattern 170 can pass through the depth of the diffusion part 172 of low band gaps through-hole pattern 170
It spends and changes, therefore compression can be changed by diffusion part 172.
It therefore, can be logical to change the low band gaps in the H of raceway groove hole by controlling process conditions and the formation efficiency of SEG techniques
The depth of the height and diffusion part 172 of sectional hole patterns 170.The transfer efficiency of electron hole can pass through the low strap in the H of raceway groove hole
The height of gap through-hole pattern 170 and the depth of diffusion part 172 change.Therefore, it can control as follows for shape
At the process conditions of the SEG techniques of low band gaps through-hole pattern 170:Can farthest electronics be generated from low band gaps through-hole pattern
Hole, and electron hole can be transferred to selecting unit from low band gaps through-hole pattern 170 as quickly as possible, to improve third
GIDL efficiency of erasing in the memory device 1003 of variant.
The channel structure 300 contacted with low band gaps through-hole pattern 170 can also include as being described in detail with reference to figure 8 to Figure 10
Low strap gap material, this can improve GIDL efficiency of erasing.
In this case, the surface of the drain region close to GST in substrate 100 can be arranged in low band gap layers 110
At part, therefore the electron hole of sufficient amount can be generated from low band gap layers 110 by small GIDL electric currents.It therefore, can be with
Electron hole is generated in the case where not changing or not increasing drain electrode electric power, and further amounts of electron hole can be passed to
Selecting unit, this can improve GIDL efficiency of erasing.
In addition, low band gap layers 110, which may include interatomic distance, can be more than periphery object structure (for example, substrate 100)
The lattice structure of interatomic distance, therefore can be to applying compression in the atom of forntier region in low band gap layers 110.Therefore,
Due to compression, the effective mass of electron hole can reduce, and under identical control grid bias, a greater amount of electronics
Hole can be passed to selecting unit, thus improve GIDL efficiency of erasing.
Exemplary embodiment described herein is illustrative, and can be in the spirit that does not depart from the disclosure or appended
Many variations are introduced in the case of the scope of the claims.For example, in the scope of the disclosure and the accompanying claims, difference is shown
The element and/or feature of example property embodiment can be bonded to each other and/or substituted for one another.
Claims (20)
1. a kind of vertical stacking memory device, including:
Dope semiconductor substrates, the dope semiconductor substrates have be applied with source electrode electric power public source and with the public affairs
Common source low band gap layers spaced apart, and the low band gap layers include low strap gap material;
Stacked gate architectures have along first direction alternately and between the gate electrode being vertically stacked on the substrate and insulation
Layer pattern;
Channel structure penetrates the stacked gate architectures along the first direction, and the channel structure connects with the low band gap layers
It touches;And
Charge storage structure between the stacked gate architectures and the channel structure, and selectively stores charge
As memory data, the gate electrode and the channel structure corresponding with the gate electrode at and the charge storage
Structure is configured to the storage unit of the vertical stacking memory device.
2. vertical stacking memory device according to claim 1, wherein the low strap gap material of the low band gap layers by
Grid induction drain electrode leakage (GIDL) current activation, and the low strap gap material is configured to:Electron hole is generated, it will be produced
Electron hole be transferred to the storage unit, and wipe the charge in the storage unit.
3. vertical stacking memory device according to claim 2, wherein the low band gap layers are more than with interatomic distance
The lattice structure of the interatomic distance of the substrate so that pass through the borderline region between the substrate and the low band gap layers
The compression of the low band gap layers at place reduces the effective mass of the electron hole.
4. vertical stacking memory device according to claim 1, wherein the substrate includes silicon (Si), and the low strap
Gap layer includes being selected at least from the group being made of SiGe (SiGe), indium arsenide (InAs), gallium antimonide (GaSb) and combinations thereof
A kind of material.
5. vertical stacking memory device according to claim 1, wherein the channel structure includes semi-conducting material, and
It include one in the cylindrical layer and column that the stacked gate architectures extend to the low band gap layers.
6. vertical stacking memory device according to claim 5 further includes between the low band gap layers and the channel junction
Low resistance pattern between structure, the low resistance pattern are configured to reduce connecing between the channel structure and the low band gap layers
It gets an electric shock and hinders.
7. vertical stacking memory device according to claim 6, wherein the low resistance pattern includes outer by selectivity
The extension pattern that epitaxial growth (SEG) technique is formed.
8. vertical stacking memory device according to claim 6, wherein the low resistance pattern includes the low band gaps material
Material.
9. vertical stacking memory device according to claim 8, wherein the channel structure includes the low strap gap material.
10. a kind of vertical stacking memory device, including:
Dope semiconductor substrates have the public source for being configured to receive source electrode electric power;
Stacked gate architectures have along first direction alternately and between the gate electrode being vertically stacked on the substrate and insulation
Layer pattern;
Channel structure penetrates the stacked gate architectures, and the low strap by including low strap gap material along the first direction
Gap through-hole pattern is connected to the substrate;And
Charge storage structure between the stacked gate architectures and the channel structure, and selectively stores charge
As memory data, the gate electrode and the channel structure corresponding with the gate electrode and the charge storage knot
Structure is configured to the storage unit of the vertical stacking memory device.
11. vertical stacking memory device according to claim 10, wherein the low band gaps through-hole pattern extend to it is described
In substrate so that the low band gaps through-hole pattern is spaced apart with the public source in the substrate, and the low band gaps
The low strap gap material of through-hole pattern is by grid induction drain leakage (GIDL) current activation, and the low strap gap material is matched
It is set to:Electron hole is generated, generated electron hole is transferred to the storage unit, and wipe in the storage unit
The charge.
12. vertical stacking memory device according to claim 11, wherein the low band gaps pattern has interatomic distance
More than the lattice structure of the interatomic distance of the substrate so that by between the substrate and the low band gaps through-hole pattern
Borderline region at compression reduce the effective mass of the electron hole.
13. vertical stacking memory device according to claim 10, wherein the semiconductor substrate includes silicon (Si), and
The low band gaps through-hole pattern includes being formed from by SiGe (SiGe), indium arsenide (InAs), gallium antimonide (GaSb) and combinations thereof
At least one material selected in group.
14. vertical stacking memory device according to claim 10, wherein the low band gaps through-hole pattern includes passing through choosing
The extension pattern that the epitaxial growth of selecting property (SEG) technique is formed.
15. vertical stacking memory device according to claim 10, wherein the channel structure includes the low band gaps material
Material.
16. a kind of stacked storage part, including:
Semiconductor substrate;
Multiple storage units are vertically stacked in the semiconductor substrate, wherein the semiconductor substrate is included for described
The public source of multiple storage units, and the wherein described semiconductor substrate is included comprising the low of one or more low strap gap materials
Band gap layer;
Stacked gate architectures for the multiple storage unit;
Channel structure for the multiple storage unit;And
Charge storage structure is configured to:Charge is stored, and the charge of storage is supplied to the multiple storage unit.
17. stacked storage part according to claim 16, wherein the low band gap layers and the public source interval
It opens.
18. stacked storage part according to claim 16, wherein the stacked gate architectures include alternately and perpendicular
Directly stack layer pattern between multiple gate electrodes over the substrate and multiple insulation.
19. stacked storage part according to claim 16, wherein the channel structure penetrates the piled grids knot
Structure with the low band gap layers to contact.
20. stacked storage part according to claim 16, wherein the charge storage structure is between the stacking gate
Between pole structure and the channel structure.
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| KR1020170044279A KR102395987B1 (en) | 2017-04-05 | 2017-04-05 | Vertical stack memory device |
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Also Published As
| Publication number | Publication date |
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| KR102395987B1 (en) | 2022-05-10 |
| KR20180113069A (en) | 2018-10-15 |
| US20180294270A1 (en) | 2018-10-11 |
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