CN102820275A - 晶片级封装装置 - Google Patents

晶片级封装装置 Download PDF

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Publication number
CN102820275A
CN102820275A CN2012101842309A CN201210184230A CN102820275A CN 102820275 A CN102820275 A CN 102820275A CN 2012101842309 A CN2012101842309 A CN 2012101842309A CN 201210184230 A CN201210184230 A CN 201210184230A CN 102820275 A CN102820275 A CN 102820275A
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Prior art keywords
wafer
attached
projection
class encapsulation
encapsulation device
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CN2012101842309A
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CN102820275B (zh
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维贾伊·乌拉尔
阿尔卡迪·V·萨莫伊洛夫
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Maxim Integrated Products Inc
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Maxim Integrated Products Inc
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Abstract

本申请案涉及一种晶片级封装装置。所述晶片级封装装置的两个邻近附接凸块之间的最小距离小于所述两个邻近附接凸块之间的间距的约百分之二十五(25％)。两个邻近附接凸块之间的最小距离允许增加每面积的附接凸块的数目而不缩减凸块的大小，这增加了焊接可靠性。增加的焊接可靠性可缩减对附接凸块的应力，尤其是由在热循环试验期间的CTE失配、在跌落试验或循环弯曲试验期间的动态变形等等引起的应力。

Description

晶片级封装装置
技术领域
本申请案涉及一种半导体装置，且更明确地说，涉及晶片级封装半导体装置的制造。
背景技术
用于制造半导体装置的传统制作工艺使用微光刻以将集成电路图案化到由半导体(例如硅、砷化镓等等)形成的圆形晶片上。通常来说，经图案化的晶片被分割成个别集成电路芯片或裸片以使集成电路彼此分离。使用多种封装技术来组装或封装个别集成电路芯片以形成可安装到印刷电路板的半导体装置。
多年以来，封装技术已发展到用来开发更小的、更便宜的、更可靠的且对环境更无害的封装。举例来说，已开发出使用可直接表面安装封装的芯片尺度封装技术，可直接表面安装封装具有不大于集成电路芯片的面积的1.2倍的表面积。晶片级封装(WLP)为涵盖供在分割之前以晶片级来封装集成电路芯片的多种技术的芯片尺度封装技术。晶片级封装将晶片制作工艺扩展到包括装置互连和装置保护工艺。因此，晶片级封装通过允许使晶片制造、封装、试验和预烧工艺以晶片级集成而使制造工艺成流线型。
发明内容
本发明描述用于制作晶片级封装半导体装置的技术，晶片级封装半导体装置的两个邻近附接凸块(例如，焊料凸块)之间的最小距离小于两个邻近附接凸块之间的间距的约百分之二十五(25％)。两个邻近附接凸块之间的缩减的距离允许增加每单位面积的附接凸块的数目而不缩减凸块的大小，从而增加了焊接可靠性。增加的焊接可靠性可缩减对附接凸块的应力，尤其是由在热循环试验期间的CTE失配、在跌落试验或循环弯曲试验期间的动态变形等等引起的应力。
提供此发明内容以按简化形式引入概念的选择，所述概念在下文的具体实施方式中得以进一步描述。此发明内容既不意在识别所主张标的物的关键特征或本质特征，又不意在用于辅助确定所主张标的物的范围。
附图说明
参考附图来描述具体实施方式。在具体实施方式和附图的不同例子中使用相同的参考数字可指示相似或等同的项目。
图1是说明根据本发明的实例实施方案的晶片级封装装置的图解部分截面侧视图。
图2是说明根据本发明的另一实例实施方案的晶片级封装装置的图解部分截面侧视图，其中附接凸块包括核心。
图3是说明根据本发明的另一实例实施方案的晶片级封装装置的图解部分截面侧视图，其中附接凸块是围绕柱结构而形成。
图4是说明根据本发明的另一实例实施方案的晶片级封装装置的图解部分截面侧视图，其中分隔物形成在邻近附接凸块之间。
图5是说明用于制作柔性晶片级封装装置(例如图1所示的装置)的实例实施方案中的工艺的流程图。
图6到11是说明根据图5所示的工艺来制作柔性晶片级封装装置(例如图4所示的装置)的图解部分截面侧视图。
具体实施方式
概述
晶片级封装促进半导体装置的生产，与使用许多其它封装技术而制造的装置相比，所述半导体装置的成本更低、具有更小的形状因子且提供更低的寄生效应。然而，迄今为止，晶片级封装技术的应用仍限于用于使用小集成电路芯片的装置(例如，带有具有小于约5.5×5.5mm2的裸片尺寸的裸片的装置)的生产。对于使用较大芯片(例如，具有介于5.5×5.5mm2与7.0×7.0mm2之间的裸片尺寸)的装置，芯片与所述装置被安装到的印刷电路板(FR4)之间的热膨胀系数(CTE)的失配变得显著。在热循环试验期间，此失配可在用于将装置安装到印刷电路板的焊料凸块中引起高应力和裂缝。此外，在跌落试验和循环弯曲试验期间，归因于动态变形，相对高的焊料刚度可引起在焊料凸块与所述凸块的金属间化合物之间的界面处发生应力。
因此，本发明描述用于制作晶片级封装半导体装置的技术，晶片级封装半导体装置的两个邻近附接凸块(例如，焊料凸块)之间的最小距离小于两个邻近附接凸块之间的间距(例如，两个邻近凸块的中心之间的距离)的约百分之二十五(25％)。这归因于装置每单位面积的附接凸块的数目的增加而增加了焊接可靠性。增加的焊接可靠性缩减对装置的应力，尤其是由CTE失配(例如，装置与装置被安装到的印刷电路板之间的机械和热性质的失配)、在跌落试验或循环弯曲试验期间的动态变形等等引起的应力。因此，所述技术促进使用大集成电路芯片的晶片级封装装置(例如，使用具有大于约5.5×5.5mm2的裸片尺寸的裸片的装置)的制作。此类晶片级封装装置可用于多种应用，包括但不限于：芯片上系统(SOC)应用、动态随机存取存储器(DRAM)应用和中央处理单元(CPU)应用。
在实施方案中，晶片级封装(WLP)装置也可包括一个或一个以上分隔物，分隔物安置在邻近附接凸块之间以防止凸块在回流工艺期间迁移，且在所述装置连接到印刷电路板时提供机械稳健性。在一个或一个以上实施方案中，分隔物可由电介质材料(例如苯并环丁烯(BCB)聚合物等等)形成。装置可进一步包括悬垂部分，悬垂部分的宽度大于装置的间距。
实例实施方案
图1到4说明根据本发明的实例实施方案的晶片级封装(WLP)装置100。如图所示，晶片级封装装置100包括集成电路芯片102，集成电路芯片102包含包括附接凸块106的衬底104。衬底104是由晶片(例如硅晶片(例如p型晶片、n型晶片等等))制成，晶片包括形成在其中的一个或一个以上集成电路(未图示)。集成电路可由合适半导体形成技术形成，例如沉积、蚀刻、退火、光刻等等。一旦形成集成电路，其即经配置以向装置100提供功能性。集成电路可以多种方式进行配置。举例来说，集成电路可包含数字电路技术、模拟电路技术、复合信号技术等等。集成电路可连接到部署在集成电路芯片102(例如，衬底104)上方的一个或一个以上导电层，例如接触垫等等。这些导电层提供电触点，集成电路是通过电触点而互连到与装置100相关联的其它组件(例如，印刷电路板等等)。导电层(例如，接触垫)的数目和配置可取决于集成电路的复杂性和配置、集成电路芯片102的大小和形状等等而变化。衬底104可进一步包括形成在集成电路上方的一个或一个以上保护层(例如，钝化层、电介质层等等)，以在制造和使用期间提供对集成电路的保护。保护层可包含各种材料，例如苯并环丁烯聚合物(BCB)、二氧化硅(SiO2)等等。
如图1到4所说明，附接凸块106包含焊料凸块，焊料凸块在部署在集成电路芯片102上方的接触垫与形成在印刷电路板的表面上的对应垫(未图示)之间提供机械和/或电互连。在一个或一个以上实施方案中，附接凸块106可由无铅焊料(例如锡-银-铜(Sn-Ag-Cu)合金焊料(即，SAC)、锡-银(Sn-Ag)合金焊料、锡-铜(Sn-Cu)合金焊料等等)制成。然而，据预期，可使用锡-铅(PbSn)焊料。下文更详细地描述用于使用晶片级封装技术来形成附接凸块106的实例工艺。
可将凸块界面108施加到集成电路芯片102的接触垫，以在接触垫与附接凸块106之间提供可靠的互连边界。举例来说，在图1到4所示的晶片级封装装置100中，凸块界面108包含施加到集成电路芯片102的接触垫的凸块下金属化物(UBM)110。UBM 110可具有多种组成物。举例来说，UBM 110可包括不同金属(例如，铝(Al)、镍(Ni)、铜(Cu)、钒等等)的多个层，其充当粘附层、扩散势垒层、可焊接层、氧化势垒层等等。然而，可能存在其它UBM结构。
当一起观察时，附接凸块106和关联的凸块界面108(例如，UBM 110)包含凸块组合件112，凸块组合件112经配置以提供集成电路芯片102到印刷电路板的机械和/或电互连。如图1到4所说明，取决于各种设计考虑，晶片级封装装置100可包括凸块组合件112的一个或一个以上阵列114。
如图1到3所说明，凸块组合件112可以多种方式进行配置。在一实施方案中，如图1所说明，附接凸块106可包含焊料。
在另一实施方案中，如图2所说明，附接凸块106可包括被焊料包围的核心116。核心116可由各种材料形成，例如聚合物等等。在一个或一个以上实施方案中，可用金属层(例如，镍或铜)涂覆核心116的外表面以允许凸块106的焊料在回流工艺期间接合到核心116。核心116用来降低热机械应力，这消除了对底部填充工艺的需要，且增加了装置100在超过二百摄氏度(200℃)的温度下的机械稳定性。此外，核心116允许在回流之后界定附接凸块106的高度。
如图3所说明，附接凸块106也可围绕柱结构118而形成。在实施方案中，柱结构118可由一种或一种以上电介质材料制成，例如苯并环丁烯聚合物(BCB)、聚酰亚胺(PI)、聚苯并恶唑(PBO)等等。类似于上文所描述的核心116的结构，柱结构118经配置以增加装置100在超过二百摄氏度(200℃)的温度下的机械稳定性，且也允许在回流之后界定附接凸块106的高度。
如图4所说明，装置100可进一步包括形成在装置100的表面122上方的分隔物120。这些分隔物120可以多种方式进行配置。举例来说，分隔物120可由电介质材料形成，例如BCB。在一个或一个以上实施方案中，电介质材料可沉积在装置100上方且经选择性地蚀刻以形成分隔物120。分隔物120用来防止焊料迁移到相邻(例如，邻近)附接凸块106且使装置100短路。分隔物120也可用来向装置100提供机械支撑。在一个或一个以上实施方案中，附接凸块106的高度(H1)(在回流之后)大于分隔物120的高度(H2)，使得附接凸块106可连接到对应的PCB垫。然而，也可在晶片级封装之前通过一种或一种以上移除技术而移除分隔物120。举例来说，可在回流工艺之后通过化学蚀刻而移除分隔物120。据预期，可使用具有核心116(如图2所示)的附接凸块106来制作图4所示的装置100的实施方案。据进一步预期，可使用围绕一个或一个以上柱结构118(如图3所示)而形成的附接凸块106来制作图4所示的装置100的实施方案。
如图1到4所说明，装置100使用垫上凸块(“BOP”)配置，其中接触垫直接地接触凸块界面108(例如，UBM垫)。然而，据预期，装置100也可使用再分布层(“RDL”)配置。RDL配置包括再分布结构，再分布结构包含薄膜金属(例如，铝、铜)重布线和互连系统，所述系统将接触垫再分布到凸块界面108(例如，UBM垫)的面积阵列，凸块界面108可更均匀地部署在装置100上方。附接凸块106随后放置在这些凸块界面108上方以形成凸块组合件112。
根据本发明，包括在凸块组合件112的阵列114中的两个邻近附接凸块106之间的最小距离(D1)小于相同的两个邻近附接凸块之间的间距距离(D2)的约百分之二十五(25)。举例来说，如果两个邻近附接凸块106之间的间距(例如，间距距离)为0.4毫米(mm)，那么两个邻近附接凸块106之间的最小距离为约0.1mm或更小。在另一实例中，如果两个邻近附接凸块106之间的间距为0.35mm，那么两个邻近附接凸块106之间的最小距离为约0.0875mm。在这些实施方案中，附接凸块106的大小在直径方面可为约二百五十(250)微米(在附接凸块106的回流之前)。然而，可取决于晶片级装置100的设计要求而使用其它附接凸块大小。举例来说，在一些实施方案中附接凸块106的大小在直径方面可小于二百五十(250)微米，且在其它实施方案中附接凸块106的大小在直径方面可大于二百五十(250)微米。
带有直径为二百五十(250)微米的焊料凸块的典型WLP装置具有0.4mm的间距。然而，如上文所描述，装置100的间距可缩减到约0.35mm，同时仍然具有直径为约二百五十(250)微米的焊料凸块(例如，附接凸块106)。此间距缩减帮助缓解归因于在热循环试验期间的热膨胀系数(CTE)失配等等而发生的焊料疲劳。此外，间距缩减可增加每面积的附接凸块106的数目而不缩减凸块106的大小，这增强了焊接可靠性。据预期，应适当地选择装置100的制作参数以及对应的PCB垫尺寸以防止焊料在邻近位点处合并(例如，短路)。
在另一实施方案中，如图1所说明，装置100可包括延伸超过最外凸块组合件124的悬垂部分122A、122B。悬垂部分122A、122B向WLP装置100提供进一步的机械支撑和焊接可靠性。悬垂部分122A、122B经配置以延伸大于装置100的间距距离(D2)的距离(D3)。通常来说，悬垂部分仅延伸到大约间距距离而不需要虚设行的焊料凸块(例如，不具有关联的电互连的焊料凸块)。因此，装置100可仅包括由输入/输出要求和间距距离(D2)规定的凸块组合件112的最小阵列114。据预期，悬垂部分122A、122B为阵列114的大小的函数。据预期，阵列114可以M×N阵列进行排列(其中M≥1且N≥1)。在一实施方案中，带有0.35mm间距的10×10阵列可允许悬垂部分122A、122B各自延伸出0.7mm。在另一实施方案中，带有0.35mm间距的16×16阵列可允许悬垂部分122A、122B各自延伸出1.1mm。然而，据预期，可使用其它阵列配置，且悬垂部分122A、122B的尺寸将取决于这些阵列配置和装置100的要求(例如，附接凸块106的大小、间距等等)而变化。
据进一步预期，可在没有悬垂部分122A、122B的情况下设计和制作图1到4所示的装置100。因此，在一实施方案中，装置100的边缘126、128可延伸大致等于间距(D2)的距离。在另一实施方案中，边缘126、128可延伸小于间距(D2)的距离。
实例制作工艺
图5说明使用晶片级封装技术以制作半导体装置(例如图1到4所示的装置100)的实例工艺200。图6到11说明用于制作半导体装置300(例如图4所示的装置100)的实例半导体晶片的区段。在图6中，说明被分割成集成电路装置之前的装置300。据预期，装置300包含半导体晶片302，半导体晶片302包括形成在其中的一个或一个以上集成电路(未图示)。这些集成电路一起形成包含衬底306的集成电路芯片304。如上文所描述，集成电路可由合适半导体形成技术形成，例如沉积、蚀刻、退火、光刻等等。集成电路可包含数字电路技术、模拟电路技术、复合信号技术等等。集成电路连接到提供电触点的一个或一个以上导电层(例如，接触垫、再分布结构等等)，集成电路是通过电触点而互接到与装置300相关联的其它组件，例如印刷电路板等等。举例来说，如图6所说明，装置300包括定位在一个或一个以上集成电路上方的一个或一个以上接触垫308，以向集成电路提供电触点。
在晶片的表面上方形成电介质层(方块202)。举例来说，如图6所示，在晶片302的表面312上方形成电介质层310(例如，BCB材料、聚酰亚胺(PI)、聚苯并恶唑(PBO)等等)。可通过一种或一种以上合适沉积技术而形成电介质层310，例如物理气相沉积、化学气相沉积、分子束外延等等。
接着在晶片上方形成分隔物(方块204)。在一个或一个以上实施方案中，通过选择性地蚀刻电介质层310而形成图7所示的分隔物314。举例来说，可使用合适光刻技术来选择性地移除非所要的电介质层310的部分以形成分隔物314。据预期，光刻技术可使用干式蚀刻、湿式蚀刻等等来提供各向异性蚀刻以形成分隔物314。又据预期，可使用激光处理以形成分隔物314。据预期，沉积在表面312上方的电介质层310的量可为所要的分隔物314的高度的函数。
一旦已形成分隔物，即将凸块界面施加到集成电路芯片的接触垫(方块206)。在一个或一个以上实施方案中，凸块界面(例如，图8所示的凸块界面316)包含施加到装置300的接触垫308的UBM结构318。UBM 318可具有多种组成物。举例来说，UBM 318可包括不同金属(例如，铝(Al)、镍(Ni)、铜(Cu)等等)的多个层，其充当粘附层、扩散势垒层、可焊接层、氧化势垒层等等。然而，可能存在其它UBM结构。
将一个或一个以上附接凸块(例如，焊料凸块)定位在一个或一个以上凸块界面上方(方块208)。举例来说，附接凸块可由无铅焊料制成，例如锡-银-铜(Sn-Ag-Cu)合金焊料(即，SAC)、锡-银(Sn-Ag)合金焊料、锡-铜(Sn-Cu)合金焊料等等。如图9所示，附接凸块320定位在施加到集成电路芯片304的接触垫308的凸块界面316(例如UBM 318)上方。在一实施方案中，附接凸块320可包括如上文所描述且如图2所示的核心(例如，核心116)。在另一实施方案中，附接凸块320可围绕如上文所描述且如图3所示的柱结构(例如，柱结构118)而形成。
接着将附接凸块回流到凸块界面以形成凸块组合件(方块210)。在回流期间，晶片302经受受控制的热(例如，通过焊料回流炉)，所述热熔化附接凸块320，从而将焊料紧固到对应的凸块界面318(见图9)且形成凸块组合件322。如上文所描述，分隔物314用来防止焊料到相邻位点(例如邻近附接凸块320等等)的迁移，所述迁移可导致装置300短路。因此，分隔物314可允许在两个邻近附接凸块320之间的最小距离(D1)可小于两个邻近附接凸块320之间的间距距离的约百分之二十五(25％)的情况下制作装置300。举例来说，两个邻近附接凸块320之间的0.35mm的间距等于所述两个邻近附接凸块之间的约0.0875mm的最小距离值。此外，分隔物314可允许间距缩减，这增加了每面积的附接凸块320的数目而不缩减凸块320的大小。通常来说，具有二百五十(250)微米的预回流直径的焊料凸块可具有0.4mm的间距。然而，装置300可具有约0.35mm的间距，同时仍然具有预回流直径为二百五十(250)微米的焊料凸块(例如，附接凸块320)。据预期，可取决于WLP装置300的设计要求和特性而使用具有大于和小于二百五十(250)微米的预回流直径的焊料凸块。此外，装置300的间距(D2)也可相对于附接凸块320的预回流直径而变化，且因此，可依据凸块320的预回流直径而相应地调整每一装置300的间距(D2)。
在回流工艺之后，可从晶片移除分隔物(方块212)。在一个或一个以上实施方案中，装置300可经受蚀刻程序以移除分隔物314。举例来说，可使用一种或一种以上合适蚀刻技术以从晶片302移除分隔物314。然而，又据预期，在一个或一个以上实施方案中，可通过随后的晶片级封装步骤而在装置300上保留分隔物314，以向装置300提供进一步的机械支撑。如上文所描述，附接凸块320的高度可大于分隔物314的高度，使得附接球可与对应的印刷电路板垫(未图示)互连。
一旦晶片制作工艺完成，即可使用合适的晶片级封装工艺以将个别半导体装置分割且封装到至少一个晶片级封装半导体装置中(方块214)。在一个或一个以上实施方案中，已分割的半导体装置(例如，装置300)可包含晶片芯片尺度封装装置。此外，一旦制作装置300，其即可包括延伸超过最外凸块组合件322的一个或一个以上悬垂部分324A、324B。如关于图1所描述，悬垂部分324A、324B向WLP装置300提供进一步的机械支撑和焊接可靠性。在一个或一个以上实施方案中，悬垂部分324A、324B的距离(D3)大于间距(D2)。举例来说，悬垂部分324A的距离大于两个邻近附接凸块316之间的间距(D2)。然而，据预期，在其它实施方案中，悬垂部分324A、324B的距离可小于间距(D2)。
虽然图6到11说明使用BOP配置的装置300，但据进一步预期，装置300可使用RDL配置。RDL配置包括再分布结构，再分布结构包含薄膜金属(例如，铝、铜)重布线和互连系统，所述系统将接触垫(例如，接触垫308)再分布到凸块界面(例如，UBM垫)的面积阵列，凸块界面可更均匀地部署在WLP装置上方。
结论
虽然已使用为结构特征和/或工艺操作所特有的语言而描述标的物，但应理解，所附权利要求书中所界定的标的物未必限于上文所描述的特定特征或动作。相反地，上文所描述的特定特征和动作是作为实施权利要求书的实例形式予以揭示。

Claims (20)

1.一种晶片级封装装置，其包含：
集成电路芯片；和
多个附接凸块，其安置在所述集成电路芯片上，
其中所述多个附接凸块中的两个邻近附接凸块之间的最小距离小于所述两个邻近附接凸块之间的间距的约百分之二十五。
2.根据权利要求1所述的晶片级封装装置，其进一步包含具有大于所述间距的距离的悬垂部分。
3.根据权利要求1所述的晶片级封装装置，其中所述多个附接凸块中的每一附接凸块包括核心。
4.根据权利要求3所述的晶片级封装装置，其中所述核心包含聚合物核心。
5.根据权利要求1所述的晶片级封装装置，其中所述多个附接凸块中的每一附接凸块是围绕柱结构而形成。
6.根据权利要求5所述的晶片级封装装置，其中所述柱结构包含电介质材料。
7.根据权利要求1所述的晶片级封装装置，其中所述间距为约0.35mm且所述最小距离为约0.0875mm。
8.一种晶片级封装装置，其包含：
集成电路芯片；
多个附接凸块，其安置在所述集成电路芯片上；和
分隔物，其安置在所述多个附接凸块中的两个邻近附接凸块之间。
9.根据权利要求8所述的晶片级封装装置，其中所述两个邻近附接凸块之间的最小距离小于所述两个邻近附接凸块之间的间距的约百分之二十五。
10.根据权利要求8所述的晶片级封装装置，其中所述分隔物的高度小于所述两个邻近附接凸块中的一个附接凸块的高度。
11.根据权利要求8所述的晶片级封装装置，其进一步包含具有大于所述间距的距离的悬垂部分。
12.根据权利要求8所述的晶片级封装装置，其中所述分隔物包含电介质材料。
13.根据权利要求12所述的晶片级封装装置，其中所述电介质材料包含苯并环丁烯聚合物材料、聚酰亚胺材料或聚苯并恶唑材料中的至少一者。
14.根据权利要求8所述的晶片级封装装置，其中所述间距为约0.4mm且所述最小距离为约0.1mm。
15.一种方法，其包含：
接纳半导体晶片，所述半导体晶片经处理以在其中形成一个或一个以上集成电路，所述半导体晶片包括部署在所述半导体晶片的表面上方的多个接触垫；
在所述半导体晶片的所述表面上方形成一个或一个以上分隔物以防止焊料迁移；
将凸块界面施加到所述多个接触垫中的每一接触垫；和
使附接凸块在每一凸块界面上方回流，
其中两个邻近附接凸块之间的最小距离小于所述两个邻近附接凸块之间的间距的约百分之二十五。
16.根据权利要求15所述的方法，其中形成一个或一个以上分隔物进一步包含：
在所述半导体晶片的所述表面上方沉积电介质层；和
选择性地蚀刻所述电介质层的非所要部分以形成所述一个或一个以上分隔物。
17.根据权利要求16所述的方法，其中所述电介质材料包含苯并环丁烯聚合物材料。
18.根据权利要求16所述的方法，其中所述选择性地蚀刻包含各向异性地蚀刻所述电介质层的所述非所要部分以形成所述一个或一个以上分隔物。
19.根据权利要求15所述的方法，其进一步包含从所述表面移除所述分隔物。
20.根据权利要求15所述的方法，其进一步包含分割所述半导体晶片以提供至少一个晶片级封装半导体装置。
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