CN102789983A - Manufacturing method of transistor - Google Patents
Manufacturing method of transistor Download PDFInfo
- Publication number
- CN102789983A CN102789983A CN2011101263674A CN201110126367A CN102789983A CN 102789983 A CN102789983 A CN 102789983A CN 2011101263674 A CN2011101263674 A CN 2011101263674A CN 201110126367 A CN201110126367 A CN 201110126367A CN 102789983 A CN102789983 A CN 102789983A
- Authority
- CN
- China
- Prior art keywords
- grid
- layer
- sacrifice layer
- transistorized
- protective layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method of a transistor. The manufacturing method comprises the steps of: providing a substrate, orderly forming a transistor, and a silicification layer on a source/drain area of the transistor on the substrate, wherein the transistor comprises a grid, and a protection layer on the grid; forming a sacrificial layer on the substrate, wherein the upper surface of the sacrificial layer is at least higher than the grid of the transistor; removing a part of sacrificial layer until the protection layer on the grid of the transistor is exposed; removing the protection layer on the grid, and removing the residual sacrificial layer. In the manufacturing method of the transistor provided by the invention, the sacrificial layer on the transistor can protect the silification layer, and just a little of silicide layer is removed, so that high contact resistance of the silicide layer is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of transistorized manufacturing approach.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster, bigger data storage amount and more function, and semiconductor chip develops to high integration direction more.And the integrated level of semiconductor chip is high more, and (CD, Critical Dimension) is more little for the characteristic size of semiconductor device.At present, in the very lagre scale integrated circuit (VLSIC), characteristic size has entered into tens scopes to the hundreds of nanometer.
Show the sketch map of prior art transistor fabrication process referring to figs. 1 to Fig. 2.
At first, please refer to Fig. 1, on substrate 10, form a plurality of transistors, particularly, said transistor comprises NFET (N type FET), PFET (P type FET).With NFET is example; Said transistor comprises the grid structure that is positioned on the substrate 10; Said grid structure comprises gate dielectric layer 16, grid 13, the protective layer 14 that is positioned at successively on the substrate 10; Surround the side wall of said grid 13 and protective layer 14, said side wall comprises the monox lateral wall 18 that surrounds grid 13 and protective layer 14, the silicon nitride side wall 12 that surrounds said monox lateral wall 18.Be formed with source region (drain region) 17 on the substrate 10 of said grid structure both sides.Be formed with disilicide layer (silicide) 15 on the substrate 10 of 17 positions, said source region (drain region).Wherein, The said protective layer 14 that is positioned on the grid 13 is used for when source region (drain region) 17 being carried out the ion injection; Prevent that grid 13 from being damaged by ion; Particularly; The material of said protective layer 14 is a silicon nitride; Thickness is in the scope of
, and the thickness of said silicon nitride side wall 12 is in the scope of
.Extended meeting forms plug structure behind said disilicide layer 15 tops, and said disilicide layer 15 can play the effect that reduces contact resistance.
With reference to figure 2, after accomplishing the ion implantation step, through stress near technology (Stress ProximityTechnology, SPT) the said protective layer of selective removal 14, silicon nitride side wall 12.Yet, in the SPT etching process, remove part disilicide layer 15 easily, can make the contact resistance of the plug structure of follow-up formation become big like this.
In publication number is the one Chinese patent application of CN101393894A, can find more about existing transistorized manufacture method.
Summary of the invention
The problem that the present invention solves provides a kind of transistorized manufacturing approach, reduces contact resistance and becomes big problem.
For addressing the above problem, the present invention provides a kind of transistorized manufacturing approach, comprising: substrate is provided, is forming transistor on the said substrate successively, be positioned at the disilicide layer on transistorized source/drain region, said transistor comprises grid, is positioned at the protective layer on the grid; On substrate, form sacrifice layer, the upper surface of said sacrifice layer is higher than transistorized grid at least; Remove the partial sacrifice layer, until the protective layer that exposes on the transistorized grid; Removal is positioned at the protective layer on the grid; Remove the residue sacrifice layer.
The material of said sacrifice layer is BARC.
Said removal partial sacrifice layer comprises until the step of exposing transistorized grid: carve or ashing removal partial sacrifice layer through doing.
Said ashing comprises to the sacrifice layer aerating oxygen.
The material of said protective layer is a silicon nitride, and the step that said removal is positioned at the protective layer on the grid comprises: be positioned at the protective layer on the grid through doing to carve to remove.
The said step that is positioned at the protective layer on the grid through dried removal at quarter comprises: do through first and carve the removal partial protection layer; Do the residual protective layer of removal at quarter through second.
Said first does employing at quarter CF
4Gas; Second does employing at quarter CH
2F
2, CH
3One or both gases among the F.
The method of said removal residue sacrifice layer comprises: remove the residue sacrifice layer through cineration technics.
The step that on substrate, forms sacrifice layer comprises: form and cover said transistorized sacrifice layer.
The thickness of grid is positioned at the scope of the thickness of the protective layer on the grid at
in the scope of
.
The thickness of sacrifice layer is in the scope of
.
Compared with prior art, the present invention has the following advantages: the sacrifice layer that is positioned on the transistor can be protected disilicide layer, disilicide layer is only destroyed by a small amount of removal, has reduced that disilicide layer is destroyed and the contact resistance problem of higher that causes.
Description of drawings
Fig. 1～Fig. 2 is the transistorized manufacture method cross-sectional view of prior art;
Fig. 3 is the schematic flow sheet of transistor fabrication process one execution mode of the present invention;
Fig. 4～Fig. 9 is the formed transistorized cross-sectional view of transistor fabrication process one embodiment of the present invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Described like background technology, the transistorized manufacturing approach of prior art can be removed the part disilicide layer, can make the contact resistance of the plug structure of follow-up formation become big like this, and then cause the decline of transistor performance.To the problems referred to above, inventor of the present invention has proposed a kind of transistorized manufacturing approach, please refer to the schematic flow sheet of transistor fabrication process of the present invention one execution mode shown in Figure 3.Said method roughly may further comprise the steps:
Step S1; Substrate is provided; Forming transistor on the said substrate successively, be positioned at the disilicide layer on the source transistor drain region, said transistor comprises protective layer, the said grid of encirclement and first side wall of protective layer and second side wall that surrounds said first side wall that is positioned on the grid;
Step S2 forms sacrifice layer on substrate;
Step S3 removes the partial sacrifice layer, until the protective layer that exposes on the transistorized grid;
Step S4, removal is positioned at the protective layer on the grid;
Step S5 removes the residue sacrifice layer;
Step S6 removes second side wall.
Below in conjunction with concrete embodiment technical scheme of the present invention is carried out detailed explanation.For technical scheme of the present invention is described better, please refer to the transistor fabrication process cross-sectional view of the one embodiment of the invention of Fig. 4～shown in Figure 9.
At first, please refer to Fig. 4, execution in step S1 provides substrate 100, on said substrate 100, forms a plurality of MOS transistors, is formed with NMOS pipe, PMOS pipe on the substrate described in the present embodiment 100.Wherein, said substrate 100 can be monocrystalline silicon or SiGe; Also can be silicon-on-insulator (Silicon on insulator, SOI); The material that perhaps can also comprise other, for example: III-V compounds of group such as GaAs.Said substrate 100 can also have isolation structure 101, is used to isolate NMOS pipe and PMOS pipe, and said isolation structure 101 can be isolated (LOCOS) from (STI) or local field oxidation for shallow trench isolation.
Particularly, said metal-oxide-semiconductor comprises the grid structure that is positioned on the substrate 100, and is positioned at the source region (drain region) 107 on the substrate of said grid structure both sides.
The step that forms metal-oxide-semiconductor is included in and forms grid structure on the substrate, and said grid structure comprises grid oxic horizon 106, grid 103, the protective layer 104 that is positioned at successively on the substrate, surrounds the side wall 108 on said grid 103 and protective layer 104 sidewalls, wherein,
In the present embodiment, the thickness of said grid 103 is in the scope of
.
Said side wall 108 comprises first side wall that surrounds said grid 103 and protective layer 104 sidewalls and second side wall that surrounds said first side wall, and particularly, said first side wall is a silica, and second side wall is a silicon nitride.
Said protective layer 104 is used for injecting the process that forms source region (drain region) 107 follow-up through ion, the damage that protection grid 103 is not injected ion.Particularly; The material of said protective layer 104 is a silicon nitride, and thickness is in the scope of
.
Forming metal-oxide-semiconductor also comprises being infused on the grid 103 both sides substrates through ion and forms source region (drain region) 107.Also be included in and form disilicide layer 105 on the source region (drain region) 107, extended meeting forms plug structure behind the top of said disilicide layer 105, and said disilicide layer 105 can play the effect that reduces the plug structure contact resistance.
It is identical with prior art with technology on substrate 100, to form the employed material of metal-oxide-semiconductor, repeats no more at this.
With reference to figure 5, execution in step S2 forms sacrifice layer 109, and said sacrifice layer 109 is used for the step protection disilicide layer 105 at follow-up removal protective layer, and the upper surface of said sacrifice layer 109 is higher than transistorized grid at least.
Simultaneously, in order to play the effect of protective transistor, preferably, the thickness of said sacrifice layer 109 is bigger, can cover said transistor.
Therefore, need be chosen in and select smaller material as sacrifice layer 109 in the step of follow-up removal protective layer, in addition, owing to follow-uply also need remove sacrifice layer 109, the material that therefore needs to select to be convenient to remove is as sacrifice layer 109.
Particularly, said sacrifice layer 109 is that (Bottom Anti-Reflect Coating, BARC), said BARC is the organic film of carbon containing to bottom antireflective coating.
Need to prove,, can cause the difficulty of follow-up removal sacrifice layer 109 technologies if said sacrifice layer 109 is thicker.Therefore; Preferably, the thickness of said sacrifice layer 109 is in the scope of
.
With reference to figure 6, execution in step S3 removes partial sacrifice layer 109; In the present embodiment; Said sacrifice layer 109 is BARC, can be through do carving or partial sacrifice layer 109 is removed in ashing, make remaining sacrifice layer 109 upper surface and grid 103 flush or be lower than the upper surface of grid 103; Thereby the protective layer 104 of grid 103 tops is exposed fully, so that subsequent step is removed said protective layer 104.
Particularly, can remove said BARC through doing quarter or ashing.Removing BARC technology through ashing comprises: feed the etching gas that comprises oxygen, the organic film BARC of said carbon containing and oxygen reaction form carbon dioxide, because carbon dioxide is that gas is removed easily, and then reach the purpose of removing sacrifice layer 109.
Need to prove, need control removal speed when removing BARC through ashing.
Also need to prove, can remove the thickness of partial sacrifice layer 109 then through time control through measuring the removal speed of ashing sacrifice layer 109 in advance.
With reference to figure 7, execution in step S4 removes the protective layer 104 on the grid 103 through etching.Said etching step is bigger to the selection of protective layer 104 and sacrifice layer 109; In the process of removing protective layer 104, can bigger damage not arranged, therefore to sacrifice layer 109; In the process of removing protective layer 104; Said sacrifice layer 109 has been protected the disilicide layer 105 that is positioned at its below, has avoided the damage of disilicide layer 105, and then prevents to cause contact resistance to become big problem.
In the present embodiment; The material of said protective layer 104 is a silicon nitride; Thickness is in the scope of
; Can remove said silicon nitride through doing the quarter method, particularly, need to select to select smaller method remove said protective layer 104 grid 103.
In order to improve removal efficient, preferably, can adopt two-step dry carving technology (comprising that first does the quarter and second dried the quarter), may further comprise the steps particularly:
Adopt CF in first dried the quarter
4Gas is removed most of nitrogenize silicon;
Second does employing gas CH in quarter
2F
2, CH
3One or both gases among the F are removed residual silicon nitride.
In above-mentioned steps, the CF that dry carving technology adopts
4Gas and CH
2F
2, CH
3During one or both gases among the F, can tangible removal effect not arranged, so sacrifice layer 109 can protect disilicide layer 105 effectively, improve the contact resistance of disilicide layer 105 BARC,
Simultaneously, adopt CF
4Gas can efficient be removed silicon nitride than the highland, and adopts CH
2F
2/ CH
3F remove silicon nitride can accomplish the selection ratio of grid higher, thereby reduce to do the quarter process to the damage of grid 103, improve the contact resistance of grid 103.
In the process of removing protective layer 104, can only pass through CF
4Gas is removed most of nitrogenize silicon, and on grid 103, keeps residual silicon nitride, in subsequent step, removes residual silicon nitride afterwards again, can protect grid 103 injury-free so on the one hand, saves step on the other hand, raises the efficiency.
With reference to figure 8, execution in step S5 removes said sacrifice layer 109 through cineration technics; The material of said sacrifice layer is BARC, can remove said sacrifice layer 109 through the ashing method original position, similarly; In podzolic process; Pass through oxygen in hot conditions to BARC (organic film of carbon containing),, thereby remove sacrifice layer 109 with the formation carbon dioxide.
With reference to figure 9, execution in step S6 removes second side wall through doing the quarter method in the present embodiment, and particularly, said second side wall is the silicon nitride side wall, and the thickness of said second side wall exists
Scope in, in dry carving technology, adopt CHF
3, CH
2F
2, CH
3One or more gases among the F carry out the isotropic etching to second side wall, to remove the silicon nitride side wall.
Need to prove, after removing sacrifice layer 109, exposed disilicide layer 105, therefore in the process of removing second side wall, disilicide layer 105 can be removed by part.But; Because the thickness less (
) of second side wall; Compared with prior art (SPT removes protective layer and silicon nitride side wall simultaneously; Remove thickness in the scope of
); Therefore the removal amount when removing second side wall is less; Therefore in the process of removing second side wall, have only very a small amount of disilicide layer 105 to be removed; It is badly damaged disilicide layer 105 to be received, thereby has reduced disilicide layer contact resistance problem of higher.
Need to prove, for the situation that keeps residual silicon nitride on the grid 103, can be when removing the silicon nitride side wall, in same dried quarter step, remove said residual silicon nitride.
Said transistor fabrication process is follow-up also to be comprised, on substrate, deposits interlayer dielectric layer, on grid 103, disilicide layer 105, forms the step of connector etc., repeats no more at this.
To sum up, the present invention provides a kind of transistorized manufacturing approach, has reduced the damage of disilicide layer through sacrifice layer protection disilicide layer, thereby has reduced to be destroyed the disilicide layer contact resistance problem of higher that causes because of disilicide layer.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (11)
1. a transistorized manufacturing approach is characterized in that, comprising: substrate is provided, is forming transistor on the said substrate successively, be positioned at the disilicide layer on transistorized source/drain region, said transistor comprises grid, is positioned at the protective layer on the grid; On substrate, form sacrifice layer, the upper surface of said sacrifice layer is higher than transistorized grid at least; Remove the partial sacrifice layer, until the protective layer that exposes on the transistorized grid; Removal is positioned at the protective layer on the grid; Remove the residue sacrifice layer.
2. transistorized manufacturing approach as claimed in claim 1 is characterized in that, the material of said sacrifice layer is BARC.
3. transistorized manufacturing approach as claimed in claim 2 is characterized in that, said removal partial sacrifice layer comprises until the step of exposing transistorized grid: carve or ashing removal partial sacrifice layer through doing.
4. transistorized manufacturing approach as claimed in claim 3 is characterized in that said ashing comprises to the sacrifice layer aerating oxygen.
5. transistorized manufacturing approach as claimed in claim 1 is characterized in that, the material of said protective layer is a silicon nitride, and the step that said removal is positioned at the protective layer on the grid comprises: be positioned at the protective layer on the grid through doing to carve to remove.
6. transistorized manufacturing approach as claimed in claim 5 is characterized in that, the said step that is positioned at the protective layer on the grid through dried removal at quarter comprises: do through first and carve the removal partial protection layer; Do the residual protective layer of removal at quarter through second.
7. transistorized manufacturing approach as claimed in claim 6 is characterized in that, said first does employing at quarter CF
4Gas; Second does employing at quarter CH
2F
2, CH
3One or both gases among the F.
8. transistorized manufacturing approach as claimed in claim 1 is characterized in that, the method for said removal residue sacrifice layer comprises: remove the residue sacrifice layer through cineration technics.
9. transistorized manufacturing approach as claimed in claim 1 is characterized in that, the step that on substrate, forms sacrifice layer comprises: form and cover said transistorized sacrifice layer.
10. transistorized manufacturing approach as claimed in claim 1; It is characterized in that; The thickness of grid is positioned at the scope of the thickness of the protective layer on the grid at
in the scope of
.
11. transistorized manufacturing approach as claimed in claim 10; It is characterized in that the thickness of sacrifice layer is in the scope of
.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110126367.4A CN102789983B (en) | 2011-05-16 | 2011-05-16 | The manufacture method of transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110126367.4A CN102789983B (en) | 2011-05-16 | 2011-05-16 | The manufacture method of transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102789983A true CN102789983A (en) | 2012-11-21 |
| CN102789983B CN102789983B (en) | 2015-11-25 |
Family
ID=47155355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110126367.4A Active CN102789983B (en) | 2011-05-16 | 2011-05-16 | The manufacture method of transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102789983B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517843A (en) * | 2013-09-29 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN108666220A (en) * | 2017-03-30 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591829A (en) * | 2003-08-28 | 2005-03-09 | 力晶半导体股份有限公司 | Automatic-aligning method silicide mfg. method |
| CN101114650A (en) * | 2006-07-26 | 2008-01-30 | 国际商业机器公司 | Method and structure for self-aligned device contacts |
| CN101207027A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device grids |
| CN101853813A (en) * | 2009-03-31 | 2010-10-06 | 台湾积体电路制造股份有限公司 | Semiconductor device and fabricating method thereof |
| CN102024754A (en) * | 2009-09-17 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
-
2011
- 2011-05-16 CN CN201110126367.4A patent/CN102789983B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591829A (en) * | 2003-08-28 | 2005-03-09 | 力晶半导体股份有限公司 | Automatic-aligning method silicide mfg. method |
| CN101114650A (en) * | 2006-07-26 | 2008-01-30 | 国际商业机器公司 | Method and structure for self-aligned device contacts |
| CN101207027A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device grids |
| CN101853813A (en) * | 2009-03-31 | 2010-10-06 | 台湾积体电路制造股份有限公司 | Semiconductor device and fabricating method thereof |
| CN102024754A (en) * | 2009-09-17 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517843A (en) * | 2013-09-29 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN108666220A (en) * | 2017-03-30 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102789983B (en) | 2015-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9754842B2 (en) | FinFET with dummy gate on non-recessed shallow trench isolation (STI) | |
| CN101814523B (en) | Semiconductor device and a manufacturing approach with the same | |
| CN100461430C (en) | Semiconductor structure and its forming method | |
| US7868373B2 (en) | Flash memory device and a method of fabricating the same | |
| CN107919327B (en) | Semiconductor structure and forming method thereof | |
| US9059209B2 (en) | Replacement gate ETSOI with sharp junction | |
| CN104916541B (en) | Form the method and FinFET of semiconductor devices and FinFET | |
| US20070246795A1 (en) | Dual depth shallow trench isolation and methods to form same | |
| CN105304709A (en) | Structure and formation method of fin-like field effect transistor | |
| US9263556B2 (en) | Silicide process using OD spacers | |
| US20110068408A1 (en) | Strained-silicon cmos transistor | |
| US10483269B2 (en) | EEPROM device | |
| CN101630655B (en) | Method for forming shallow plough groove isolation | |
| US10804391B2 (en) | Vertical field-effect transistor (VFET) devices and methods of forming the same | |
| US20150064812A1 (en) | Method of forming a semiconductor device employing an optical planarization layer | |
| CN102789983A (en) | Manufacturing method of transistor | |
| CN107591364B (en) | Semiconductor structure and forming method thereof | |
| CN108010835A (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| US20200303247A1 (en) | Semiconductor structures with a protective liner and methods of forming the same | |
| CN109003899B (en) | Semiconductor structure, forming method thereof and forming method of fin field effect transistor | |
| CN106601680B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN106298676A (en) | Method for manufacturing semiconductor element | |
| CN108074868B (en) | Semiconductor structure and forming method thereof | |
| US7732310B2 (en) | Sidewall memory with self-aligned asymmetrical source and drain configuration | |
| KR20080033130A (en) | Pre-silicide spacer removal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |