CN104517843A - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- CN104517843A CN104517843A CN201310455829.6A CN201310455829A CN104517843A CN 104517843 A CN104517843 A CN 104517843A CN 201310455829 A CN201310455829 A CN 201310455829A CN 104517843 A CN104517843 A CN 104517843A
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Abstract
A method for forming a semiconductor device comprises the following steps: providing a semiconductor substrate consisting of a first region and a second region, wherein the surface of the semiconductor substrate in the first region has a first gate structure, and the surface of the semiconductor substrate in the second region has a second gate structure; forming a spacer film covering the first gate structure, the second gate structure and the semiconductor substrate; forming an anti-reflection coating layer covering the spacer film; forming a photoresist layer disposed on the surface of the anti-reflection coating layer in the first region; etching with the photoresist layer as a mask to remove the anti-reflection coating layer in the second region; and back-etching the spacer film in the second region with the photoresist layer as a mask, and forming spacers on the surface of the semiconductor substrate in the second region, wherein the spacers are disposed on the two sides of the second gate structure. While improving the accuracy of photoresist layer formation, damage of the forming process to the semiconductor substrate is avoided, the flatness of the semiconductor substrate is improved, and the electrical property of semiconductor devices is improved.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly the formation method of semiconductor device.
Background technology
In the process for making of semiconductor device; the method of photoresist being carried out to the photoetching of exposure imaging is the main method realizing Graphic transitions; specific region for the protection of processed lower coating is not etched or adulterates, common, and processed lower coating is Semiconductor substrate.
Along with the development of chip technology, the feature dimensions of chip is more and more less, the material of processed lower coating is also more and more diversified, therefore in photolithographic exposure process, due to the exposure reflection problems that optical property difference produces between photoresist layer and its lower coating, become the key factor affecting exposure performance.So the method only using conventional photoresist to carry out exposing has been difficult to realize the accurate transfer of fine pattern.
For meeting the requirement of photoetching process, antireflecting coating (Anti-Reflective Coating:ARC) technology is applied to the precision improving photoetching in photoetching.The effect of antireflecting coating is mainly: prevent light by reflecting at lower clad interface after photoresist; And the light of reflection can interfere with incident light, cause photoresist can not uniform exposure.Antireflecting coating comprises reflection coating provided (Top Anti-ReflectiveCoating:TARC) and bottom antireflective coating (Bottom Anti-Reflective Coating:BARC).
But the Semiconductor substrate of the semiconductor device that prior art is formed is vulnerable to damage, affects the electric property of semiconductor device.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor device of optimization, while improving the photoresist layer accuracy formed, semiconductor device formation process is avoided to cause damage to Semiconductor substrate, and minimizing technique causes etching to side wall, improves the electric property of semiconductor device.
For solving the problem, the invention provides a kind of formation method of semiconductor device, comprise: Semiconductor substrate is provided, described Semiconductor substrate comprises first area and second area, described first area semiconductor substrate surface has first grid structure, and described second area semiconductor substrate surface has second grid structure; Form the side wall film covering described first grid structure, second grid structure and Semiconductor substrate; Form the antireflecting coating covering described side wall film; Antireflecting coating surface in described first area forms photoresist layer; With described photoresist layer for mask, etching removes the antireflecting coating of second area; With described photoresist layer for mask, return the side wall film of etching second area, form side wall at second area semiconductor substrate surface, and described side wall is positioned at second grid structure both sides.
Optionally, described side wall film is single layer structure or sandwich construction.
Optionally, when described side wall film is single layer structure, described side wall film is silicon nitride layer or silicon oxide layer; When described side wall film is sandwich construction, described side wall film is the sandwich construction of silicon oxide layer and silicon nitride layer.
Optionally, anisotropic etch process is adopted to return the side wall film of etching second area.
Optionally, spin coating proceeding is adopted to form described antireflecting coating.
Optionally, the thickness of described antireflecting coating is 100 dust to 2000 dusts.
Optionally, the forming step that the antireflecting coating surface in described first area forms photoresist layer is: form the initial lithographic glue-line covering antireflecting coating; By exposure imaging technique, remove the initial lithographic glue-line being positioned at the antireflecting coating surface of second area, the antireflecting coating surface in described first area forms photoresist layer.
Optionally, dry etch process etching is adopted to remove the antireflecting coating of second area.
Optionally, described dry etch process is reactive ion etching.
Optionally, described antireflecting coating is organic antireflective coating.
Optionally, also comprise step: with described photoresist layer for mask, in the Semiconductor substrate of described second grid structure both sides, form doped region; Remove the antireflecting coating of described photoresist layer and first area.
Optionally, the photoresist layer of described removal first area and the technique of antireflecting coating are cineration technics.
Optionally, described doped region is light doping section or heavily doped region.
Optionally, ion implantation technology is adopted to form described doped region.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the present embodiment; side wall film is formed between antireflecting coating and Semiconductor substrate; when etching the antireflecting coating removing second area; the described side wall film protection Semiconductor substrate technique that is not etched destroyed; improve the evenness of semiconductor substrate surface, improve the electric property of semiconductor device.
Meanwhile, in the present embodiment, after the antireflecting coating removing second area, return the side wall film of etching second area, form the side wall being positioned at second grid structure both sides, the technique avoiding side wall to be removed second area antireflecting coating etched; And when removing the antireflecting coating of second area, less by the impact of etching technics at the side wall film of second grid structure two side areas; Compared with prior art, the present invention forms side wall after removal second area antireflecting coating, avoid removal second area anti-reflective coating layer process offside wall and cause etching, therefore the width of the side wall of the present invention's formation is larger, effectively can stop the easy diffusion ion in the metal silicide of follow-up formation, prevent the ion diffuse in metal silicide from entering channel region; And due to the width of side wall comparatively large, interpenetrate between the doped region that effectively can stop follow-up formation, improve the reliability of semiconductor device, optimize the electric property of semiconductor device.
Further, in the present embodiment, adopt cineration technics to remove the photoresist layer of first area and antireflecting coating, avoid removing described photoresist layer and antireflecting coating causes damage to second area Semiconductor substrate, improve the electric property of semiconductor device further.
Further, the present embodiment defines antireflecting coating below photoresist layer, and the existence of described antireflecting coating makes photoresist layer expose evenly, improves the accuracy of the photoresist layer figure of formation.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet that an embodiment forms semiconductor device;
Fig. 2 is the light reflectogram of light in active area and isolation structure interface of photoresist layer exposure;
Fig. 3 to Figure 16 is the cross-sectional view of another embodiment of the present invention semiconductor device forming process.
Embodiment
As stated in the Background Art, the electric property of the semiconductor device of prior art formation is poor.
For this reason, formation method for semiconductor device is studied, the formation method of semiconductor device comprises the following steps, please refer to Fig. 1: step S1, provide Semiconductor substrate, described Semiconductor substrate comprises first area and second area, and described first area semiconductor substrate surface has first grid structure, described second area semiconductor substrate surface has second grid structure; Step S2, in described first area, semiconductor substrate surface forms the first side wall, and described first side wall is positioned at first grid structure both sides, forms the second side wall at described second area semiconductor substrate surface, and described second side wall is positioned at second grid structure both sides; Step S3, form photoresist layer on described second area surface; Step S4, be mask with photoresist layer, doping formed to the first area Semiconductor substrate of first grid structure both sides, forms doped region; The photoresist layer of step S5, removal second area.
The formation method of the above-mentioned semiconductor device provided, after second area surface forms photoresist layer, the figure that figure and the expection of photoresist layer are formed has deviation.Analyzing the problems referred to above Producing reason is: first, in photoresist layer exposure process, the light of exposure reflects at semiconductor substrate surface, causes photoresist layer to expose uneven.Secondly, in order to prevent being electrically connected in semiconductor device, adopt isolation structure isolated first area and second area, please refer to Fig. 2, AA1 is first area (active area), and AA2 is second area, and STI is isolation structure, and PR is photoresist layer; In photoresist layer exposure process, the light 01 of exposure reflects in the interface of first area Semiconductor substrate and isolation structure, causes the uneven exposure of the sidewall of photoresist layer, affects follow-uply in the Semiconductor substrate of first area, to form doped region.
For solving the problem, antireflecting coating is formed between Semiconductor substrate and photoresist layer, described antireflecting coating avoids photoresist layer when exposure imaging, the light of exposure reflects at semiconductor substrate surface or Semiconductor substrate and isolation structure boundary layer, improves the accuracy of the antireflecting coating surperficial formation photoresist layer at second area.
But after forming antireflecting coating, the technique of follow-up removal first area antireflecting coating causes damage to Semiconductor substrate, has had a strong impact on the electric property of semiconductor device.Formation method for semiconductor device studies discovery further, causes the reason of the problems referred to above as follows:
The technique of the antireflecting coating of described removal first area is dry etching, and the semiconductor substrate surface of described dry etch process to first area causes etching; And due to the thickness of antireflecting coating thicker (thickness of antireflecting coating is greater than the thickness of first grid structure or second grid structure), therefore the process time of the antireflecting coating of dry etching first area is longer, cause dry etch process to cause the etching of long period to first area Semiconductor substrate, the Semiconductor substrate of first area sustains damage.Concrete, described dry etch process causes the semiconductor substrate surface of first area uneven, it is follow-up when semiconductor substrate surface forms metal silicide, interfacial state between described metal silicide and Semiconductor substrate is poor, be unfavorable for reducing contact of semiconductor device resistance, affect the electric property of semiconductor device.
Meanwhile, the technique that the first side wall of semiconductor device that said method is formed also is removed the antireflecting coating of first area affected, and concrete, described first side wall is etched, and causes the width of the first side wall to reduce; Rear extended meeting forms metal silicide at the first area semiconductor substrate surface of the first side wall both sides, there is the ion of easily diffusion in described metal silicide; If the width of described first side wall reduces, the ion of easily diffusion in metal silicide can be caused to diffuse in the channel region of semiconductor device by the first side wall, cause the degraded performance of semiconductor device; And the first lateral wall width is less, the doped region of follow-up formation can be caused easily to interpenetrate, the electric property of degrade.
For this reason, the invention provides a kind of formation method of semiconductor device of optimization, between antireflecting coating and Semiconductor substrate, form side wall film, and after the antireflecting coating removing second area, return etching side wall film and form the side wall being positioned at second grid structure both sides.The present invention avoids removing anti-reflective coating layer process double conductive substrate and causes damage, and forms side wall after etching removes antireflecting coating, avoids side wall to be etched technogenic influence, improves the electric property of semiconductor device.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 3 to Figure 16 is the cross-sectional view of another embodiment of the present invention semiconductor device forming process.
Please refer to Fig. 3, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 comprises first area I and second area II, and Semiconductor substrate 100 surface of described first area I has first grid structure 110, and Semiconductor substrate 100 surface of described second area II has second grid structure 120.
Described Semiconductor substrate 100 is Si substrate, Ge substrate, GeSi substrate or GaAs substrate; Described Semiconductor substrate 100 surface can also form some epitaxial interface layers or strained layer to improve the electric property of semiconductor device.In an embodiment of the present invention, described Semiconductor substrate 100 is Si substrate.
Described first area I is NMOS area or PMOS area, and described second area II is NMOS area or PMOS area.Wherein, when described first area I is NMOS area, described second area II is PMOS area, and when described first area I is PMOS area, described second area II is NMOS area.In an embodiment of the present invention, with described first area I for NMOS area, second area II is that PMOS area does exemplary illustrated.
Also it should be noted that, described first area I and second area II can be adjacent or interval, should too not limit the scope of the invention.
Isolation structure 101 can also be formed in described Semiconductor substrate 100, existing isolation structure usually adopt shallow trench isolation from.The packing material of described isolation structure 101 can be one or more in silica, silicon nitride, silicon oxynitride.
Described first grid structure 110 comprise be positioned at described Semiconductor substrate 100 surface first grid oxide layer 111, be positioned at the first grid electrode layer 112 on described first grid oxide layer 111 surface and be positioned at the first top mask layer 113 on first grid electrode layer 112 surface.
Described second grid structure 120 comprise be positioned at described Semiconductor substrate 200 surface second gate oxide layer 121, be positioned at the second gate electrode layer 122 on described second gate oxide layer 121 surface and be positioned at the second top mask layer 123 on second gate electrode layer 112 surface.
The material of described first grid oxide layer 111 or second gate oxide layer 121 is silica or high K medium material, the material of described first grid electrode layer 112 or second gate electrode layer 122 is polysilicon, the polysilicon of doping or metal, and the material of described first top mask layer 113 or the second top mask layer 123 is silicon nitride.
The top acting as protection first grid structure 110 or second grid structure 120 of described first top mask layer 113 or the second top mask layer 123 not destroy by subsequent technique.
Please refer to Fig. 4, form the side wall film covering described first grid structure 110, second grid structure 120 and Semiconductor substrate 100.
Acting as of described side wall film: protection Semiconductor substrate 100 surface by subsequent etching remove antireflecting coating technique destroy; Described side wall film can also be positioned at the side wall of first grid structure 110 or second grid structure 120 both sides in follow-up formation.
The formation process of described side wall film is chemical vapour deposition (CVD) or ald.
Described side wall film is single layer structure or sandwich construction.
In the present embodiment, described side wall film is the sandwich construction of silicon oxide layer 102 and silicon nitride layer 103.Atom layer deposition process is adopted to form described silicon oxide layer 102 and silicon nitride layer 103.The thickness of described silicon oxide layer 102 is 10 dust to 100 dusts, and the thickness of described silicon nitride layer 103 is 50 dust to 200 dusts.
In other embodiments of the present invention, described side wall film is the single layer structure of silicon oxide layer or silicon nitride layer, and described side wall film can also be the sandwich construction of silicon oxide layer, silicon nitride layer and silicon oxide layer.
Please refer to Fig. 5, form the first antireflecting coating 104 covering described side wall film.
In the present embodiment, the top of described first antireflecting coating 104 is higher than the top of first grid structure 110 or second grid structure 120, avoid due to the first antireflecting coating 104 top lower than first grid structure 110 or second grid structure 120 top time, the photoresist layer of follow-up formation exposes uneven in first grid structure 110 or second grid structure 120 surf zone, and impact forms the accuracy of photoresist layer.
The effect of described first anti-reflecting layer 104 is mainly: when preventing the initial lithographic glue-line exposure of follow-up formation, light is reflected at Semiconductor substrate 100 interface by initial lithographic glue-line, avoid the light reflected can interfere with incident light, and avoid, at isolation structure 101 and Semiconductor substrate 100 interface, light reflection occurs, make initial lithographic glue-line energy uniform exposure, thus form the photoresist layer with better pattern.
In the present embodiment, described first antireflecting coating 104 is positioned at silicon nitride layer 103 surface.
The formation process of described first antireflecting coating 104 is spin coating proceeding or chemical vapor deposition method, and the thickness of described first antireflecting coating 104 is 100 dust to 2000 dusts.
Described first antireflecting coating 104 is inorganic anti-reflective coating or organic antireflective coating.
The material of described inorganic anti-reflective coating is titanium, titanium oxide, titanium nitride, chromium oxide, carbon, amorphous silicon, silicon nitride, silicon oxynitride or silicon oxide carbide; The material of described organic antireflective coating is made up of light absorbing material and polymeric material, and described organic antireflective coating comprises organic antireflective coating without silicon and siliceous organic antireflective coating.
In the present embodiment, described first antireflecting coating 104 is organic antireflective coating, adopts spin coating proceeding to form described first antireflecting coating 104.
Please refer to Fig. 6, form the first photoresist layer 105 on first antireflecting coating 104 surface of described first area I.
The forming step of described first photoresist layer 105 is: the initial lithographic glue-line forming covering first antireflecting coating 104; By exposure imaging technique, remove the initial lithographic glue-line being positioned at first antireflecting coating 104 surface of second area II, form the first photoresist layer 105 on first antireflecting coating 104 surface of described first area I.
Owing to being formed with the first antireflecting coating 104 between initial lithographic glue-line and Semiconductor substrate 100, described first antireflecting coating 104 makes initial lithographic glue-line expose evenly, thus accurate removal is positioned at the initial lithographic glue-line of second area II, form first photoresist layer 105 with good pattern on first antireflecting coating 104 surface of first area I, avoid generating process deviation.
Please refer to Fig. 7, with described first photoresist layer 105 for mask, etching removes first antireflecting coating 104 of second area II.
Remove the first antireflecting coating 104 being positioned at second area II, expose Semiconductor substrate 100 surface of second grid structure 120 both sides, in the Semiconductor substrate 100 of second grid structure 120 both sides, form doped region so that follow-up.
Dry etch process or cineration technics is adopted to remove described first antireflecting coating 104.
When removing described first antireflecting coating 104 owing to adopting cineration technics, described cineration technics also can cause damage to the first photoresist layer 105, reduces the figure accuracy of the first photoresist layer 105, affects the technique of follow-up formation doped region.Therefore, in the present embodiment, adopt dry etch process etching to remove first antireflecting coating 104 of second area II, avoid causing damage to the figure of the first photoresist layer 105.
As an embodiment, described dry etch process is reactive ion etching, and the technological parameter of described reactive ion etching process is: reacting gas is H
2, N
2and CF
4, wherein, H
2flow is 100sccm to 200sccm, N
2flow is 10sccm to 200sccm, CF
4flow is 10sccm to 100sccm, and reaction chamber pressure is that 100 millitorrs to 1 hold in the palm, and chamber temp is 200 degree to 350 degree, and radio frequency source power is 100 watts to 500 watts.
In the present embodiment, when adopting dry etch process removal to be positioned at first antireflecting coating 104 of second area II, on Semiconductor substrate 100 surface of second area II, there is side wall film, described side wall film stops that the etching gas of reactive ion etching contacts with Semiconductor substrate 100, thus avoid described dry etch process to cause damage to second area II Semiconductor substrate 100, when the follow-up surface of the Semiconductor substrate 100 in second grid structure 120 both sides forms metal silicide, described metal silicide and Semiconductor substrate 100 surface contact tight, thus improve the electric property of semiconductor device.
If do not form side wall film between the first antireflecting coating 104 and Semiconductor substrate 100, due to the thickness of the first antireflecting coating 104 thicker (200 dust to 2000 dust), then the process time of reactive ion etching process is longer; And by the reaction chamber being placed in reactive ion etching process of Semiconductor substrate 100 long period, reactive ion etching process can be caused to cause etching injury to second area II Semiconductor substrate 100 surface, cause the surface irregularity of Semiconductor substrate 100, affect the electric property of semiconductor device.When adopting dry etch process etching to remove first antireflecting coating of described second area II, dry etch process has anisotropic specific, the etching gas of dry etching has the air flow direction perpendicular with semiconductor substrate surface, therefore, the impact that the side wall film being positioned at second grid structure 120 both sides is subject to dry etch process is less, the width being positioned at the side wall film of second grid structure 120 two side areas with differ less before dry etching.
Please refer to Fig. 8, with described first photoresist layer 105 for mask, return the side wall film of etching second area II, form side wall on second area II Semiconductor substrate 100 surface, and described side wall is positioned at second grid structure 120 both sides.
Anisotropic etch process is adopted to return the side wall film of etching second area II.
As an embodiment, described anisotropic etch process is dry etching, and the technological parameter of described dry etch process is: etching gas comprises CF
4, CHF
3and Ar, CHF
3flow is 65sccm to 200sccm, CF
4flow be the flow of 30sccm to 50sccm, Ar be 50sccm to 70sccm, reaction chamber pressure is 0 millitorr to 5 millitorr, and source power is 200 watts to 1000 watts, and bias voltage is 200V to 1000V.
In the present embodiment, described side wall film is the sandwich construction of silicon oxide layer 102 and silicon nitride layer 103, and therefore, the side wall of formation is the sandwich construction of monox lateral wall 132 and silicon nitride spacer 133.
If the side wall of second grid structure 120 both sides was formed before the first antireflecting coating 104 removing second area II, then when etching the first antireflecting coating 104 removing second area II, described etching technics also can etch side wall, causes the width of side wall to reduce; Semiconductor substrate 100 surface of rear extended meeting in side wall both sides forms metal silicide, has the ion of easily diffusion in described metal silicide; The reduction of lateral wall width can cause the blocking capability of side wall commute diffusion ion to die down, and in metal silicide, the ion of easily diffusion is easily diffused in the channel region below second grid structure by side wall, causes the reliability of semiconductor device to reduce, and electric property worsens.And in the present embodiment, side wall due to second grid structure 120 both sides is formed after the first antireflecting coating 104 removing second area II, the side wall of dry etch process to second grid structure 120 both sides can be effectively avoided to cause etching, the lateral wall width formed in second grid structure 120 both sides is larger, in the effective barrier metal silicide of energy, easily diffusion ion diffuses to undesirably region, improve the reliability of semiconductor device, optimize the electric property of semiconductor device.
Please refer to Fig. 9, with described first photoresist layer 105 for mask, in the Semiconductor substrate 100 of described second grid structure 120 both sides, form the first doped region 106.
Described first doped region 106 is light doping section or heavily doped region.
In the present embodiment, with described first doped region 106 for presenting a demonstration property of heavily doped region illustrates, described side wall is the master wall forming described heavily doped region.
Ion implantation technology is adopted to form the first doped region 106 in the second area II Semiconductor substrate 100 of described side wall both sides.
The present embodiment is with described second area II for presenting a demonstration property of PMOS area illustrates, the doping type of described first doped region 106 is the doping of P type.As an embodiment, the concrete technology parameter adopting ion implantation technology to form described doped region 106 is: described P type Doped ions is boron or indium, and the energy of ion implantation is 1kev to 50kev, and ion implantation dosage is 1E15atom/cm
2to 5E19atom/cm
2.
In other embodiments of the present invention, described first doped region is light doping section, adopts ion implantation technology to form described light doping section.
Please refer to Figure 10, remove described first photoresist layer 105(and please refer to Fig. 9) and the first antireflecting coating 104(of first area I please refer to Fig. 9).
In the present embodiment, cineration technics is adopted to remove first antireflecting coating 104 of the first photoresist layer 105 and first area I, the damage caused Semiconductor substrate 100 when farthest can reduce removal first photoresist layer 105 and the first antireflecting coating 104.
As an embodiment, the concrete technology parameter of described cineration technics is: the gas that described cineration technics adopts is oxygen, and reaction temperature is 40 degree to 250 degree, and oxygen flow is 10sccm to 1000sccm.
Please refer to Figure 11, form the second antireflecting coating 107 covering first area I side wall film, first grid structure 110, second grid structure 120, side wall and Semiconductor substrate 100.
The top of described second antireflecting coating 107 is higher than the top of first grid structure 110 or second grid structure 120.
The first antireflecting coating 104(that the formation process of described second antireflecting coating 107, material and effect provide see the embodiment of the present invention please refer to Fig. 5) formation process, material and effect, do not repeat them here.
Please refer to Figure 12, form the second photoresist layer 108 on second antireflecting coating 107 surface of described second area II.
The forming process of described second photoresist layer 108 please refer to Fig. 6 see the first photoresist layer 105() forming process, do not repeat them here.
Please refer to Figure 13, with described second photoresist layer 108 for mask, etching removes second antireflecting coating 107 of first area I.
The technique that described etching removes second antireflecting coating 107 of first area I etches see the present invention the first antireflecting coating 104(removing second area II and please refer to Fig. 7) technique, do not repeat them here.
It should be noted that, between second antireflecting coating 107 and Semiconductor substrate 100 of first area I, have side wall film, concrete, described side wall film is the sandwich construction of silicon oxide layer 102 and silicon nitride layer 103.In the process of the second antireflecting coating 107 removing first area I, described side wall film can protect first area I Semiconductor substrate 100 not to be destroyed.Therefore, after removing the second antireflecting coating 107, first area I Semiconductor substrate 100 still has level and smooth surface, is conducive to follow-up formation and Semiconductor substrate 100 surface contact metal silicide closely, thus reduce the contact resistance of semiconductor device, optimize the electric property of semiconductor device.
Please refer to Figure 14, with described second photoresist layer 108 for mask, return the side wall film of etching first area I, form side wall in first grid structure 110 both sides.
In the present embodiment, the side wall of formation is the sandwich construction of monox lateral wall 142 and silicon nitride spacer 143.
The formation process of the side wall of described first grid structure 110 both sides, see the formation process of the side wall of second grid structure 120 both sides of the present invention, does not repeat them here.
Please refer to Figure 15, with described second photoresist layer 108 for mask, in the Semiconductor substrate 100 of described first grid structure 110 both sides, form the second doped region 109.
Described second doped region 109 is light doping section or heavily doped region.
The present embodiment is with described second doped region 109 for presenting a demonstration property of heavily doped region illustrates, described side wall is the master wall forming heavily doped region.
As an embodiment, ion implantation technology is adopted to form the second doped region 109 in the first area I Semiconductor substrate 100 of described side wall both sides.
The present embodiment is that presenting a demonstration property of NMOS area illustrates that the doping type of described second doped region 109 adulterates for N-type with described first area I.As an embodiment, the concrete technology parameter adopting ion implantation technology to form described second doped region 109 is: described N-type Doped ions is arsenic or antimony, and the energy of ion implantation is 1kev to 40kev, and ion implantation dosage is 1E14atom/cm
2to 5E18atom/cm
2.
In other embodiments of the present invention, described second doped region is light doping section, then described side wall is the offset side wall forming light doping section; Follow-up at offset side wall both sides formation master wall, with institute's master wall for mask, in the Semiconductor substrate of first grid structure both sides, form heavily doped region.
Please refer to Figure 16, remove described second photoresist layer 108(and please refer to Figure 15) and the second antireflecting coating 107(of second area II please refer to Figure 15).
The technique removing second antireflecting coating 107 of the second photoresist layer 108 and second area II please refer to the present invention and removes the first photoresist layer 105(and please refer to Fig. 9) and the first antireflecting coating 104(of first area I please refer to Fig. 9) technique, do not repeat them here.
In the present embodiment, described second doped region 109 and described first doped region 106 are heavily doped region, and the side wall of first grid structure 110 both sides and the side wall of second grid structure 120 both sides are the master wall forming heavily doped region.
In other embodiments of the present invention, in the Semiconductor substrate of described first area, in doped region and described second area Semiconductor substrate, doped region is light doping section and heavily doped region.Before formation heavily doped region, in first area Semiconductor substrate and second area Semiconductor substrate, form light doping section, the forming step that the forming step of described light doping section can provide with reference to the present embodiment Fig. 4 to Figure 16, do not repeat them here.
Follow-up technique also comprises: carry out annealing in process to described Semiconductor substrate; Form the first metal silicide at the semiconductor substrate surface of described first grid structure both sides, form the second metal silicide at the semiconductor substrate surface of described second grid structure both sides.
To sum up, technical scheme provided by the invention has the following advantages:
First, in the present embodiment, bottom photoresist layer, define antireflecting coating, described antireflecting coating stops the reflection of light, thus makes photoresist layer uniform exposure, forms the accurate photoresist layer of figure, improves the accuracy of technique, avoids generating process deviation.
Secondly, in the present embodiment, be formed with side wall film between Semiconductor substrate and antireflecting coating, the described side wall film protection Semiconductor substrate technique removing antireflecting coating that is not etched destroyed, avoid causing damage to Semiconductor substrate, improve the evenness of semiconductor substrate surface; Follow-up when semiconductor substrate surface forms metal silicide, described metal silicide and semiconductor substrate surface interfacial state well, are conducive to the contact resistance reducing semiconductor device, thus improve the driveability of semiconductor device.
Again, in the present embodiment, after returning the described side wall film of etching, form side wall; Described side wall is formed after etching removes antireflecting coating, avoids the impact that side wall is subject to etching technics; Therefore, the width of the side wall formed in the present embodiment is comparatively large, and described side wall effectively can stop that in the metal silicide of follow-up formation, easy diffusion ion diffuses to undesirably region, thus improves the reliability of semiconductor device; And due to the width of the side wall formed comparatively large, distant between the doped region of follow-up formation, prevent from interpenetrating between adjacent doped region, further the electric property of optimization semiconductor device.
Finally, the present embodiment have employed excellent technique and removes photoresist layer and remaining antireflecting coating, concrete, cineration technics is adopted to remove described photoresist layer and remaining antireflecting coating, further reduce the damage of technique to Semiconductor substrate, improve the evenness of Semiconductor substrate, improve the reliability of semiconductor device.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a formation method for semiconductor device, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises first area and second area, and described first area semiconductor substrate surface has first grid structure, and described second area semiconductor substrate surface has second grid structure;
Form the side wall film covering described first grid structure, second grid structure and Semiconductor substrate;
Form the antireflecting coating covering described side wall film;
Antireflecting coating surface in described first area forms photoresist layer;
With described photoresist layer for mask, etching removes the antireflecting coating of second area;
With described photoresist layer for mask, return the side wall film of etching second area, form side wall at second area semiconductor substrate surface, and described side wall is positioned at second grid structure both sides.
2. the formation method of semiconductor device according to claim 1, is characterized in that, described side wall film is single layer structure or sandwich construction.
3. the formation method of semiconductor device according to claim 2, is characterized in that, when described side wall film is single layer structure, described side wall film is silicon nitride layer or silicon oxide layer; When described side wall film is sandwich construction, described side wall film is the sandwich construction of silicon oxide layer and silicon nitride layer.
4. the formation method of semiconductor device according to claim 1, is characterized in that, adopts anisotropic etch process to return the side wall film of etching second area.
5. the formation method of semiconductor device according to claim 1, is characterized in that, adopts spin coating proceeding to form described antireflecting coating.
6. the formation method of semiconductor device according to claim 1, is characterized in that, the thickness of described antireflecting coating is 100 dust to 2000 dusts.
7. the formation method of semiconductor device according to claim 1, is characterized in that, the forming step that the antireflecting coating surface in described first area forms photoresist layer is: form the initial lithographic glue-line covering antireflecting coating; By exposure imaging technique, remove the initial lithographic glue-line being positioned at the antireflecting coating surface of second area, the antireflecting coating surface in described first area forms photoresist layer.
8. the formation method of semiconductor device according to claim 1, is characterized in that, adopts dry etch process etching to remove the antireflecting coating of second area.
9. the formation method of semiconductor device according to claim 8, is characterized in that, described dry etch process is reactive ion etching.
10. the formation method of semiconductor device according to claim 1, is characterized in that, described antireflecting coating is organic antireflective coating.
The formation method of 11. semiconductor device according to claim 10, is characterized in that, also comprise step: with described photoresist layer for mask, in the Semiconductor substrate of described second grid structure both sides, form doped region; Remove the antireflecting coating of described photoresist layer and first area.
The formation method of 12. semiconductor device according to claim 11, is characterized in that, adopts cineration technics to remove the antireflecting coating of photoresist layer and first area.
The formation method of 13. semiconductor device according to claim 11, is characterized in that, described doped region is light doping section or heavily doped region.
The formation method of 14. semiconductor device according to claim 13, is characterized in that, adopts ion implantation technology to form described doped region.
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| CN106558494A (en) * | 2015-09-29 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor device |
| CN107785421A (en) * | 2016-08-29 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN108597991A (en) * | 2018-05-11 | 2018-09-28 | 上海华力集成电路制造有限公司 | Photoresist etch-back manufacturing method thereof |
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