CN102789983B - The manufacture method of transistor - Google Patents
The manufacture method of transistor Download PDFInfo
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- CN102789983B CN102789983B CN201110126367.4A CN201110126367A CN102789983B CN 102789983 B CN102789983 B CN 102789983B CN 201110126367 A CN201110126367 A CN 201110126367A CN 102789983 B CN102789983 B CN 102789983B
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Abstract
A manufacture method for transistor, comprising: provide substrate, forms transistor, the disilicide layer be positioned on the source/drain region of transistor over the substrate successively, and described transistor comprises grid, the protective layer be positioned on grid; Substrate forms sacrifice layer, and the upper surface of described sacrifice layer is at least higher than the grid of transistor; Remove partial sacrificial layer, until expose the protective layer on the grid of transistor; Remove the protective layer be positioned on grid; Remove residue sacrifice layer.In the manufacture method of transistor provided by the invention, the sacrifice layer be positioned on transistor can protect disilicide layer, disilicide layer is only removed on a small quantity, and then reduces the higher problem of disilicide layer contact resistance.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of manufacture method of transistor.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed, larger data storage amount and more function faster, and semiconductor chip is to more high integration future development.And the integrated level of semiconductor chip is higher, the characteristic size (CD, CriticalDimension) of semiconductor device is less.At present, in very lagre scale integrated circuit (VLSIC), characteristic size has entered into the scope that tens arrive hundreds of nanometer.
The schematic diagram of prior art transistor fabrication process is shown referring to figs. 1 to Fig. 2.
First, please refer to Fig. 1, form multiple transistor over the substrate 10, particularly, described transistor comprises NFET (N-type field effect transistor), PFET (P type field effect transistor).For NFET; described transistor comprises the grid structure be positioned on substrate 10; described grid structure comprises the gate dielectric layer 16 be positioned at successively on substrate 10, grid 13, protective layer 14; surround the side wall of described grid 13 and protective layer 14, described side wall comprises the monox lateral wall 18 surrounding grid 13 and protective layer 14, the silicon nitride spacer 12 surrounding described monox lateral wall 18.The substrate 10 of described grid structure both sides is formed with source region (drain region) 17.The substrate 10 of position, described source region (drain region) 17 is formed with disilicide layer (silicide) 15.Wherein, described in be positioned at protective layer 14 on grid 13 for when carrying out ion implantation to source region (drain region) 17, prevent grid 13 from being damaged by ion, particularly, the material of described protective layer 14 is silicon nitride, and thickness exists
scope in, the thickness of described silicon nitride spacer 12 exists
scope in.After above described disilicide layer 15, extended meeting forms plug structure, and described disilicide layer 15 can play the effect reducing contact resistance.
With reference to figure 2, after completing ion implantation step, by stress close to protective layer 14, silicon nitride spacer 12 described in technology (StressProximityTechnology, SPT) selective removal.But, in SPT etching process, easily remove part disilicide layer 15, the contact resistance of the plug structure of follow-up formation can be made like this to become large.
Be can find more manufacture methods about existing transistor in the Chinese patent application of CN101393894A at publication number.
Summary of the invention
The problem that the present invention solves is to provide a kind of manufacture method of transistor, reduces contact resistance and becomes large problem.
For solving the problem, the invention provides a kind of manufacture method of transistor, comprising: substrate is provided, form transistor, the disilicide layer be positioned on the source/drain region of transistor over the substrate successively, described transistor comprises grid, the protective layer be positioned on grid; Substrate forms sacrifice layer, and the upper surface of described sacrifice layer is at least higher than the grid of transistor; Remove partial sacrificial layer, until expose the protective layer on the grid of transistor; Remove the protective layer be positioned on grid; Remove residue sacrifice layer.
The material of described sacrifice layer is BARC.
Described removal partial sacrificial layer, until the step exposing the grid of transistor comprises: remove partial sacrificial layer by dry quarter or ashing.
Described ashing comprises and passes into oxygen to sacrifice layer.
The material of described protective layer is silicon nitride, and the step of the protective layer that described removal is positioned on grid comprises: carve by dry the protective layer removed and be positioned on grid.
The described step by removing the protective layer be positioned on grid dry quarter comprises: remove partial protection layer by the first dry quarter; Residual protective layer is removed by the second dry quarter.
Described first dry quarter adopts CF
4gas; Second dry quarter adopted CH
2f
2, CH
3one or both gases in F.
The described method removing residue sacrifice layer comprises: remove residue sacrifice layer by cineration technics.
The step that substrate is formed sacrifice layer comprises: form the sacrifice layer covering described transistor.
The thickness of grid exists
scope in, the thickness being positioned at the protective layer on grid exists
scope in.
The thickness of sacrifice layer exists
scope in.
Compared with prior art, the present invention has the following advantages: the sacrifice layer be positioned on transistor can protect disilicide layer, makes disilicide layer only be removed destruction on a small quantity, reduces disilicide layer and is destroyed and the higher problem of the contact resistance caused.
Accompanying drawing explanation
Fig. 1 ~ Fig. 2 is the manufacture method cross-sectional view of the transistor of prior art;
Fig. 3 is the schematic flow sheet of transistor fabrication process one execution mode of the present invention;
Fig. 4 ~ Fig. 9 is the cross-sectional view of the transistor that transistor fabrication process one embodiment of the present invention is formed.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Described by background technology, the manufacture method of prior art transistor can remove part disilicide layer, the contact resistance of the plug structure of follow-up formation can be made like this to become large, and then cause the decline of transistor performance.For the problems referred to above, the present inventor proposes a kind of manufacture method of transistor, please refer to the schematic flow sheet of a transistor fabrication process of the present invention execution mode shown in Fig. 3.Described method roughly comprises the following steps:
Step S1, substrate is provided, form transistor over the substrate successively, the disilicide layer be positioned on source transistor drain region, described transistor comprises the protective layer be positioned on grid, surrounds the first side wall of described grid and protective layer and surrounds the second side wall of described first side wall;
Step S2, substrate forms sacrifice layer;
Step S3, removes partial sacrificial layer, until expose the protective layer on the grid of transistor;
Step S4, removes the protective layer be positioned on grid;
Step S5, removes residue sacrifice layer;
Step S6, removes the second side wall.
Below in conjunction with specific embodiment, technical scheme of the present invention is described in detail.In order to technical scheme of the present invention is described better, please refer to the transistor fabrication process cross-sectional view of the one embodiment of the invention shown in Fig. 4 ~ Fig. 9.
First, please refer to Fig. 4, perform step S1, substrate 100 is provided, described substrate 100 forms multiple MOS transistor, substrate 100 described in the present embodiment is formed with NMOS tube, PMOS.Wherein, described substrate 100 can be monocrystalline silicon or SiGe; Also can be silicon-on-insulator (Silicononinsulator, SOI); Or other material can also be comprised, such as: the III-V such as GaAs.Described substrate 100 can also have isolation structure 101, and for isolating NMOS tube and PMOS, described isolation structure 101 can be that shallow trench isolation is from (STI) or local oxidation isolation (LOCOS).
Particularly, described metal-oxide-semiconductor comprises the grid structure be positioned on substrate 100, and is positioned at the source region (drain region) 107 on the substrate of described grid structure both sides.
The step forming metal-oxide-semiconductor is included on substrate and forms grid structure, and described grid structure comprises the grid oxic horizon 106 be positioned at successively on substrate, grid 103, protective layer 104, surrounds the side wall 108 on described grid 103 and protective layer 104 sidewall, wherein,
In the present embodiment, the thickness of described grid 103 exists
scope in.
Described side wall 108 comprises the first side wall surrounding described grid 103 and protective layer 104 sidewall and the second side wall surrounding described first side wall, and particularly, described first side wall is silica, and the second side wall is silicon nitride.
Described protective layer 104 is for being formed in the process in source region (drain region) 107 subsequently through ion implantation, protection grid 103 is not by the damage of injecting ion.Particularly, the material of described protective layer 104 is silicon nitride, and thickness exists
scope in.
Form metal-oxide-semiconductor also to comprise and on the substrate of grid 103 both sides, form source region (drain region) 107 by ion implantation.Also be included on source region (drain region) 107 and form disilicide layer 105, behind the top of described disilicide layer 105, extended meeting forms plug structure, and described disilicide layer 105 can play the effect reducing plug structure contact resistance.
Form the materials and process that uses of metal-oxide-semiconductor on the substrate 100 same as the prior art, do not repeat them here.
With reference to figure 5, perform step S2, form sacrifice layer 109, described sacrifice layer 109 for protecting disilicide layer 105 in the step of follow-up removal protective layer, and the upper surface of described sacrifice layer 109 is at least higher than the grid of transistor.
Meanwhile, in order to play the effect of protective transistor, preferably, the thickness of described sacrifice layer 109 is comparatively large, can cover described transistor.
Therefore, selection and comparison is little in the step of follow-up removal protective layer material need be selected as sacrifice layer 109, in addition, because follow-up also needs removes sacrifice layer 109, therefore need to select the material being convenient to remove as sacrifice layer 109.
Particularly, described sacrifice layer 109 is bottom antireflective coating (BottomAnti-ReflectCoating, BARC), and described BARC is the organic film of carbon containing.
It should be noted that, if described sacrifice layer 109 is thicker, the difficulty of follow-up removal sacrifice layer 109 technique can be caused.Therefore, preferably, the thickness of described sacrifice layer 109 exists
scope in.
With reference to figure 6; perform step S3; remove partial sacrificial layer 109; in the present embodiment; described sacrifice layer 109 is BARC, can be carved or partial sacrificial layer 109 is removed in ashing by dry, makes the upper surface of remaining sacrifice layer 109 and the upper surface flush of grid 103 or the upper surface lower than grid 103; thus exposed completely by the protective layer 104 above grid 103, so that subsequent step is removed described protective layer 104.
Particularly, described BARC can be removed by dry quarter or ashing.Remove BARC technique by ashing to comprise: pass into the etching gas comprising oxygen, the organic film BARC of described carbon containing and oxygen reaction form carbon dioxide, because carbon dioxide is that gas is easily removed, and then reach the object removing sacrifice layer 109.
It should be noted that, need control when removing BARC by ashing to remove speed.
Also it should be noted that, by measuring the removal speed of ashing sacrifice layer 109 in advance, then being removed the thickness of partial sacrificial layer 109 by time controling.
With reference to figure 7, perform step S4, remove the protective layer 104 on grid 103 by etching.The selection and comparison of described etching step to protective layer 104 and sacrifice layer 109 is large; in the process removing protective layer 104; larger damage can not be had to sacrifice layer 109; therefore; in the process removing protective layer 104; described sacrifice layer 109 protects the disilicide layer 105 be positioned at below it, avoids the damage of disilicide layer 105, and then prevents the problem that causes contact resistance to become large.
In the present embodiment, the material of described protective layer 104 is silicon nitride, and thickness exists
scope in, described silicon nitride can be removed by dry lithography, particularly, the method little to grid 103 selection and comparison need be selected to remove described protective layer 104.
In order to improve removal efficiency, preferably, two-step dry carving technology (comprising the first dry quarter and the second dry quarter) can be adopted, comprise the following steps particularly:
CF is adopted in first dry quarter
4gas removes most of the nitrogen SiClx;
Gas CH is adopted in second dry quarter
2f
2, CH
3one or both gas in F removes residual silicon nitride.
In above-mentioned steps, the CF that dry carving technology adopts
4gas and CH
2f
2, CH
3during one or both gases in F, can not have obvious removal effect to BARC, therefore sacrifice layer 109 can protect disilicide layer 105 effectively, improves the contact resistance of disilicide layer 105,
Meanwhile, CF is adopted
4gas efficiency can remove silicon nitride higher, and adopts CH
2f
2/ CH
3f removes silicon nitride and can accomplish higher to the Selection radio of grid, thus reduction process at dry quarter is to the damage of grid 103, improves the contact resistance of grid 103.
In the process removing protective layer 104, only can pass through CF
4gas removes most of the nitrogen SiClx, and on grid 103, retain residual silicon nitride, removes residual silicon nitride afterwards in subsequent step again, grid 103 can be protected injury-free so on the one hand, saves step on the other hand, raises the efficiency.
With reference to figure 8, perform step S5, described sacrifice layer 109 is removed by cineration technics, the material of described sacrifice layer is BARC, can remove described sacrifice layer 109, similarly by ashing method original position, in podzolic process, in hot conditions to BARC (organic film of carbon containing) by oxygen, to form carbon dioxide, thus remove sacrifice layer 109.
With reference to figure 9, perform step S6, remove the second side wall by dry lithography in the present embodiment, particularly, described second side wall is silicon nitride spacer, and the thickness of described second side wall exists
scope in, in dry carving technology, adopt CHF
3, CH
2f
2, CH
3one or more gases in F, carry out isotropic etching to the second side wall, to remove silicon nitride spacer.
It should be noted that, after removal sacrifice layer 109, expose disilicide layer 105, therefore in the process of removal second side wall, disilicide layer 105 can be partially removed.But, due to the thickness of the second side wall less (
), compared with prior art (SPT removes protective layer and silicon nitride spacer simultaneously, removes thickness and exists
scope in), therefore the removal amount when removal the second side wall is less, therefore in the process of removal second side wall, only have very low amount disilicide layer 105 to be removed, disilicide layer 105 can not be made to be subject to badly damaged, thus reduce the higher problem of disilicide layer contact resistance.
It should be noted that, for situation grid 103 retaining residual nitrogen SiClx, can while removal silicon nitride spacer, in same dry quarter step, remove described residual silicon nitride.
Described transistor fabrication process is follow-up also to be comprised, and at deposited on substrates interlayer dielectric layer, grid 103, disilicide layer 105 is formed the step of connector etc., does not repeat them here.
To sum up, the invention provides a kind of manufacture method of transistor, decrease the damage of disilicide layer by sacrifice layer protection disilicide layer, thus reduce the higher problem of the disilicide layer contact resistance that causes because disilicide layer is destroyed.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (9)
1. a manufacture method for transistor, is characterized in that, comprising: provide substrate, forms transistor, the disilicide layer be positioned on the source/drain region of transistor over the substrate successively, and described transistor comprises grid, the protective layer be positioned on grid; Substrate forms sacrifice layer, and described sacrifice layer is the organic film of carbon containing, described sacrifice layer to cover on described disilicide layer and the upper surface of described sacrifice layer at least higher than the grid of transistor; Remove partial sacrificial layer, make the upper surface of upper surface lower than grid of remaining sacrifice layer, to expose the protective layer on the grid of transistor; Remove the protective layer be positioned on grid; Oxygen is passed into remove residue sacrifice layer by cineration technics and to expose described disilicide layer to described sacrifice layer.
2. the manufacture method of transistor as claimed in claim 1, it is characterized in that, the material of described sacrifice layer is BARC.
3. the manufacture method of transistor as claimed in claim 2, is characterized in that, described removal partial sacrificial layer, until the step exposing the grid of transistor comprises: remove partial sacrificial layer by dry quarter or ashing.
4. the manufacture method of transistor as claimed in claim 1, it is characterized in that, the material of described protective layer is silicon nitride, and the step of the protective layer that described removal is positioned on grid comprises: carve by dry the protective layer removed and be positioned on grid.
5. the manufacture method of transistor as claimed in claim 4, is characterized in that, the described step by removing the protective layer be positioned on grid dry quarter comprises: remove partial protection layer by the first dry quarter; Residual protective layer is removed by the second dry quarter.
6. the manufacture method of transistor as claimed in claim 5, is characterized in that, described first dry quarter adopts CF
4gas; Second dry quarter adopted CH
2f
2, CH
3one or both gases in F.
7. the manufacture method of transistor as claimed in claim 1, it is characterized in that, the step that substrate is formed sacrifice layer comprises: form the sacrifice layer covering described transistor.
8. the manufacture method of transistor as claimed in claim 1, it is characterized in that, the thickness of grid exists
scope in, the thickness being positioned at the protective layer on grid exists
scope in.
9. the manufacture method of transistor as claimed in claim 8, it is characterized in that, the thickness of sacrifice layer exists
scope in.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110126367.4A CN102789983B (en) | 2011-05-16 | 2011-05-16 | The manufacture method of transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110126367.4A CN102789983B (en) | 2011-05-16 | 2011-05-16 | The manufacture method of transistor |
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| CN102789983A CN102789983A (en) | 2012-11-21 |
| CN102789983B true CN102789983B (en) | 2015-11-25 |
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| CN104517843B (en) * | 2013-09-29 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN108666220A (en) * | 2017-03-30 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (5)
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|---|---|---|---|---|
| CN1591829A (en) * | 2003-08-28 | 2005-03-09 | 力晶半导体股份有限公司 | Automatic-aligning method silicide mfg. method |
| CN101114650A (en) * | 2006-07-26 | 2008-01-30 | 国际商业机器公司 | Method and structure for self-aligned device contacts |
| CN101207027A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device grids |
| CN101853813A (en) * | 2009-03-31 | 2010-10-06 | 台湾积体电路制造股份有限公司 | Semiconductor device and fabricating method thereof |
| CN102024754A (en) * | 2009-09-17 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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2011
- 2011-05-16 CN CN201110126367.4A patent/CN102789983B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591829A (en) * | 2003-08-28 | 2005-03-09 | 力晶半导体股份有限公司 | Automatic-aligning method silicide mfg. method |
| CN101114650A (en) * | 2006-07-26 | 2008-01-30 | 国际商业机器公司 | Method and structure for self-aligned device contacts |
| CN101207027A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device grids |
| CN101853813A (en) * | 2009-03-31 | 2010-10-06 | 台湾积体电路制造股份有限公司 | Semiconductor device and fabricating method thereof |
| CN102024754A (en) * | 2009-09-17 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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