CN102789429B - 支持页属性的虚拟地址至物理地址的转换 - Google Patents

支持页属性的虚拟地址至物理地址的转换 Download PDF

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Publication number
CN102789429B
CN102789429B CN201210167652.5A CN201210167652A CN102789429B CN 102789429 B CN102789429 B CN 102789429B CN 201210167652 A CN201210167652 A CN 201210167652A CN 102789429 B CN102789429 B CN 102789429B
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memory address
physical memory
page
address
instruction
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CN102789429A (zh
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O·法里克
B-Z·弗莱德曼
J·D·多维科
E·维斯曼
J·B·克罗斯兰德
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/507—Control mechanisms for virtual memory, cache or TLB using speculative control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/684—TLB miss handling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
CN201210167652.5A 2007-06-01 2008-05-30 支持页属性的虚拟地址至物理地址的转换 Active CN102789429B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/757,103 2007-06-01
US11/757,103 US8799620B2 (en) 2007-06-01 2007-06-01 Linear to physical address translation with support for page attributes
CN2008101000501A CN101315614B (zh) 2007-06-01 2008-05-30 支持页属性的虚拟地址至物理地址的转换

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CN102789429A CN102789429A (zh) 2012-11-21
CN102789429B true CN102789429B (zh) 2016-06-22

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CN2008101000501A Expired - Fee Related CN101315614B (zh) 2007-06-01 2008-05-30 支持页属性的虚拟地址至物理地址的转换

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US (7) US8799620B2 (enExample)
JP (5) JP2008299844A (enExample)
CN (2) CN102789429B (enExample)
DE (1) DE102008025476A1 (enExample)
GB (1) GB2449749B (enExample)

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CN108132894B (zh) * 2017-12-23 2021-11-30 天津国芯科技有限公司 一种cpu中tlb多命中异常的定位装置及方法

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JP6567618B2 (ja) 2019-08-28
US20220050791A1 (en) 2022-02-17
US8799620B2 (en) 2014-08-05
DE102008025476A1 (de) 2008-12-18
US20140304488A1 (en) 2014-10-09
US20140351553A1 (en) 2014-11-27
JP2008299844A (ja) 2008-12-11
JP2012123814A (ja) 2012-06-28
US20140351554A1 (en) 2014-11-27
CN102789429A (zh) 2012-11-21
GB2449749B (en) 2010-03-03
US20080301398A1 (en) 2008-12-04
US20160041921A1 (en) 2016-02-11
US9158703B2 (en) 2015-10-13
US11074191B2 (en) 2021-07-27
US9164916B2 (en) 2015-10-20
JP2016066372A (ja) 2016-04-28
GB2449749A (en) 2008-12-03
US20180060246A1 (en) 2018-03-01
JP2014067445A (ja) 2014-04-17
CN101315614A (zh) 2008-12-03
GB0809264D0 (en) 2008-06-25
US9164917B2 (en) 2015-10-20
CN101315614B (zh) 2012-07-04
JP2018022508A (ja) 2018-02-08
JP5855632B2 (ja) 2016-02-09
JP6212102B2 (ja) 2017-10-11

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