CN102779807A - RDL (radiological defense laboratory) technology-compatible inductive component and manufacture method - Google Patents
RDL (radiological defense laboratory) technology-compatible inductive component and manufacture method Download PDFInfo
- Publication number
- CN102779807A CN102779807A CN2012100128523A CN201210012852A CN102779807A CN 102779807 A CN102779807 A CN 102779807A CN 2012100128523 A CN2012100128523 A CN 2012100128523A CN 201210012852 A CN201210012852 A CN 201210012852A CN 102779807 A CN102779807 A CN 102779807A
- Authority
- CN
- China
- Prior art keywords
- metal
- layer
- inductance
- forms
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention relates to an RDL (radiological defense laboratory) technology-compatible inductive component and a manufacture method. The method is characterized by comprising the following steps of: using a thin film metal deposition technology on a silicon substrate and simultaneously forming a first layer metal interconnection transmission line and a shielding layer; carrying out the spin coating of a photosensitive medium layer, and developing in an exposure way, forming into a metal interconnection through hole, annealing, performing dry etching on plasmas to remove the developing remaining part, and filling the metal interconnection through hole with plated metal; forming a second layer metal interconnection transmission line and an inductance coil; forming an outermost layer metal through hole; and manufacturing an electrical inductor with the metal shielding layer under the condition that the original technological steps are not increased. The invention is compatible with the main-stream re-wiring technology in wafer level encapsulation, under the condition that the technological steps are not increased, the electrical inductor with the shielding layer can be manufactured at low cost, the substrate eddy current of the silicon substrate can be effectively cut off, the quality factor of the electric inductor can be improved, the series resistance of the electric inductor can be reduced, and the electromagnetic interference of the vortex current to a chip can be reduced.
Description
Technical field
The present invention relates to a kind of and inductance element and manufacturing approach the RDL process compatible, relate to the manufacturing of passive device in a kind of wafer level packaging or rather, inductance element and manufacturing approach in the layer (RDL) that can be used for rerouting.
Background technology
Along with the development of radio communication, radio frequency microwave circuit is at wireless personal communication, wireless lan (wlan), and satellite communication has obtained extensive use in the automotive electronics.Increasing function is just continual to be integrated in the various handheld devices, and the size of equipment is also dwindled what do not stop simultaneously.Miniaturization, low cost, low power consuming, high performance demand continues to increase.
Inductance uses in circuit in a large number, and at matching network, filter plays an important role in the low noise amplifier.Tradition inductance spare is all restricting development of integrated circuits from the area to the cost.Integrated passive devices reaches the high advantage of reliability less with its miniaturization, film-type, parasitic parameter and satisfied the demand that current electronic product is low-cost, in light weight, integrated level is high, ultra-thin, and is remarkable to improving the chip performance effect.
Because traditional packaging cost is higher, can't satisfy the superiority that demonstrates fully the embedded passive device.Disc grade chip size encapsulation (WLCSP) is with its low cost, and small size has obtained extensive use in electronic product, Amkor (Ultra CSP
TM), Fraunhofer, Fujitsu (Super CSP
TM), Form Factor (Wow
TM, MOST
TM) wait many companies and research institution that the Wafer-Level Packaging Technology of oneself is all arranged.Embedding passive device can be good at satisfying requirements such as miniaturization, low cost, low-power consumption in wafer level packaging.
An important indicator of inductance is quality factor, and quality factor are high more, and the efficient of inductance element is just high more.The raising of quality factor has received restriction and the influence of the resistance of inductance line own of the ghost effect of substrate.Therefore current optimization work to the silicon planar spiral inductor mainly can be divided into two types, and one type is the square resistance that reduces inductance, as increasing the thickness of coil, selects for use the lower Cu of resistivity as coil metal.
Another kind of is exactly to start with from substrate with reducing substrate loss.Document Zu, L.; Yicheng Lu; Frye, R.C.; Lau, M.Y.; Chen, S.-C.S.; Kossives, D.P.; Jenshan Lin; Tai, K.L.; , " High Q-factor inductors integrated on MCM Si substrates, " IEEE Transactions on, vol.19, no.3, pp.635-643, Aug 1996 adopts the High Resistivity Si substrate to reduce substrate loss, but the High Resistivity Si cost is higher.Document Chang, J.Y.-C.; Abidi, A.A.; Gaitan, M.; " Large suspended inductors on silicon and their use in a 2-μ m CMOS RF amplifier, " Electron Device Letters, IEEE; Vol.14; No.5, pp.246-248, employings such as May 1993 are emptied the substrate under the inductance and are reduced substrate loss.Representative in these methods of suspension inductance type can the most effectively reduce substrate loss and parasitic capacitance.The shortcoming of suspension inductance is: the macroscopic-void of the inductance substrate that suspends on the one hand need adopt MEMS technology; This technology and CMOS technology are incompatible; Be difficult to realize that the full chip of RF receiver is integrated; The mechanical strength of inductance of suspending on the other hand is little, for the mechanical strength of improving the suspension inductance often need increase some technology trivial step, is unfavorable for commercial production.
And for example, document Chang, C.A.; Sung-Pi Tseng; Jun Yi Chuang; Shiue-Shr Jiang; Yeh, J.A.; " Characterization of spiral inductors with patterned floating structures, " Microwave Theory and Techniques, IEEE Transactions on; Vol.52; No.5, pp.1375-1381, May 2004 usefulness P/N joint groove make shielding construction and block the substrate eddy current and reduce substrate loss under coil inductance.But the making of PN joint groove has increased processing step, and can pollute existing device on the disk.
Inductance from the visible high quality factor of making based on wafer level packaging RDL technology of top discussion because its cost is low, with the wafer level packaging process compatible, in the radio circuit field, has boundless application prospect.Thereby be guided out design of the present invention.
Summary of the invention
In order to adapt to the miniaturization of product, the cost degradation growth requirement the present invention proposes band screen planar spiral inductor and manufacture method with the RDL process compatible.The inductance that described method is made has screen, can effectively block the substrate eddy current to silicon substrate, has improved the quality factor of inductance and has reduced the series resistance of inductance, and reduced the electromagnetic interference of vortex current to chip.
The technical scheme that the present invention taked is: utilize electroplating technology or aluminium etching process to form special metal screen layer when inductance bridge line and ground floor metal reroute forming earlier; On dielectric layer, form the second layer metal transmission line that reroutes then with the electroplating technology of sputter, photoetching; Form plane inductive coil simultaneously, planar coil and the metal screen layer under it constitute inductance jointly.
The screen that the present invention adds can effectively be blocked the substrate eddy current, improves the quality factor of inductance, and has reduced the electromagnetic interference of vortex current to chip, has improved the performance and the Electro Magnetic Compatibility thereof of inductance.And layer RDL technology that reroutes in the present invention and the wafer level packaging is compatible fully, need not increase processing step, can form simultaneously with the layer that reroutes, thereby is reducing aspect passive device volume, the reduction packaging cost very big potentiality are arranged.
Concrete processing step of the present invention is following:
A. can adopt in following two kinds of technologies any to form ground floor reroute metal transport layer, inductance bridge line and metal screen layer;
A1. utilize sputter, photoetching and electroplating technology
(a) sputtering seed layer on substrate or substrate;
(b) spin coating photoresist, exposure imaging forms the reroute opening of metal transport layer, inductance bridge line and metal screen layer of ground floor;
(c) plated metal is preferably aluminium, forms ground floor reroute metal transport layer, inductance bridge line and metallic shield layer pattern;
(d) dissolving barrier layer photoresist, etching relict sublayer;
A2. utilize the aluminium etching process
(a) splash-proofing sputtering metal aluminium on substrate;
(b) spin coating photoresist, exposure imaging forms the reroute mask of metal transport layer, inductance bridge line and metal screen layer of ground floor;
(c) the aluminium corrosion forms ground floor metal interconnecting wires, inductance bridge line and metallic shield layer pattern;
(d) remove photoresist;
A1 and A2 choose any one kind of them.A1 technology can be electroplated less metal of resistance value such as Cu, and electroplated metal thickness is thicker.A2 technology is simple, has avoided electroplating technology.
B. photoetching process forms dielectric layer
(a) spin coating photosensitive medium can be light-sensitive polyimide or photosensitive BCB;
(b) soft baking, exposure imaging forms metal interconnected via trench, annealing;
(c) plasma dry is carved and is removed the development nubbin.
C. utilize sputter, photoetching and electroplating technology to form the second layer reroute metal transport layer and planar spiral inductor;
(a) sputtering seed layer;
(b) spin coating photoresist, exposure imaging forms the reroute mask of metal transport layer and planar spiral inductor of the second layer;
(c) plated metal is preferably copper, forms the second layer reroute metal transport layer and planar spiral inductor figure;
(d) dissolving barrier layer photoresist, etching relict sublayer;
D. photoetching process forms protective dielectric layer
(a) spin coating photosensitive medium can be light-sensitive polyimide or photosensitive BCB;
(b) soft baking, exposure imaging forms metal interconnected opening, is convenient to realize being electrically connected or planting soldered ball, annealing with other devices or system;
(c) plasma dry is carved and is removed the development nubbin.
The inductance element of the band screen of being made by above-mentioned technology is characterised in that:
(1) described inductance element is made up of planar spiral inductor coil and the aplysia punctata metal screen layer under it; Described inductance coil is plane side's helical coil or flat circle helical coil; The bridge line and the metal screen layer of described inductance coil are positioned at same plane;
(2) for the flat circle helical coil, the trend of screen ray is consistent with the normal direction of the round helical coil on it; For plane side's helical coil, the trend of screen ray is with vertical with the corresponding edge of square helical coil on it;
(3) the ray live width of aplysia punctata metal screen layer is that 0.1 μ m is to 20 μ m; Beeline is that 1 μ m is to 30 μ m between the ray of aplysia punctata metal screen layer;
(4) behind step C successively repeating step B, C to form multilayer interconnection line and inductive graph;
(5) only form screen figure, through hole and inductive graph in the technical process, do not form the metal interconnection line;
(6) substrate in the steps A is for carrying out the reroute disk of accomplishing CMOS technology or MEMS technology of technology of wafer level packaging;
(7) before the steps A, on substrate, form the passivation separator, separation layer thickness 0.1 μ m is preferably 1.2 μ m to 5 μ m;
(8) before the steps A, coated media layer on substrate, hypothallus thickness be 2 μ m to 50 μ m, be preferably 10 μ m;
(9) metal thickness described in the steps A be 0.1 μ m to 5 μ m, be preferably 0.2 μ m;
(10) preferable alloy among the step C is Cu;
(11) in the steps A thickness of metal be 1 μ m to 10 μ m, be preferably 5 μ m;
(12) inductance is shaped as round spirality, hexagon spirality or square spirality;
(13) described dielectric layer material is polyimides or BCB.
This shows, the present invention relates to a kind of and inductance element and manufacturing approach the RDL process compatible, it is characterized in that on silicon substrate, forming metal interconnected transmission line of ground floor and screen simultaneously with the film metal depositing technics; The spin coating photosensitive dielectric layer, exposure imaging forms metal interconnected through hole, annealing, plasma dry is carved and is removed the development nubbin, and plated metal fills up metal interconnected through hole; Form second layer metal interlinked transfer line and inductance line then; Form the outermost metal through hole; Thereby under the situation that does not increase original processing step, produce the inductance of metal screen layer.With the process compatible that reroutes in the wafer level packaging of main flow; Under the situation that does not increase processing step; Low cost produces the inductance that has screen; Silicon substrate is effectively blocked the substrate eddy current, improved the quality factor of inductance and reduced the series resistance of inductance, and reduced the electromagnetic interference of vortex current chip.
Description of drawings
Fig. 1 is described inductance element that comprises band aplysia punctata metal screen layer and RDL the reroute vertical view (a) and the sectional view (b) of layer structure.
Fig. 2 utilizes sputter, photoetching and electroplating technology to form metal interconnecting wires, inductance bridge line and screen figure.(a) sputtering seed layer, (b) photoetching development forms opening, (c) electroplates and forms metal level, (d) removes photoresist and remaining Seed Layer.Because metal level Seed Layer down is extremely thin and with the metal level thawing, so begin to draw no longer in the drawings from Fig. 2 d.
Fig. 3 utilizes the aluminium etching process to form metal interconnecting wires, inductance bridge line and screen figure.(a) metallic aluminium sputter, (b) thin glue photoetching development forms the barrier layer, and (c) the aluminium corrosion forms figure.
Fig. 4 photoetching process forms dielectric layer and cloth line three-way hole.
Fig. 5 utilizes sputter, photoetching and electroplating technology to form second layer metal interconnection line and planar spiral inductor.
Fig. 6 protective layer medium forms.
Embodiment
For advantage of the present invention and good effect are found full expression, substantive distinguishing features of the present invention and obvious improvement are described further below in conjunction with accompanying drawing and embodiment.
As shown in Figure 1,106 is aplysia punctata metallic shield layer pattern, its every wide 10 μ m of ray, and shortest spacing is 30 μ m between adjacent two rays, every ray trend is vertical with the square spiral inductance corresponding edge on it, has effectively weakened vortex current.Reroute metal transport layer 104 (a), inductance bridge line 105 (a) and aplysia punctata metal screen layer 106 of ground floor is deposited on the substrate 101 through thin-film technique simultaneously, and substrate 101 can be embedding standard silicon chip or the common silicon chip that chip is arranged.Passivation barrier 102 can be SiO
2, medium with low dielectric constant or the layering of the two combination, be used to reduce the ground floor coupling between metal transport layer 104 (a) and the substrate 101 of rerouting, but make substrate 101 planarizations and the embedding substrate 101 that chip is arranged of insulation blocking.Dielectric layer 103 is preferably medium with low dielectric constant, like polyimides or BCB.First is deposited on when rerouting metal transport layer 104 (a), inductance bridge line 105 (a) and aplysia punctata metal screen layer 106 and has accomplished the induction structure of optimizing under the situation that does not increase any processing step, has practiced thrift cost, has improved inductance performance.
Fig. 2 is to form each step sketch map that inductance element and RDL reroute layer to Fig. 6.
Fig. 2 among the embodiment with the reroute schematic flow sheet of metal transport layer 104 (a), inductance bridge line 105 (a) and aplysia punctata metal screen layer 106 of photoetching electroplating technology formation ground floor.(a) sputtering seed layer 107 on substrate at first in.(b) the spin coating photoresist 108, and exposure imaging forms figure.(c) plated metal forms first reroute metal transport layer 104 (a), inductance bridge line 105 (a) and the aplysia punctata metal screen layer 106.(d) dissolving barrier layer photoresist 108, etching electroplating relict sublayer 107.Reroute metal transport layer 104 (a), inductance bridge line 105 (a) and aplysia punctata metal screen layer 106 of ground floor forms.
Fig. 3 among the embodiment with aluminium etching process formation first reroute metal level 104 (a), inductance bridge line 105 (a) and aplysia punctata metal screen layer 106.(a) splash-proofing sputtering metal aluminium on substrate at first.(b) the spin coating photoresist 108, carry out exposure imaging form first reroute metal level 104 (a), inductance bridge line 105 (a) and aplysia punctata metal screen layer 106 the figure that stops.(c) corrosion aluminium, and remove photoresist formation figure.Technology among Fig. 2 and Fig. 3 can be chosen one of which wantonly.
Fig. 4 is the formation sketch map of dielectric layer.(a) the low K photosensitive medium 103 of spin coating can be polyimides or BCB, and preceding baking makes dielectric layer stable.(b) exposure imaging forms the metal throuth hole groove, and annealing is solidified, and the plasma dry etching is removed the development nubbin.
Fig. 5 is through the sputtering seed layer, and photoetching forms the opening of second layer metal wiring transmission line and snail coil pattern then, then electroplates and forms second layer metal wiring transmission and snail coil pattern.Remove photoresist and relict sublayer.
Fig. 6 forms protective dielectric layer, and K photosensitive medium 103 is hanged down in spin coating, and exposure imaging forms that opening is convenient follow-uply to be electrically connected or to plant ball, and annealing is solidified.
The inductance element and first or second that it must be emphasized that the band screen reroutes, and the metal transport layer forms simultaneously.
Claims (9)
1. inductance element with screen is characterized in that 1. described inductance element is made up of planar spiral inductor coil and the aplysia punctata metal screen layer under it; 2. described inductance coil is plane side's helical coil or flat circle helical coil; 3. the bridge line of described inductance coil and metal screen layer are positioned at same plane.
2. inductance element as claimed in claim 1 is characterized in that: for the flat circle helical coil, the trend of screen ray is consistent with the normal direction of the round helical coil on it; For plane side's helical coil, the trend of screen ray is with vertical with the corresponding edge of square helical coil on it.
3. inductance element as claimed in claim 1 is characterized in that: the ray live width of aplysia punctata metal screen layer is that 0.1 μ m is to 20 μ m; Beeline is that 1 μ m is to 30 μ m between the ray of aplysia punctata metal screen layer.
4. make method like each described inductance element among the claim 1-3; It is characterized in that utilizing earlier electroplating technology or aluminium etching process to form metal screen layer when inductance bridge line and ground floor metal reroute forming; On dielectric layer, form the second layer metal transmission line that reroutes then with the electroplating technology of sputter, photoetching; Form plane inductive coil simultaneously, inductance coil and the metal screen layer under it constitute inductance jointly.
5. method as claimed in claim 4 is characterized in that concrete steps are:
A. adopt the bridge line and the metal screen layer of any formation metal interconnecting wires, inductance coil in following two kinds of technologies;
A1. utilize sputter, photoetching and electroplating technology
(a) sputtering seed layer on substrate or substrate;
(b) spin coating photoresist, exposure imaging, the opening of formation ground floor metal interconnecting wires, inductance bridge line and metal screen layer;
(c) plated metal is preferably aluminium, forms ground floor metal interconnecting wires, inductance bridge line and metallic shield layer pattern;
(d) dissolving barrier layer photoresist, etching relict sublayer;
A2. utilize the aluminium etching process
(a) splash-proofing sputtering metal aluminium on substrate;
(b) spin coating photoresist, exposure imaging, the mask of formation ground floor metal interconnecting wires, inductance bridge line and metal screen layer;
(c) the aluminium corrosion forms ground floor metal interconnecting wires, inductance bridge line and metallic shield layer pattern;
(d) remove photoresist;
B. photoetching process forms dielectric layer
(a) spin coating photosensitive medium can be light-sensitive polyimide or photosensitive BCB;
(b) soft baking, exposure imaging forms metal interconnected via trench, annealing;
(c) plasma dry is carved and is removed the development nubbin;
C. utilize sputter, photoetching and electroplating technology to form second layer metal interconnection line and planar spiral inductor.
(a) sputtering seed layer;
(b) spin coating photoresist, exposure imaging forms the reroute mask of metal transport layer and planar spiral inductor of the second layer;
(c) plated metal copper forms the second layer reroute metal transport layer and planar spiral inductor figure;
(d) dissolving barrier layer photoresist, etching relict sublayer;
D. photoetching process forms protective dielectric layer
(a) spin coating photosensitive medium can be light-sensitive polyimide or photosensitive BCB;
(b) soft baking, exposure imaging forms metal interconnected opening, is convenient to realize being electrically connected or planting soldered ball, annealing with other devices or system;
(c) plasma dry is carved and is removed the development nubbin.
6. method as claimed in claim 5 is characterized in that behind step C repeating step B and C are to form multilayer interconnection transmission line and inductive graph successively.
7. method as claimed in claim 5 is characterized in that:
1. before steps A, on substrate, form the passivation separator, said passivation separation layer thickness is 0.1-5 μ m;
2. before steps A, the thickness of coated media layer is 2-50 μ m on substrate;
3. the metal layer thickness 0.1-5 μ m described in the steps A;
4. described shapes of inductors is circle spirality, hexagon spirality or square spirality;
5. described dielectric layer material is polyimides or BCB.
8. method as claimed in claim 7 is characterized in that:
1. the passivation separation layer thickness is 1.2 μ m;
2. the thickness of dielectric layers that applies is 10 μ m;
3. the described metal thickness of steps A is 0.2 μ m.
9. like claim 4 or 5 described methods, it is characterized in that inductance element and first or second with the screen metal transport layer that reroutes forms simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100128523A CN102779807A (en) | 2012-01-16 | 2012-01-16 | RDL (radiological defense laboratory) technology-compatible inductive component and manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100128523A CN102779807A (en) | 2012-01-16 | 2012-01-16 | RDL (radiological defense laboratory) technology-compatible inductive component and manufacture method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102779807A true CN102779807A (en) | 2012-11-14 |
Family
ID=47124671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012100128523A Pending CN102779807A (en) | 2012-01-16 | 2012-01-16 | RDL (radiological defense laboratory) technology-compatible inductive component and manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102779807A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103247606A (en) * | 2013-04-16 | 2013-08-14 | 江阴长电先进封装有限公司 | High-inductance-value silica-based planar spiral inductor structure |
| CN104051413A (en) * | 2013-03-14 | 2014-09-17 | 新加坡商格罗方德半导体私人有限公司 | Device with integrated passive component |
| CN104425463A (en) * | 2013-09-09 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Integrated passive device structure and manufacturing method thereof |
| CN105185907A (en) * | 2015-09-01 | 2015-12-23 | 中国科学院上海微系统与信息技术研究所 | Manufacturing method of high-density inductor |
| CN105244313A (en) * | 2015-09-08 | 2016-01-13 | 上海航天测控通信研究所 | Interconnection manufacturing method for film through holes in substrate |
| CN106298735A (en) * | 2016-08-22 | 2017-01-04 | 杭州电子科技大学 | The three dimensional inductor structure of a kind of high quality factor and processing technology thereof |
| CN107946236A (en) * | 2017-11-22 | 2018-04-20 | 华进半导体封装先导技术研发中心有限公司 | A kind of wafer-level packaging line layer interconnection integrated inductor and its manufacture method |
| CN109205550A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | MEMS devices structure and forming method thereof |
| CN109599489A (en) * | 2018-10-12 | 2019-04-09 | 复旦大学 | High q-factor three-dimensional spiral structure inductance based on MEMS technology and preparation method thereof |
| CN109643665A (en) * | 2016-08-22 | 2019-04-16 | 高通股份有限公司 | More size pads encapsulation based on face grid |
| CN109712960A (en) * | 2017-10-25 | 2019-05-03 | 台湾积体电路制造股份有限公司 | Integrated circuit and its forming method and semiconductor device |
| CN111446527A (en) * | 2020-04-09 | 2020-07-24 | 中国电子科技集团公司第十三研究所 | Method for manufacturing double-layer silicon-based filter based on three-dimensional inductor |
| CN113078055A (en) * | 2021-03-23 | 2021-07-06 | 浙江集迈科微电子有限公司 | Irregular wafer interconnection structure and interconnection process |
| TWI830116B (en) * | 2021-08-31 | 2024-01-21 | 台灣積體電路製造股份有限公司 | Semiconductor device and method of fabricating the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1666342A (en) * | 2003-05-29 | 2005-09-07 | 三菱电机株式会社 | Semiconductor device |
| CN1825579A (en) * | 2005-01-31 | 2006-08-30 | 三洋电机株式会社 | Circuit substrate structure and circuit apparatus |
| CN1979852A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Domain structure of increwing induction quality factor |
| US20110068433A1 (en) * | 2009-09-24 | 2011-03-24 | Qualcomm Incorporated | Forming radio frequency integrated circuits |
| CN102169860A (en) * | 2011-01-31 | 2011-08-31 | 日月光半导体制造股份有限公司 | Semiconductor structure with passive component structure and manufacturing method thereof |
-
2012
- 2012-01-16 CN CN2012100128523A patent/CN102779807A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1666342A (en) * | 2003-05-29 | 2005-09-07 | 三菱电机株式会社 | Semiconductor device |
| CN1825579A (en) * | 2005-01-31 | 2006-08-30 | 三洋电机株式会社 | Circuit substrate structure and circuit apparatus |
| CN1979852A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Domain structure of increwing induction quality factor |
| US20110068433A1 (en) * | 2009-09-24 | 2011-03-24 | Qualcomm Incorporated | Forming radio frequency integrated circuits |
| CN102169860A (en) * | 2011-01-31 | 2011-08-31 | 日月光半导体制造股份有限公司 | Semiconductor structure with passive component structure and manufacturing method thereof |
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104051413A (en) * | 2013-03-14 | 2014-09-17 | 新加坡商格罗方德半导体私人有限公司 | Device with integrated passive component |
| CN103247606B (en) * | 2013-04-16 | 2015-06-17 | 江阴长电先进封装有限公司 | High-inductance-value silica-based planar spiral inductor structure |
| CN103247606A (en) * | 2013-04-16 | 2013-08-14 | 江阴长电先进封装有限公司 | High-inductance-value silica-based planar spiral inductor structure |
| CN104425463B (en) * | 2013-09-09 | 2018-08-24 | 中芯国际集成电路制造(上海)有限公司 | The structure and manufacturing method of integrated passive devices |
| CN104425463A (en) * | 2013-09-09 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Integrated passive device structure and manufacturing method thereof |
| CN105185907A (en) * | 2015-09-01 | 2015-12-23 | 中国科学院上海微系统与信息技术研究所 | Manufacturing method of high-density inductor |
| CN105244313A (en) * | 2015-09-08 | 2016-01-13 | 上海航天测控通信研究所 | Interconnection manufacturing method for film through holes in substrate |
| CN105244313B (en) * | 2015-09-08 | 2017-09-12 | 上海航天电子通讯设备研究所 | Film through-hole interconnection preparation method on substrate |
| CN106298735A (en) * | 2016-08-22 | 2017-01-04 | 杭州电子科技大学 | The three dimensional inductor structure of a kind of high quality factor and processing technology thereof |
| CN106298735B (en) * | 2016-08-22 | 2018-10-02 | 杭州电子科技大学 | A kind of the three dimensional inductor structure and its manufacture craft of high quality factor |
| CN109643665A (en) * | 2016-08-22 | 2019-04-16 | 高通股份有限公司 | More size pads encapsulation based on face grid |
| US10865100B2 (en) | 2017-06-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming micro-electro-mechanical system (MEMS) structure |
| CN109205550A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | MEMS devices structure and forming method thereof |
| CN109205550B (en) * | 2017-06-30 | 2020-11-24 | 台湾积体电路制造股份有限公司 | MEMS device structure and method of forming the same |
| US10804155B2 (en) | 2017-10-25 | 2020-10-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Inductor structure for integrated circuit |
| US10790194B2 (en) | 2017-10-25 | 2020-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Inductor structure for integrated circuit |
| CN109712960A (en) * | 2017-10-25 | 2019-05-03 | 台湾积体电路制造股份有限公司 | Integrated circuit and its forming method and semiconductor device |
| CN109712960B (en) * | 2017-10-25 | 2021-06-15 | 台湾积体电路制造股份有限公司 | Integrated circuit, method of forming the same, and semiconductor device |
| CN107946236B (en) * | 2017-11-22 | 2020-06-02 | 华进半导体封装先导技术研发中心有限公司 | Wafer-level packaging circuit layer interconnection integrated inductor and manufacturing method thereof |
| CN107946236A (en) * | 2017-11-22 | 2018-04-20 | 华进半导体封装先导技术研发中心有限公司 | A kind of wafer-level packaging line layer interconnection integrated inductor and its manufacture method |
| CN109599489A (en) * | 2018-10-12 | 2019-04-09 | 复旦大学 | High q-factor three-dimensional spiral structure inductance based on MEMS technology and preparation method thereof |
| CN111446527A (en) * | 2020-04-09 | 2020-07-24 | 中国电子科技集团公司第十三研究所 | Method for manufacturing double-layer silicon-based filter based on three-dimensional inductor |
| CN111446527B (en) * | 2020-04-09 | 2021-10-15 | 中国电子科技集团公司第十三研究所 | Method for manufacturing double-layer silicon-based filter based on three-dimensional inductor |
| CN113078055A (en) * | 2021-03-23 | 2021-07-06 | 浙江集迈科微电子有限公司 | Irregular wafer interconnection structure and interconnection process |
| CN113078055B (en) * | 2021-03-23 | 2024-04-23 | 浙江集迈科微电子有限公司 | Irregular wafer interconnection structure and interconnection process |
| TWI830116B (en) * | 2021-08-31 | 2024-01-21 | 台灣積體電路製造股份有限公司 | Semiconductor device and method of fabricating the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102779807A (en) | RDL (radiological defense laboratory) technology-compatible inductive component and manufacture method | |
| TWI394186B (en) | A method of manufacturing a coil inductor | |
| KR101045195B1 (en) | An inductor formed in an integrated circuit | |
| CN102522181B (en) | Planar spiral inductor with wide-narrow-alternatingly line width and space | |
| US8826514B2 (en) | Microfabricated inductors with through-wafer vias | |
| US8686522B2 (en) | Semiconductor trench inductors and transformers | |
| WO2011103259A2 (en) | Power inductors in silicon | |
| CN102569032A (en) | Method for manufacturing inductance element by overlapping multiple layers of metalized thin films | |
| US9741655B2 (en) | Integrated circuit common-mode filters with ESD protection and manufacturing method | |
| JP2014168099A (en) | Magnetic film enhanced inductor | |
| US11942428B2 (en) | Inductors with through-substrate via cores | |
| US20180323146A1 (en) | Multi-die inductors with coupled through-substrate via cores | |
| Park et al. | High Q spiral-type microinductors on silicon substrates | |
| US10163558B2 (en) | Vertically stacked inductors and transformers | |
| US20150340338A1 (en) | Conductor design for integrated magnetic devices | |
| TWI489613B (en) | Methods of forming magnetic vias to maximize inductance in integrated circuits and structures formed thereby | |
| CN107492437A (en) | A kind of glass base high Q value inductance and preparation method thereof | |
| Feng et al. | High-performance solenoidal RF transformers on high-resistivity silicon substrates for 3D integrated circuits | |
| CN106207333B (en) | A kind of LC low-pass filter based on through silicon via coupled capacitor | |
| US20140061853A1 (en) | Plated lamination structures for integrated magnetic devices | |
| CN101017816A (en) | Design method for on-chip spiral inductor with the wearing metal conductor line width and gap | |
| US8450830B2 (en) | Forming a ferromagnetic alloy core for high frequency micro fabricated inductors and transformers | |
| CN103824755A (en) | High-Q inductor and preparation method | |
| US20180370792A1 (en) | A method for manufacturing a hollow mems structure | |
| CN112397289A (en) | Novel MEMS high-Q-value non-solenoid integrated inductor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20121114 |