CN103824755A - High-Q inductor and preparation method - Google Patents
High-Q inductor and preparation method Download PDFInfo
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- CN103824755A CN103824755A CN201210465578.5A CN201210465578A CN103824755A CN 103824755 A CN103824755 A CN 103824755A CN 201210465578 A CN201210465578 A CN 201210465578A CN 103824755 A CN103824755 A CN 103824755A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
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Abstract
The invention provides a high-Q inductor and a preparation method. Firstly, the surface of a semiconductor substrate is corroded into a pit shape; then, a support layer is formed on the other surface of the semiconductor substrate; next, an inductor structure containing a plurality of layers of metal coils is formed in a position, corresponding to the deep pit, on the surface of the support layer; and finally, the substrate structure on which the inductor structure is formed is corroded to remove semiconductor substrate material between the pit and the inductor so as to hollow out the semiconductor substrate. Therefore, the Q value of the inductor formed by the method is increased by multiple times compared with that of a traditional integrated inductor; and the method is simple in process and low in cost.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to a kind of high Q inductance and preparation method.
Background technology
Along with the development of radio communication, radio frequency microwave circuit is widely applied in wireless personal communication, wireless lan (wlan), satellite communication, automotive electronics.More and more function is just continual is integrated in various handheld devices, and the size of equipment is also constantly being dwindled simultaneously.Miniaturization, low cost, low power consuming, high performance demand continue to increase.
Inductance is a kind of elements of a large amount of uses in circuit, especially in matching network, filter, low noise amplifier, plays an important role.Traditional electrical sensing unit has all restricted the development of integrated circuit from area to cost.Integrated passive devices need to could meet current electronic product low cost with its miniaturization, film-type, parasitic parameter is few and reliability is high advantage, lightweight, integrated level is high, ultra-thin demand.
Because traditional packaging cost is higher, cannot meet the superiority that fully demonstrates embedded passive device.Wafer-level Chip Scale Package (WLCSP) is with its low cost, and small size is widely applied in electronic product, Amkor (Ultra CSP
tM), Fraunhofer, Fujitsu (Super CSP
tM), Form Factor (Wow
tM, MOST
tM) there is the Wafer-Level Packaging Technology of oneself in Deng Duo company and research institution.In wafer level packaging, embedding passive device can be good at meeting the requirements such as miniaturization, low cost, low-power consumption.
An important indicator of inductance is quality factor, and quality factor are higher, and the efficiency of inductance element is just higher.The raising of quality factor has been subject to the restriction of ghost effect and the impact of the resistance of inductor wire own of substrate.Therefore currently mainly can be divided into two classes to the Optimization Work of silicon planar spiral inductor, a class is the square resistance that reduces inductance, as increased the thickness of coil, selects Cu that resistivity is lower as coil metal.
Another kind ofly start with and reduce substrate loss from substrate exactly.For example,, at document " Zu, L.; Yicheng Lu; Frye, R.C.; Lau, M.Y.; Chen, S.-C.S.; Kossives, D.P.; Jenshan Lin; Tai, K.L.; , " High Q-factor inductors integrated on MCM Si substrates, " IEEE Transactions on, vol.19, no.3, pp.635-643, Aug 1996 " in, adopt HR-Si substrate to reduce substrate loss, its High Resistivity Si cost is higher.And for example, at document " Chang, C.A.; Sung-Pi Tseng; Jun Yi Chuang; Shiue-Shr Jiang; Yeh, J.A.; " Characterization of spiral inductors with patterned floating structures; " Microwave Theory and Techniques, IEEE Transactions on, vol.52, no.5, pp. 1375-1381, May 2004 " in, adopt P/N joint groove under coil inductance, to make shielding construction and block substrate eddy current and reduce substrate loss.But the making of PN joint groove has increased processing step, and can pollute the existing device on disk.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of simple method of preparing high Q inductance of technique.
Another object of the present invention is to provide a kind of high Q inductance.
For achieving the above object and other relevant objects, the invention provides a kind of method of preparing high Q inductance, it at least comprises:
1) surface corrosion of semiconductor base is become to dell shape;
2) form supporting layer on another surface of described semiconductor base;
3) form with respect to the position of dell the induction structure that comprises multiple layer metal coil on the surface of described supporting layer;
4) underlying structure that forms induction structure is corroded, remove the semiconductor-based bottom material between dell and induction structure, make semiconductor base be worn sky.
Preferably, the depth bounds of dell is: semiconductor base thickness deducts 30 μ m and deducts 200 μ m to semiconductor base thickness.
Preferably, the material of described supporting layer comprises benzocyclobutene or polyimides.
Preferably, the thickness range of the layer at each the wire coil place in described induction structure is that 0.5 μ m is to 20 μ m.
Preferably, described induction structure comprises in surperficial passivation layer.
Preferably, the material of described semiconductor base is ordinary silicon.
Preferably, described induction structure is round spirality, multilateral helical or fold-line-shaped.
High Q inductance provided by the invention, it at least comprises:
Be formed on the supporting layer of the semiconductor-based basal surface of wearing hollow structure; And
In the induction structure of described support layer surface, wherein, it is spatially overlapping that this induction structure comprises that multiple layer metal coil and region and this are worn hollow structure.
Preferably, described induction structure is round spirality, multilateral helical or fold-line-shaped.
As mentioned above, high Q inductance of the present invention and preparation method, have following beneficial effect: processing step is simple, with other process compatibles, with low cost, and the inductance Q value of preparation has improved several times than traditional integrated inductor, particularly evident at HFS, there are very large potentiality in integrated passive devices field.
Accompanying drawing explanation
Fig. 1 to Fig. 7 is shown as the flow chart of the method for the high Q inductance of preparation of the present invention.
Element numbers explanation
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Refer to Fig. 1 to Fig. 7.It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, when its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
The method of the high Q inductance of preparation of the present invention at least comprises the following steps:
The first step a: surface corrosion of semiconductor base is become to dell shape.Wherein, the material of semiconductor base is preferably ordinary silicon.
For example, select a silicon substrate 100 as semiconductor base, first to these silicon substrate 100 surface preparations, and at silicon substrate 100 upper and lower surface deposited silicon nitrides as corrosion barrier layer 101; A surface formation corrosion window that is dry-etched in subsequently silicon substrate 100 by photoetching development, as shown in Figure 1, wherein, label 102 is photoresist; Then again this silicon substrate 100 is put into KOH anisotropic etch solution, thereby go out dell in these silicon substrate 100 1 surface corrosions, as shown in Figure 2.Wherein, the remaining silicon substrate thickness in dell bottom, between 30 μ m to 200 μ m, is preferably 50 μ m.
Second step: another surface at described semiconductor base forms supporting layer.
For example, as supporting layer 103, and it is carried out to softcure at the surperficial spin coating benzocyclobutene (BCB) without dell of the silicon substrate 100 shown in Fig. 2 or polyimides (PI) dielectric material, as shown in Figure 3.
The 3rd step: the surface at described supporting layer forms with respect to the position of dell the induction structure that comprises multiple layer metal coil.
For example, first, in the surperficial first sputtered with Ti W/Cu Seed Layer of the supporting layer 103 shown in Fig. 3, after photoetching development, the metallic copper of the about 7um of re-plating, removes photoresist subsequently, and remove the TiW/Cu Seed Layer of exposure with dry etching, thus the first metal wire ring layer 104 formed, as shown in Figure 4.
Wherein, these the first metal wire ring layer 104 thickness be 0.5 μ m to 20 μ m, be preferably 7 μ m, can be rounded, polygon, fold-line-shaped etc.
Then, at the body structure surface that has formed the first metal wire ring layer 104, the polymer such as the photosensitive BCB of spin coating or PI is as dielectric layer again, then photoetching development forms through hole, and it is firmly curing that the polymer such as BCB or PI is carried out to high temperature, and remove the residual organic substance of via bottoms with plasma etching, as shown in Figure 5; Sputtered with Ti W/Cu Seed Layer more subsequently, and after photoetching development, the metallic copper of the about 7um of re-plating, removes photoresist subsequently again, and remove the TiW/Cu Seed Layer of exposure with dry etching, thus form the second metal wire ring layer 106, as shown in Figure 6.
Wherein, the second metal wire ring layer 106 thickness be 0.5 μ m to 20 μ m, be preferably 7 μ m, shape can be identical with the shape of the first metal wire ring layer 104, thereby make formed induction structure be round spirality, multilateral helical or fold-line-shaped etc.Preferably, the induction structure forming is Archimedian screw shape, so that the smooth high-frequency loss of transition is little.
The 4th step: the underlying structure that forms induction structure is corroded, remove the semiconductor-based bottom material between dell and induction structure, semiconductor base is emptied.
For example, the structure shown in Fig. 6 is put into the alkaline solution such as KOH or TMAH and erode the excess silicon of dell bottom, thereby the silicon base under this induction structure is emptied, form and empty structure 107.
Again for example, use XeF
2isotropic etching gas falls the remaining silicon etching in dell bottom of the structure shown in Fig. 6.
Thus, based on above-mentioned preparation method, the high Q inductance that preparation forms comprises: the supporting layer 103 that is formed on semiconductor base 100 surfaces with structure emptied 107; And induction structure in described supporting layer 103 surfaces.
Wherein, this induction structure at least comprises: the first metal wire ring layer 104, dielectric layer 105 and the second inductor wire ring layer 106, this induction structure is with to empty structure 107 spatially overlapping.
As a kind of optimal way, in aforementioned the 3rd step, forming after the second metal wire ring layer, can continue to prepare the 3rd metal wire ring layer .... N metal wire ring layer, and after the last one deck wire coil layer forming, then adopt and form passivation layer materials such as gold on surface.Wherein, N is more than or equal to 3.Prepare thus the induction structure that comprises N layer metal wire ring layer and passivation layer.
In sum, the method of the high Q inductance of preparation of the present invention adopts the mode of wet etching and dry etching combination to empty the silicon substrate below planar coil inductance, thereby suppress substrate loss, improve inductance Q value, preparation technology of the present invention is simple, and the present invention can adopt common low-resistance silicon as substrate, with low cost.So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (10)
1. a method of preparing high Q inductance, is characterized in that, the method for the high Q inductance of described preparation at least comprises:
1) surface corrosion of semiconductor base is become to dell shape;
2) form supporting layer on another surface of described semiconductor base;
3) form with respect to the position of dell the induction structure that comprises multiple layer metal coil on the surface of described supporting layer;
4) underlying structure that forms induction structure is corroded, remove the semiconductor-based bottom material between dell and induction structure, semiconductor base is emptied.
2. the method for the high Q inductance of preparation according to claim 1, is characterized in that: the depth bounds of dell is: semiconductor base thickness deducts 30 μ m and deducts 200 μ m to semiconductor base thickness.
3. the method for the high Q inductance of preparation according to claim 1, is characterized in that: the material of described supporting layer comprises benzocyclobutene or polyimides.
4. the method for the high Q inductance of preparation according to claim 1, is characterized in that: the thickness range of the layer at each the wire coil place in described induction structure is that 0.5 μ m is to 20 μ m.
5. according to the method for the high Q inductance of the preparation described in claim 1 or 4, it is characterized in that: described induction structure comprises in surperficial passivation layer.
6. the method for the high Q inductance of preparation according to claim 1, is characterized in that: the material of described semiconductor base is ordinary silicon.
7. according to the method for the high Q inductance of the preparation described in claim 1 or 4, it is characterized in that: described induction structure is round spirality, multilateral helical or fold-line-shaped.
8. a high Q inductance, is characterized in that, described high Q inductance at least comprises:
Be formed on the supporting layer of the semiconductor-based basal surface of emptying structure;
In the induction structure of described support layer surface, wherein, it is spatially overlapping that this induction structure comprises that multiple layer metal coil and region and this are emptied structure.
9. high Q inductance according to claim 8, is characterized in that: the material of described supporting layer comprises benzocyclobutene or polyimides.
10. high Q inductance according to claim 1, is characterized in that: described induction structure is round spirality, multilateral helical or fold-line-shaped.
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| CN201210465578.5A CN103824755A (en) | 2012-11-16 | 2012-11-16 | High-Q inductor and preparation method |
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| CN201210465578.5A CN103824755A (en) | 2012-11-16 | 2012-11-16 | High-Q inductor and preparation method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9509251B2 (en) | 2015-03-24 | 2016-11-29 | Freescale Semiconductor, Inc. | RF amplifier module and methods of manufacture thereof |
| US9787254B2 (en) | 2015-09-23 | 2017-10-10 | Nxp Usa, Inc. | Encapsulated semiconductor device package with heatsink opening, and methods of manufacture thereof |
| US9871107B2 (en) | 2015-05-22 | 2018-01-16 | Nxp Usa, Inc. | Device with a conductive feature formed over a cavity and method therefor |
| CN107705971A (en) * | 2017-08-30 | 2018-02-16 | 歌尔股份有限公司 | A kind of manufacture method of coil, coil, electronic equipment |
| US10075132B2 (en) | 2015-03-24 | 2018-09-11 | Nxp Usa, Inc. | RF amplifier with conductor-less region underlying filter circuit inductor, and methods of manufacture thereof |
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| US5384274A (en) * | 1992-04-06 | 1995-01-24 | Nippon Precision Circuits Inc. | Method of making a combined semiconductor device and inductor |
| US20040036569A1 (en) * | 2002-08-20 | 2004-02-26 | Asia Pacific Microsystems, Inc. | Three-dimensional intergrated inductor, its module and fabrication method of the same |
| CN101580223A (en) * | 2009-06-18 | 2009-11-18 | 大连理工大学 | Manufacturing method of a piezoelectric micro-cantilever beam probe |
| CN101997506A (en) * | 2009-08-07 | 2011-03-30 | 索尼公司 | High frequency device |
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2012
- 2012-11-16 CN CN201210465578.5A patent/CN103824755A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5384274A (en) * | 1992-04-06 | 1995-01-24 | Nippon Precision Circuits Inc. | Method of making a combined semiconductor device and inductor |
| US20040036569A1 (en) * | 2002-08-20 | 2004-02-26 | Asia Pacific Microsystems, Inc. | Three-dimensional intergrated inductor, its module and fabrication method of the same |
| CN101580223A (en) * | 2009-06-18 | 2009-11-18 | 大连理工大学 | Manufacturing method of a piezoelectric micro-cantilever beam probe |
| CN101997506A (en) * | 2009-08-07 | 2011-03-30 | 索尼公司 | High frequency device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9509251B2 (en) | 2015-03-24 | 2016-11-29 | Freescale Semiconductor, Inc. | RF amplifier module and methods of manufacture thereof |
| US10075132B2 (en) | 2015-03-24 | 2018-09-11 | Nxp Usa, Inc. | RF amplifier with conductor-less region underlying filter circuit inductor, and methods of manufacture thereof |
| US9871107B2 (en) | 2015-05-22 | 2018-01-16 | Nxp Usa, Inc. | Device with a conductive feature formed over a cavity and method therefor |
| US9787254B2 (en) | 2015-09-23 | 2017-10-10 | Nxp Usa, Inc. | Encapsulated semiconductor device package with heatsink opening, and methods of manufacture thereof |
| CN107705971A (en) * | 2017-08-30 | 2018-02-16 | 歌尔股份有限公司 | A kind of manufacture method of coil, coil, electronic equipment |
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