CN102738089B - Semiconductor package and its module - Google Patents
Semiconductor package and its module Download PDFInfo
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- CN102738089B CN102738089B CN201210058206.0A CN201210058206A CN102738089B CN 102738089 B CN102738089 B CN 102738089B CN 201210058206 A CN201210058206 A CN 201210058206A CN 102738089 B CN102738089 B CN 102738089B
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- chip
- minor tick
- electron device
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Abstract
Present invention is disclosed a kind of encapsulating structure, including：Chip of the side formed with optical electron device, and the substrate of the covering chip；Master space part is provided between the chip and substrate, it is characterised in that at least one layer of minor tick part being additionally provided between the chip and substrate between the optical electron device and master space part.Compared with prior art, the present invention between the optical electron device and master space part by setting minor tick part, to prevent the chip stress problem of Cracking caused by chip size is excessive, and avoid because distance piece excessively widens and caused by gluing inequality problem, so as to lift chip package quality.
Description
Technical field
The present invention relates to field of semiconductor manufacture technology, more particularly to a kind of semiconductor package and its module.
Background technology
Crystal wafer chip dimension encapsulation technology（Wafer Level Chip Size Packaging, WLCSP）It is to whole
Wafer cuts to obtain the technology of single finished product chip again after being packaged test.Wherein, the technology mainly passes through one piece of band
The high light transmittance glass for having more distance pieces is covered in above optical electron device to enter to the optical electron device of chip wafer
Row protection.As shown in Figure 1 and Figure 2, in the prior art, carried out using a ＇ of high light transmittance glass 13 with the more ＇ of distance piece 12
The encapsulation of chip wafer, wherein, the generation type of distance piece is：One layer of photoresistance of spin coating on the ＇ of glass 13 of a high-transmittance, then
The ＇ of one circle distance piece 12 is formed by exposure imaging mode, it is then that high light transmittance glass of the full wafer with distance piece and one is same
The ＇ of chip wafer 11 of size is combined by sticking glue laminated, to realize to the ＇ of optics electronic device 14 on chip wafer
Protection.
In the prior art, often through the edge shape for designing different walls, such as jagged edge, to solve asking for excessive glue
Topic, and increase the support force of chip by widening distance piece.However, it is directed to larger-size chip, single layer of spacer pair
The support of chip is limited, and chip stress problems of crack is easily caused in subsequent manufacturing processes, certainly will reduce the function of chip
And reliability.
The content of the invention
An object of the present invention is to provide a kind of new semiconductor package, and it passes through in the optical electron device
Minor tick part is set between part and master space part, to prevent the chip stress problem of Cracking caused by chip size is excessive.
It is another object of the present invention to provide a kind of new semiconductor module.
One of correspondingly, for achieving the above object, a kind of encapsulating structure provided by the invention, including：
Chip of the side formed with optical electron device, and the substrate of the covering chip；
Master space part is provided between the chip and substrate, it is characterised in that be additionally provided with position between the chip and substrate
At least one layer of minor tick part between the optical electron device and master space part, the master space part and the minor tick part
It is bonding that the surface of optical electron device is provided with chip by adhesive, to support the chip simultaneously, wherein, it is described
Minor tick part is 40 ~ 100um including the distance between some spaced sub- distance pieces, the primary and secondary distance piece, described time
The width of distance piece is 80 ~ 260um, and master space part and minor tick the part thickness is 10 ~ 60um.
As a further improvement on the present invention, the master space part is shaped as closed ring.
As a further improvement on the present invention, the minor tick part, which is provided with, holds glue space.
As a further improvement on the present invention, the sub- distance piece is bar shaped.
Correspondingly, to realize the another object of foregoing invention, a kind of semiconductor module provided by the invention, the semiconductor
Module includes any one semiconductor package as described above.
Compared with prior art, the present invention between the optical electron device and master space part by setting minor tick
Part, to prevent the chip stress problem of Cracking caused by chip size is excessive, and avoid because distance piece excessively widens and caused by
Gluing inequality problem, so as to lift chip package quality.
Brief description of the drawings
Fig. 1 is the floor map of wafer stage chip distance piece in the prior art；
Fig. 2 is the schematic cross-section of single chip after encapsulation in the prior art；
Fig. 3 is the schematic cross-section of the semiconductor module of an embodiment of the present invention；
Fig. 4 be an embodiment of the present invention encapsulation after single chip schematic cross-section；
Fig. 5 A are the structural representations of the first embodiment spacers of encapsulating structure of the present invention；
Fig. 5 B are the structural representations of the second embodiment spacers of encapsulating structure of the present invention；
Fig. 5 C are the structural representations of the 3rd embodiment spacers of encapsulating structure of the present invention；
Fig. 6 is the step flow chart of the embodiment of manufacture method one of chip of the present invention.
Embodiment
Below with reference to embodiment shown in the drawings, the present invention will be described in detail.But these embodiments are simultaneously
The present invention is not limited, structure that one of ordinary skill in the art is made according to these embodiments, method or functionally
Conversion is all contained in protection scope of the present invention.
As shown in figure 3, the semiconductor module of an embodiment of the present invention, includes semiconductor encapsulating structure, a camera lens
Component, and the filter layer 21 being arranged between the semiconductor package and the lens assembly, wherein, the lens assembly
Including lens container 23, the lens bracket 25 being arranged in the lens container 23, and fixed and set by the lens bracket 25
At least one camera lens 27 put.
As shown in figure 4, in a preferred embodiment of the invention, the encapsulating structure includes chip 10 and substrate 13, because
For crystal wafer chip dimension encapsulation technology（Wafer Level Chip SizePackaging, WLCSP）It is that full wafer wafer is entered
Cut to obtain the technology of single finished product chip again after row packaging and testing, so realizing on whole piece wafer needs by set specification
Formed with several optical electron devices 12（An optical electron device is correspondingly arranged on a chip）.
In the preferred embodiment, substrate 13 is a high light transmittance glass, and a master is supported by between chip 10 and substrate 13
Minor tick part 15 of the distance piece 14 and one between optical electron device 12 and master space part 14.Preferably, primary and secondary distance piece
（14、15）It is formed at by exposure imaging mode on a side surface of substrate 13, certainly, this distance piece can also be that separation is set
The element put, it, which is acted on, essentially consists in support chip and one accommodation space of interval formation between chip and substrate, is protected with reaching
Protect the purpose of optical electron device.Preferably, primary and secondary distance piece（14、15）Can be by adhesive with being set on chip wafer 10
Have that the surface of optical electron device 12 is bonding, certainly, in other embodiments, it is only necessary to by primary and secondary distance piece wherein it
One and crystal grain be provided with optics side it is bonding.Preferably, epoxy resin can be selected in such a adhesive.It is worth one
It is mentioned that, in other embodiment of the present invention, above-mentioned minor tick part can not merely be arranged to one layer, it can also be provided that more
Layer, its shape are also unrestricted.By increasing the structure of minor tick part, when encapsulating some size larger chips, it is possible to have
Effect avoids the phenomenon for causing chip stress to ftracture because support of the single layer of spacer to chip is limited, meanwhile, it also avoid increasing
The shortcomings that gluing is uneven caused by monospace part width, so as to greatly reduce excessive glue, the probability without glue, improves chip
Reliability.
Illustrate the structure of primary and secondary distance piece in some preferred embodiments of the present invention below with reference to Fig. 5 A ~ 5C.
Join first shown in Fig. 5 A, in first embodiment of the invention, being shaped as of primary and secondary distance piece surround optical electron
The closed ring that device area is set, it is highly preferred that some can be set to hold glue space 151 on minor tick part, to reduce glue
The danger in optics area is spilled over to, these hold the shape in glue space and quantity is unrestricted, can be circular hole, square hole, sawtooth pattern etc.
Deng.
Join shown in Fig. 5 B, in second embodiment of the invention, minor tick part is shaped as surrounding optical electron device region
The discontinuous annular that domain is set, i.e., set some gaps 152, now this distance piece is exactly by between some height on minor tick part
Spacing body forms, and this little distance piece can be bar shaped, circular arc, square, " L " shape and other any irregular figures.Equally
, the quantity of the position in these gaps is also unrestricted.
Join shown in Fig. 5 C, in third embodiment of the invention, minor tick part is shaped as strip, it is preferable that in order to
Ensure uniform force, between around the optical electron device four strips parallel with its four sides being set secondary
Spacing body, certainly, in other embodiments, the shape of minor tick part can also be other any irregular figures.
In various embodiments of the present invention, the shape of minor tick part is only described, however, the shape of master space part can also
Closed ring or with holes annular or discontinuous annular and strip etc. are arranged as required into, with reference to above-mentioned time
Each embodiment of distance piece, the shape of master space part of the invention are also unrestricted.In addition, in the preferred embodiment of the present invention
In, the distance between primary and secondary distance piece is set as 40 ~ 100um, the width of minor tick part is set as 80 ~ 260um.
The manufacture method of wafer stage chip of the present invention is introduced below in conjunction with Fig. 6.First, there is provided a transparent substrate（Step
S1）, then one layer of photoresistance of spin coating on substrate（Step S2）, and according to the shape of set primary and secondary distance piece, by exposure,
Development（Step S3）Obtain the substrate with primary and secondary distance piece；There is provided a chip wafer formed with optical electron device and
Adhesive（Step S4, S5）；
The surface that primary and secondary distance piece is provided with to optical electron device using adhesive with the chip wafer is bonding
（Step S6）.
The present invention between the optical electron device and master space part by setting minor tick part, to prevent because of chip chi
It is very little it is excessive cause chip stress problem of Cracking, for large size chip, double, Spaced part design add chip with
The contact area of high light transmittance glass, reduce the risk that chip splits；Turn avoid increase monospace part width simultaneously causes
Gluing inequality the shortcomings that, so as to greatly reduce excessive glue, the probability without glue.
It should be appreciated that although the present specification is described in terms of embodiments, not each embodiment only includes one
Individual independent technical scheme, this narrating mode of specification is only that those skilled in the art will should say for clarity
For bright book as an entirety, the technical scheme in each embodiment may also be suitably combined to form those skilled in the art can
With the other embodiment of understanding.
Those listed above is a series of to be described in detail only for feasibility embodiment of the invention specifically
Bright, they simultaneously are not used to limit the scope of the invention, all equivalent implementations made without departing from skill spirit of the present invention
Or change should be included in the scope of the protection.
Claims (5)
1. a kind of encapsulating structure, including：
Chip of the side formed with optical electron device, and the substrate of the covering chip；
Master space part is provided between the chip and substrate, it is characterised in that be additionally provided between the chip and substrate positioned at institute
At least one layer of minor tick part between optical electron device and master space part is stated, the master space part and the minor tick part are logical
Cross adhesive and surface of the chip provided with optical electron device is bonding, to support the chip simultaneously, prevent chip stress
Cracking, wherein, the minor tick part is including the distance between some spaced sub- distance pieces, the primary and secondary distance piece
40 ~ 100um, the width of the minor tick part is 80 ~ 260um, and master space part and minor tick the part thickness is 10 ~ 60um.
2. encapsulating structure according to claim 1, it is characterised in that the master space part is shaped as closed ring.
3. encapsulating structure according to claim 1, it is characterised in that the minor tick part, which is provided with, holds glue space.
4. encapsulating structure according to claim 1, it is characterised in that the sub- distance piece is bar shaped.
5. a kind of semiconductor module, it is characterised in that the semiconductor module is included such as any one institute of Claims 1-4
The encapsulating structure stated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210058206.0A CN102738089B (en) | 2012-03-07 | 2012-03-07 | Semiconductor package and its module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210058206.0A CN102738089B (en) | 2012-03-07 | 2012-03-07 | Semiconductor package and its module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102738089A CN102738089A (en) | 2012-10-17 |
| CN102738089B true CN102738089B (en) | 2018-02-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210058206.0A Active CN102738089B (en) | 2012-03-07 | 2012-03-07 | Semiconductor package and its module |
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| Country | Link |
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| CN (1) | CN102738089B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118623621B (en) * | 2024-08-12 | 2024-10-29 | 河南方圆工业炉设计制造有限公司 | Continuous heating furnace and control method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101431086A (en) * | 2007-11-08 | 2009-05-13 | 采钰科技股份有限公司 | Semiconductor package and its forming method |
| CN101783362A (en) * | 2010-01-22 | 2010-07-21 | 友达光电股份有限公司 | Upper cover structure, packaging structure of luminous element and packaging method for luminous element |
| CN101866912A (en) * | 2009-04-15 | 2010-10-20 | 宇威光电股份有限公司 | Luminous device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6791660B1 (en) * | 2002-02-12 | 2004-09-14 | Seiko Epson Corporation | Method for manufacturing electrooptical device and apparatus for manufacturing the same, electrooptical device and electronic appliances |
| KR100688972B1 (en) * | 2006-06-01 | 2007-03-08 | 삼성전자주식회사 | Display device and manufacturing method thereof |
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2012
- 2012-03-07 CN CN201210058206.0A patent/CN102738089B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101431086A (en) * | 2007-11-08 | 2009-05-13 | 采钰科技股份有限公司 | Semiconductor package and its forming method |
| CN101866912A (en) * | 2009-04-15 | 2010-10-20 | 宇威光电股份有限公司 | Luminous device |
| CN101783362A (en) * | 2010-01-22 | 2010-07-21 | 友达光电股份有限公司 | Upper cover structure, packaging structure of luminous element and packaging method for luminous element |
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| Publication number | Publication date |
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| CN102738089A (en) | 2012-10-17 |
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