CN102738080B - 具有嵌入式光伏电池的阵列基板的制作方法 - Google Patents

具有嵌入式光伏电池的阵列基板的制作方法 Download PDF

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CN102738080B
CN102738080B CN201210253264.9A CN201210253264A CN102738080B CN 102738080 B CN102738080 B CN 102738080B CN 201210253264 A CN201210253264 A CN 201210253264A CN 102738080 B CN102738080 B CN 102738080B
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张鑫狄
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TCL China Star Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种具有嵌入式光伏电池的阵列基板的制作方法,包括以下步骤:步骤1、提供基板;步骤2、在基板上形成缓冲层;步骤3、在缓冲层上形成非晶硅层;步骤4、激光退火,将非晶硅层转变为多晶硅层;步骤5、通过掩膜工艺在多晶硅层上形成预定图形;步骤6、在多晶硅层上形成第一光致抗蚀剂图形,并在该第一光致抗蚀剂图形内注入N+离子;步骤7、在多晶硅层上形成栅极绝缘层;步骤8、在栅极绝缘层上形成第二光致抗蚀剂图形,并在第二该光致抗蚀剂图形内注入N-离子;步骤9、在栅极绝缘层上形成第三光致抗蚀剂图形,并在第三该光致抗蚀剂图形内注入P+离子,并活化;步骤10、在栅极绝缘层上形成第一金属层,并通过掩膜工艺形成栅极;步骤11、在第一金属层上形成第一绝缘层,并氢化该第一绝缘层,以形成氢化绝缘层;步骤12、在第一绝缘层上通过掩膜工艺形成第一沟道;步骤13、在第一绝缘层上形成第二金属层,并通过掩膜工艺形成金属电极,进而形成薄膜晶体管与光伏电池。

Description

具有嵌入式光伏电池的阵列基板的制作方法
技术领域
本发明涉及液晶显示领域,尤其涉及一种具有嵌入式光伏电池的阵列基板的制作方法。
背景技术
液晶显示装置(LCD,Liquid Crystal Display)具有机身薄、省电、无辐射等众多优点,得到了广泛的应用。现有市场上的液晶显示装置大部分为背光型液晶显示装置,其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子,通过玻璃基板通电与否来控制液晶分子改变方向,将背光模组的光线折射出来产生画面。由于液晶显示面板本身不发光,需要借由背光模组提供的光源来正常显示影像,因此,背光模组成为液晶显示装置的关键组件之一。背光模组依照光源入射位置的不同分成侧入式背光模组与直下式背光模组两种。直下式背光模组是将发光光源例如CCFL(Cold Cathode Fluorescent Lamp,阴极萤光灯管)或LED(Light Emitting Diode,发光二极管)设置在液晶显示面板后方,直接形成面光源提供给液晶显示面板。而侧入式背光模组是将背光源LED灯条(Light bar)设于液晶显示面板侧后方的背板边缘,LED灯条发出的光线从导光板(LGP,Light Guide Plate)一侧的入光面进入导光板,经反射和扩散后从导光板出光面射出,再经由光学膜片组以形成面光源提供给液晶显示面板。然而,背光源发出的光只有6%左右可以透过液晶显示面板,这就造成大量光能被浪费。
通常液晶显示面板由彩膜基板(CF,Color Filter)、彩膜基板(TFT,ThinFilm Transistor)、夹于彩膜基板与彩膜基板之间的液晶(LC,Liquid Crystal)及密封胶框(Sealant)组成,其成型工艺一般包括:前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中,前段Array制程主要是形成TFT基板,以便于控制液晶分子的运动;中段Cell制程主要是在TFT基板与CF基板之间添加液晶;后段模组组装制程主要是驱动IC压合与印刷电路板的整合,进而驱动液晶分子转动,显示图像。
光伏电池是通过光电效应或者光化学效应直接把光能转化成电能的装置,为了提高液晶显示装置中的背光源的光的利用率,本领域技术人员在液晶显示面板中加入光伏电池,该光伏电池吸收多余的光能,并将光能转化为电能,为液晶显示面板的元件或配件供电,充分利用背光源所发出的光能,节省了对外部电能的消耗。
然而,现有技术中只是将制作好的光伏电池集成于液晶显示面板中,制程较为复杂,生产周期也较长,进而增加了生产成本。
发明内容
本发明的目的在于提供一种具有嵌入式光伏电池的阵列基板的制作方法,其在形成阵列基板的同时形成光伏电池,制程简单,成本低。
为实现上述目的,本发明提供一种具有嵌入式光伏电池的阵列基板的制作方法,包括以下步骤:
步骤1、提供基板;
步骤2、在基板上形成缓冲层;
步骤3、在缓冲层上形成非晶硅层;
步骤4、激光退火,将非晶硅层转变为多晶硅层;
步骤5、通过掩膜工艺在多晶硅层上形成预定图形;
步骤6、在多晶硅层上形成第一光致抗蚀剂图形,并在该第一光致抗蚀剂图形内注入N+离子;
步骤7、在多晶硅层上形成栅极绝缘层;
步骤8、在栅极绝缘层上形成第二光致抗蚀剂图形,并在第二该光致抗蚀剂图形内注入N-离子;
步骤9、在栅极绝缘层上形成第三光致抗蚀剂图形,并在第三该光致抗蚀剂图形内注入P+离子,并活化;
步骤10、在栅极绝缘层上形成第一金属层,并通过掩膜工艺形成栅极;
步骤11、在第一金属层上形成第一绝缘层,并氢化该第一绝缘层,以形成氢化绝缘层;
步骤12、在第一绝缘层上通过掩膜工艺形成第一沟道;
步骤13、在第一绝缘层上形成第二金属层,并通过掩膜工艺形成金属电极,进而形成薄膜晶体管与光伏电池。
还包括:
步骤14、在第二金属层上形成第二绝缘层,并该第二绝缘层上通过掩膜工艺形成第二沟道;
步骤15、在第二绝缘层上形成平坦化层,并通过掩膜工艺形成第三沟道;
步骤16、在该平坦化层上形成透明导电层,并通过掩膜工艺在该透明导电层上形成预定图案;
步骤17、对该透明导电层进行退火处理。
所述基板为玻璃基板。
所述缓冲层、非晶硅层、第一与第二绝缘层均通过化学气相沉积形成于基板上。
所述第一、第二金属层通过溅射工艺形成。
所述掩膜工艺包括曝光制程、显影制程及蚀刻制程。
所述N+离子、N-离子及P+离子均位于所述多晶硅层。
所述透明导电层为氧化铟锡层。
所述平坦化层为有机层。
本发明的有益效果:本发明具有嵌入式光伏电池的阵列基板的制作方法,在形成阵列基板的同时形成光伏电池,其以简单的制程将光伏电池嵌入阵列基板中,进而利用背光源发出的光线为液晶显示面板元件或配件供电,充分利用背光源所发出的光能,节省了对外部电能的消耗。
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其它有益效果显而易见。
附图中,
图1为本发明具有嵌入式光伏电池的阵列基板的制作方法的流程图;
图2至图18为本发明具有嵌入式光伏电池的阵列基板的制作方法的各制作阶段的结构示意图;
图19为本发明具有嵌入式光伏电池的阵列基板的制作方法制成的阵列基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1至图19,本发明提供一种具有嵌入式光伏电池的阵列基板的制作方法,包括以下步骤:
步骤1、提供基板20,该基板20由可透光材质构成,通常为玻璃基板、石英基板或其他合适的材料的基板。
步骤2、在基板20上形成缓冲层30。
该缓冲层30又名阻挡层,其通过化学气相沉积(Chemical vapor deposition,CVD)形成于基板20上,主要用于以防止杂质扩散到有源层。
步骤3、在缓冲层30上形成非晶硅层40,该非晶硅层40通过化学气相沉积形成于缓冲层30上。
步骤4、激光退火,将非晶硅层40转变为多晶硅层40’。
步骤5、通过掩膜工艺在多晶硅层40’上形成预定图形。
其具体实施方式可为在多晶硅层40’上覆一层感光(photo-sensitive)材料,该层即所谓的光致抗蚀剂层,然后使得光线通过灰阶掩膜或半灰阶掩膜照射于光致抗蚀剂层上以将该光致抗蚀剂层曝光。由于灰阶掩膜或半灰阶掩膜上具有有源区域的图案,将使部分光线得以穿过灰阶掩膜或半灰阶掩膜而照射于光致抗蚀剂层上,使得光致抗蚀剂层的曝光具有选择性,同时借此将灰阶掩膜或半灰阶掩膜上的图案完整的复印至光致抗蚀剂层上。然后,利用合适的显影液剂(developer)除去部分光致抗蚀剂,使得光致抗蚀剂层显现所需要的图案。接着,通过蚀刻工艺将部分多晶硅层40’去除,在此的蚀刻工艺可选用湿式蚀刻、干式蚀刻或两者配合使用。最后,将剩余的图案化的光致抗蚀剂层全部去除,进而形成预定图案的第一多晶硅部42与第二多晶硅部44,在本实施例中,该第一多晶硅部42与第二多晶硅部44分离设置。
步骤6、在多晶硅层40’上形成第一光致抗蚀剂图形,并在该第一光致抗蚀剂图形内注入N+离子。
其具体实施方式可为在多晶硅层40’上覆一层感光材料,通过灰阶掩膜或半灰阶掩膜照对该光致抗蚀剂层曝光,利用合适的显影液剂除去部分光致抗蚀剂,以形成第一光致抗蚀剂图形;在该第一光致抗蚀剂图形上注入N+离子,并去除剩余的图案化的光致抗蚀剂层,进而在缓冲层30上形成第一、第二及第三N+离子部52、54、56,在本实施例中,所述第一与第二N+离子部52、54分别位于第一多晶硅部42的两侧,所述第三N+离子部56位于第二多晶硅部44靠近第一多晶硅部42侧。
步骤7、在多晶硅层40’上形成栅极绝缘层60。
步骤8、在栅极绝缘层60上形成第二光致抗蚀剂图形,并在第二该光致抗蚀剂图形内注入N-离子。
其具体实施方式可为在栅极绝缘层60上覆一层感光材料,通过灰阶掩膜或半灰阶掩膜照对该光致抗蚀剂层曝光,利用合适的显影液剂除去部分光致抗蚀剂,以形成第二光致抗蚀剂图形;在该第二光致抗蚀剂图形上注入N-离子,并去除剩余的图案化的光致抗蚀剂层,进而在第一与第二N+离子部52、54靠近第一多晶硅部42形成第一与第二N-离子部53、55。
步骤9、在栅极绝缘层60上形成第三光致抗蚀剂图形,并在第三该光致抗蚀剂图形内注入P+离子,并活化。
其具体实施方式可为在栅极绝缘层60上覆一层感光材料,通过灰阶掩膜或半灰阶掩膜照对该光致抗蚀剂层曝光,利用合适的显影液剂除去部分光致抗蚀剂,以形成第三光致抗蚀剂图形;在该第三光致抗蚀剂图形上注入P+离子,并去除剩余的图案化的光致抗蚀剂层,进而在第三N+离子部56远离第一多晶硅部42侧形成P+离子部57,并将植入的离子进行活化。
步骤10、在栅极绝缘层60上形成第一金属层70,并通过掩膜工艺形成栅极72。其具体工艺与上述工艺相似,在此不做赘述。
步骤11、在第一金属层70上形成第一绝缘层80,并氢化该第一绝缘层80,以形成氢化绝缘层80’。
步骤12、在第一绝缘层80上通过掩膜工艺形成第一沟道82,以露出第一、第二与第三N+离子部52、54、56及P+离子部57。
步骤13、在第一绝缘层80上形成第二金属层90,并通过掩膜工艺形成金属电极92,进而形成薄膜晶体管(TFT)与光伏电池。
所述第一N+离子部52、第二N+离子部54、第一N-离子部53、第二N-离子部55、第一多晶硅部42、栅极72及两个金属电极92共同形成一薄膜晶体管;所述第三N+离子部56、P+离子部57及两个金属电极92共同形成一光伏电池。
步骤14、在第二金属层90上形成第二绝缘层100,并该第二绝缘层100上通过掩膜工艺形成第二沟道102。
步骤15、在第二绝缘层100上形成平坦化层110,并通过掩膜工艺形成第三沟道112。在本实施例中,所述平坦化层110为有机层。
步骤16、在该平坦化层110上形成透明导电层120,并通过掩膜工艺在该透明导电层120上形成预定图案。所述透明电极层120为氧化铟锡(ITO)层,其用于将薄膜晶体管的漏极的电流导出。
步骤17、对该透明导电层120进行退火处理,以提高电学性能。
其中,所述缓冲层30、非晶硅层40、第一与第二绝缘层80、100均通过化学气相沉积形成于基板上;所述第一、第二金属层70、90通过溅射工艺形成。
综上所述,本发明具有嵌入式光伏电池的阵列基板的制作方法,在形成阵列基板的同时形成光伏电池,其以简单的制程将光伏电池嵌入阵列基板中,进而利用背光源发出的光线为液晶显示面板元件或配件供电,充分利用背光源所发出的光能,节省了对外部电能的消耗。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (8)

1.一种具有嵌入式光伏电池的阵列基板的制作方法,其特征在于,包括以下步骤:
步骤1、提供基板;
步骤2、在基板上形成缓冲层;
步骤3、在缓冲层上形成非晶硅层;
步骤4、激光退火,将非晶硅层转变为多晶硅层;
步骤5、通过掩膜工艺在多晶硅层上形成预定图形;
步骤6、在多晶硅层上形成第一光致抗蚀剂图形,并在该第一光致抗蚀剂图形内注入N+离子;
步骤7、在多晶硅层上形成栅极绝缘层;
步骤8、在栅极绝缘层上形成第二光致抗蚀剂图形,并在第二该光致抗蚀剂图形内注入N-离子;
步骤9、在栅极绝缘层上形成第三光致抗蚀剂图形,并在第三该光致抗蚀剂图形内注入P+离子,并活化;
步骤10、在栅极绝缘层上形成第一金属层,并通过掩膜工艺形成栅极;
步骤11、在第一金属层上形成第一绝缘层,并氢化该第一绝缘层,以形成氢化绝缘层;
步骤12、在第一绝缘层上通过掩膜工艺形成第一沟道;
步骤13、在第一绝缘层上形成第二金属层,并通过掩膜工艺形成金属电极,进而形成薄膜晶体管与光伏电池;
还包括:
步骤14、在第二金属层上形成第二绝缘层,并该第二绝缘层上通过掩膜工艺形成第二沟道;
步骤15、在第二绝缘层上形成平坦化层,并通过掩膜工艺形成第三沟道;
步骤16、在该平坦化层上形成透明导电层,并通过掩膜工艺在该透明导电层上形成预定图案;
步骤17、对该透明导电层进行退火处理。
2.如权利要求1所述的具有嵌入式光伏电池的阵列基板的制作方法,其特征在于,所述基板为玻璃基板。
3.如权利要求1所述的具有嵌入式光伏电池的阵列基板的制作方法,其特征在于,所述缓冲层、非晶硅层、第一与第二绝缘层均通过化学气相沉积形成于基板上。
4.如权利要求1所述的具有嵌入式光伏电池的阵列基板的制作方法,其特征在于,所述第一、第二金属层通过溅射工艺形成。
5.如权利要求1所述的具有嵌入式光伏电池的阵列基板的制作方法,其特征在于,所述掩膜工艺包括曝光制程、显影制程及蚀刻制程。
6.如权利要求1所述的具有嵌入式光伏电池的阵列基板的制作方法,其特征在于,所述N+离子、N-离子及P+离子均位于所述多晶硅层。
7.如权利要求1所述的具有嵌入式光伏电池的阵列基板的制作方法,其特征在于,所述透明导电层为氧化铟锡层。
8.如权利要求1所述的具有嵌入式光伏电池的阵列基板的制作方法,其特征在于,所述平坦化层为有机层。
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CN104157656A (zh) * 2014-07-29 2014-11-19 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
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JP2008145447A (ja) * 2005-03-29 2008-06-26 Sharp Corp アクティブマトリクス基板、表示装置、および電子機器
US20070102035A1 (en) * 2005-10-31 2007-05-10 Xiai (Charles) Yang Method and Structure for Integrated Solar Cell LCD Panel
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CN101685218B (zh) * 2008-09-24 2012-04-04 北京京东方光电科技有限公司 液晶显示面板阵列基板及其制造方法
CN101813849B (zh) * 2009-02-19 2013-03-13 北京京东方光电科技有限公司 彩膜基板及其制造方法和液晶面板
CN101614896B (zh) * 2009-06-22 2011-08-31 友达光电股份有限公司 薄膜晶体管数组基板、显示面板、液晶显示装置及其制作方法
CN101995691B (zh) * 2009-08-20 2013-05-15 上海天马微电子有限公司 液晶显示装置
CN102253547B (zh) * 2010-05-21 2015-03-11 北京京东方光电科技有限公司 阵列基板及其制造方法和液晶显示器
CN102445804A (zh) * 2010-09-30 2012-05-09 联胜(中国)科技有限公司 显示装置
CN102569192B (zh) * 2012-03-06 2014-04-09 深圳市华星光电技术有限公司 半穿半反液晶显示器的阵列基板制造方法
CN102569191B (zh) * 2012-03-06 2013-09-04 深圳市华星光电技术有限公司 半穿半反液晶显示器的阵列基板制造方法
CN102543866B (zh) * 2012-03-06 2013-08-28 深圳市华星光电技术有限公司 穿透式液晶显示器的阵列基板制造方法

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