CN102737580A - Active matrix organic light emitting diode (AMOLED) display panel - Google Patents
Active matrix organic light emitting diode (AMOLED) display panel Download PDFInfo
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- CN102737580A CN102737580A CN2012102209417A CN201210220941A CN102737580A CN 102737580 A CN102737580 A CN 102737580A CN 2012102209417 A CN2012102209417 A CN 2012102209417A CN 201210220941 A CN201210220941 A CN 201210220941A CN 102737580 A CN102737580 A CN 102737580A
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Abstract
The invention discloses an active matrix organic light emitting diode (AMOLED) display panel, which comprises a pixel matrix, a row driver, a line driver, row address wires and line address wires. The pixel matrix consists of pixels which are arranged at equal intervals; the row driver provides row gating signals for the pixels in the pixel matrix through the row address wires; the line driver provides data signals for the pixels in the pixel matrix through the line address wires; each row address wire is simultaneously communicated with grid electrodes of first transistors of the pixels in the two rows adjacent to the row address wire; each line address wire comprises a first line of address wires and a second line of address wires, and one end of the first transistor of one of the pixels in the two adjacent rows is communicated with the first line of address wires; and one end of the first transistor of another one of pixels in the two adjacent rows is communicated with the second line of address wires.
Description
Technical field
The present invention relates to the electroluminescent device technical field, be specifically related to a kind of AMOLED display panel.
Background technology
As everyone knows; OLED (Organic Light Emitting Diode) is that current drives is luminous; And AMOLED (Active Matrix Organic Light Emitting Diode) is the active matrix organic light-emitting diode (AMOLED) panel, and the AMOLED display panel has characteristics such as reaction velocity is very fast, contrast is higher, the visual angle is wider.
Shown in Figure 1 is the frame diagram of existing AMOLED display panel, as can be seen from the figure, and pixel P (M; N) according to uniformly-spaced rearranging picture element matrix, number for each pixel according to residing line number of each pixel and columns, like pixel P (1; 1) pixel of representing first row first to be listed as, pixel P (2,1) represents the pixel of second row, first row; And the like, pixel P (M, the pixel of N) representing the capable N of M to be listed as.As shown in the figure, (M N) is positioned at the position of M row address line and N column address conductor point of crossing to each pixel P.For the ease of describing, (M, N), in fact, (M N) has the capable and hundreds of row of hundreds of to pixel P, adopts 4M to represent the row address line that M is capable accordingly, adopts 5N to represent the column address conductor of N row only to have listed a part of pixel P among the figure.
Fig. 2 has provided pixel P (M; N) internal circuit, and each pixel P (M, N) internal circuit comprises OLED device 11; The negative pole of said OLED device 11 is connected to second source line 7, and the positive pole of said OLED device 11 is communicated with first power lead 6 through the first transistor 12; Transistor seconds 14; Its grid is connected with row address line 4; Two ends connect the grid of column address conductor 5 and the first transistor 12 respectively in addition; According to the type selecting connected mode of said transistor seconds 14, guarantee that said transistor seconds 14 can conducting make that the data-signal of said column address conductor 5 can be through inputing to the grid of said the first transistor 12 behind the said transistor seconds 14 when row address line 4 provides gating signal; Data keep electric capacity 13; One end is connected to first power lead 6; The other end is connected to the grid of the first transistor 12, and the connected mode of said the first transistor 12 guarantees when said column address conductor 5 data signals transmitted input to the grid of said the first transistor 12 according to the type decided of said the first transistor 12; Said the first transistor 12 conductings, said first power lead 6 can add on the said OLED luminescent device 11.Wherein, said the first transistor 12 can be the thin film transistor (TFT) (PTFT) of P type with transistor seconds 14, also can be the thin film transistor (TFT) (NTFT) of N type according to the connection of side circuit, the transistor of the other types that also can be processed by polysilicon.
Shown in Figure 3 is the circuit diagram of line driver 2, as shown in the figure, and this line driver 2 comprises M d type flip flop, although Fig. 3 has only shown four d type flip flops, in fact, has how many row how many d type flip flops are just arranged in line driver 2 inside.As shown in Figure 3, the input end D of delegation's address displacement signal wire 22 to trigger 23 provides the gated sweep signal through shift signal line 22, one-row pixels is all arranged by gating in each time period.The output terminal Q of d type flip flop 23 is connected to the input end D of row address line 41 and d type flip flop 24; The output terminal Q of d type flip flop 24 is connected to the input end D of row address line 42 and d type flip flop 25; The output terminal Q of d type flip flop 25 is connected to the input end D of row address line 43 and d type flip flop 26; The output terminal Q of d type flip flop 26 is connected to row address line 44.D type flip flop 23,24,25 and 26 input end of clock are connected with clock signal 21.
Fig. 4 has shown the block diagram of row driver 3, and row driver 3 comprises a data register 31, and this video data 33 of vision signal 33 and transmission that is used to store input is to digital to analog converter 32, and the output terminal of digital to analog converter 32 is connected to column address conductor 5.
In conjunction with Fig. 1 to Fig. 4, the principle of work of AMOLED display panel is following:
In write cycle: line driver 2 is during through the capable pixel of row address line 4M gating M, and row address line 4M provides gating signal for the grid of the first transistor 14 in the capable image element circuit of M; Row driver 3; Be applied to the grid of the first transistor 12 through transistor seconds 14 through column address conductor 5N; Data-signal on the column address conductor 5 flows through OLED device 11 through the electric current of the corresponding size of the first transistor 12 controls, and control OLED device 11 sends the light of corresponding gray scale.
In the display cycle: the voltage of the first transistor 12 grids is remained to next write cycle by liquid crystal capacitance 13, and therefore the luminous gray scale of OLED device 11 also remains unchanged always during this period.
Fig. 5 has provided the sequential chart of the work one-period of image element circuit.As can be seen from Figure 2 because the first row pixel distance line driver 2 is nearest, so the gating signal on the row address line 4 to arrive for the first row pixel time spent the shortest; N row pixel distance line driver 2 farthest, it is the longest that the gating signal on the row address line arrives the N row pixel time spent; Therefore the gating signal on the row address line 4 is from pixel P (M, 1) to pixel P (M, the delay time with d1 N).On the other hand, the pixel distance row driver 3 of first row is nearest, and the capable pixel distance row driver 3 of M farthest; Therefore the data-signal of column address conductor 5 has the delay time of d2 to the capable pixel of M from the first row pixel.If the cycle of clock signal 21 is frame period H, thus the pixel P of AMOLED display panel (M, N) time for writing signal is: t=H-d1-d2.
For the AMOLED display panel, the time of M row address line and the whole gatings of N column address conductor is the cycle V of a picture frame, and obviously, the time span in a frame period is: V=M*H.And because the length of the picture frame cycle V of AMOLED display panel fixes, therefore along with the line number of AMOLED display panel and the continuous increase of columns, i.e. the continuous increase of M value, the contraction in length of frame period H.Behind the contraction in length of frame period H; Can cause the AMOLED display panel each picture element signal write cycle t=H-d1-d2 shortening; Therefore along with the increase of screen size and resolution; The ON time of each row pixel will shorten accordingly, for each pixel, be difficult to obtain sufficiently long write cycle of t, just can reduce the sharpness of AMOLED display panel greatly.
Summary of the invention
Technical matters to be solved by this invention is in the prior art because the increase of screen size and resolution, and causing pixel deficiency of time write cycle of AMOLED display panel to influence the sharpness of AMOLED display panel and then provide a kind of can increase the large tracts of land display panel pixel AMOLED display panel of write cycle.
For solving the problems of the technologies described above, the present invention provides a kind of AMOLED display panel, comprising: picture element matrix, comprise that some M of being in are capable, the pixel P of N row (M, N), wherein M is the natural number greater than 1, N is the natural number greater than 1;
Processor clock signal, receiving cycle are the clock signal of system of H, and the output cycle is the clock signal of 2H;
Line driver is worked under the clock signal sequential condition of said processor clock signal output, and it is that (M N) provides capable gating signal for said pixel P in the said picture element matrix through row address line;
Row driver is that (M N) provides data-signal for said pixel P in the said picture element matrix through column address conductor;
Said row address line through parallel connection the first sub-row address line and the second sub-row address line is respectively (2m-1) row pixel and the capable pixel of 2m provides gating signal;
Said column address conductor is that the pixel that n is listed as provides data-signal through the first sub-column address conductor and the second sub-column address conductor of parallel connection;
The said first sub-column address conductor is that the pixel of (2m-1) row n row provides data-signal, and the said second sub-column address conductor is that the pixel of (2m) row n row provides data-signal.
Said line driver is made up of m d type flip flop of series connection, and the clock signal input terminal of each said d type flip flop is connected with the signal output part of said processor clock signal;
The input end D termination of each said d type flip flop is received the output signal of the output terminal Q end of a last d type flip flop; And the output terminal Q of each said d type flip flop end is communicated with said row address line respectively.
Said processor clock signal adopts the frequency division d type flip flop; The signal input part D termination of said frequency division d type flip flop is received clock signal of system, when the signal feedback of its signal output part Q end output is held to its signal input part D with said line driver in the clock signal input terminal of all d type flip flops be connected.
Said row driver comprises registers group and digital to analog converter group;
Said registers group comprises first register and second register; Said digital to analog converter group comprises first digital to analog converter and second digital to analog converter;
First vision signal that said first register receives and storage is imported is also carried out digital-to-analog conversion with said first video signal transmission to said first digital to analog converter and is handled, and the simulating signal after said first digital to analog converter will be changed exports the said first sub-column address conductor to;
Second vision signal that said second register receives and storage is imported is also carried out digital-to-analog conversion with said second video signal transmission to said second digital to analog converter and is handled, and the simulating signal after said second digital to analog converter will be changed exports the said second sub-column address conductor to.
Technique scheme of the present invention compared with prior art has following beneficial effect:
(1) among the present invention, each row address line comprises the first sub-row address line and the second sub-row address line, the capable pixel of the first sub-row address line gating 2m-1, the capable pixel of the second sub-row address line gating 2m; Therefore when line driver be pixel in picture element matrix when gating signal is provided through a certain row address line, can be that two capable pixels provide gating signal simultaneously; Simultaneously, each column address conductor comprises the first sub-column address conductor and the second sub-column address conductor among the present invention, and the first sub-column address conductor is that the pixel of the capable n row of 2m-1 provides data-signal, and the second sub-column address conductor is that the pixel of the capable n row of 2m provides data-signal.Therefore when two capable pixels by while during gating; The adjacent two capable pixels that can control respectively in the same row through the first sub-column address conductor and the second sub-column address conductor are respectively carried out luminous; And then realize each pixel is visited separately; And, guarantee the sharpness of display screen because two row pixels can be guaranteed the time long enough of the write cycle of each pixel simultaneously by gating.
(2) among the present invention; Clock signal is after processor clock signal is handled; The cycle of the clock signal of output expands to two times of clock signal of system cycle, the signal of processor clock signal output and the clock signal input terminal UNICOM of all d type flip flops in the line driver.Therefore each row address line is two row pixels when gating signal is provided simultaneously, and the cycle stretch-out of the obtainable gating signal of each row pixel is two times of original clock signal cycle, to guarantee to provide for each pixel the write cycle of abundance.
Description of drawings
The frame diagram of the AMOLED display panel that Fig. 1 provides for prior art;
Fig. 2 is the AMOLED display panel pixel circuit diagram of prior art;
The frame diagram of the AMOLED display panel line driver that Fig. 3 provides for prior art;
The frame diagram of the AMOLED display panel row driver that Fig. 4 provides for prior art;
The AMOLED display panel that Fig. 5 provides for prior art writes the sequential chart of the waveform of a pixel;
Fig. 6 is AMOLED display panel frame figure of the present invention;
Fig. 7 is the row driver frame figure of AMOLED display panel of the present invention;
Fig. 8 is the column driver frame figure of AMOLED display panel of the present invention;
Fig. 9 is the sequential chart of the waveform that writes a pixel of AMOLED display panel of the present invention;
Figure 10 is the capable pixel gating sequential chart of AMOLED display panel of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the present invention is further specified.
Present embodiment provides a kind of AMOLED display panel, and as shown in Figure 6, it comprises: a kind of AMOLED display panel; Comprise: picture element matrix, picture element matrix comprises that some M of being in are capable, the pixel P (M of N row; N), wherein M is the natural number greater than 1, and N is the natural number greater than 1; Processor clock signal 210, receiving cycle are the clock signal of system of H, and the output cycle is the clock signal of 2H; Line driver 2 is worked under the clock signal sequential condition of said processor clock signal 210 outputs, and (m is a natural number, and m≤M/2) is that (M N) provides capable gating signal for said pixel P in the said picture element matrix through row address line (4m) for it; Row driver 3, (n is a natural number, and n≤N/2) is that (M N) provides data-signal for said pixel P in the said picture element matrix through column address conductor 5n; Said row address line 4m through parallel connection the first sub-row address line 4ma and the second sub-row address line 4mb is respectively the capable pixel of 2m-1 and the capable pixel of 2m provides gating signal; Said column address conductor 5n is that the pixel that n is listed as provides data-signal through the first sub-column address conductor 5na and the second sub-column address conductor 5nb of parallel connection; The said first sub-column address conductor 5na is that the pixel of the capable n row of 2m-1 provides data-signal, and the said second sub-column address conductor 5nb is that the pixel of the capable n row of 2m provides data-signal.
Can see that from Fig. 6 first power lead 6 is connected to all pixels, and the electric current through OLED device 11 is provided; Second source line 7 is connected to all pixels, and the leakage current through OLED11 is provided.For simplicity, several pixels 1 have only been identified in the drawings.In fact, have the capable and hundreds of row of hundreds of.
Fig. 7 is the block diagram according to the horizontal drive circuit 2 of present embodiment demonstration, for the pixel of gating first row and second row, through driving row address line 41, the first sub-row address line 41a and the second sub-row address line 41b;
The block diagram of the row driver 3 that provides for present embodiment shown in Figure 8.Row driver 3 comprises two data register 31a, 31b, and at two line time stored inputting video data 33a, 33b, transmitting and storing video data 33a, 33b is to digital-to-analogue converter 32a, 32b.The output of digital-to- analogue converter 32a and 32b is connected to column address conductor 51a, 51b, and 52a, 52b ..., 5ma, 5mb (m is the half the of line number M here).
Fig. 9 is the signal waveform sequential chart according to the write cycle of present embodiment demonstration.(M, time-delay N) is d1 to a gating signal on the row address line from a pixel P (M, 1) to a pixel P.Because two row are gatings simultaneously, such one write cycle t1=2*H-d1.On the other hand, data- signal 51a, 51b, 52a, 52b, 53a, the 53b time-delay from the first row pixel to M row pixel is d2.Therefore last t2=2*H-d1-d2 write cycle has increased the length of a clock period H, so has had sufficiently long write cycle with respect to prior art.
Along with the bigger of display screen and high more resolution, because video frame period diminishes, the frame period also becomes more and more littler.But, still keep sufficient pixel write cycle according to AMOLED display of the present invention.Only shown two row gating simultaneously in this example.In fact, be easy to expand to, say more easy expansion for AMLCD especially more than 2 row.
The foregoing description is merely preferred implementation of the present invention; But embodiment of the present invention is not restricted to the described embodiments; Other are any not to deviate from change, modification, combination, the simplification of being done under spirit of the present invention and the principle; All should be the substitute mode of equivalence, be included within protection scope of the present invention.Though the present invention is to disclose as above than preferable embodiment; Yet it is not in order to limit the present invention; Anyly be familiar with this technological personage, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching; Therefore, protection scope of the present invention is as the criterion when the claim with application defines.
Claims (4)
1. AMOLED display panel comprises:
Picture element matrix, comprise that some M of being in are capable, the pixel P of N row (M, N), wherein M is the natural number greater than 1, N is the natural number greater than 1;
Processor clock signal (210), receiving cycle are the clock signal of system of H, and the output cycle is the clock signal of 2H;
Line driver (2); Under the clock signal sequential condition of said processor clock signal (210) output, work; (m is a natural number, and m≤M/2) is that (M N) provides capable gating signal for said pixel P in the said picture element matrix through row address line (4m) for it;
Row driver (3), (n is a natural number, and n≤N/2) is that (M N) provides data-signal for said pixel P in the said picture element matrix through column address conductor (5n);
It is characterized in that:
Said row address line (4m) is respectively (2m-1) row pixel through the first parallelly connected sub-row address line (4ma) and the second sub-row address line (4mb) and the capable pixel of 2m provides gating signal;
Said column address conductor (5n) is that the pixel that n is listed as provides data-signal through the first sub-column address conductor (5na) and the second sub-column address conductor (5nb) of parallel connection;
The said first sub-column address conductor (5na) is that the pixel of (2m-1) row n row provides data-signal, and the said second sub-column address conductor (5nb) is that the pixel of (2m) row n row provides data-signal.
2. AMOLED display panel according to claim 1 is characterized in that:
Said line driver (2) is made up of m d type flip flop of series connection, and the clock signal input terminal of each said d type flip flop is connected with the signal output part of said processor clock signal (210);
The input end D termination of each said d type flip flop is received the output signal of the output terminal Q end of a last d type flip flop; And the output terminal Q of each said d type flip flop end is communicated with said row address line (4m) respectively.
3. AMOLED display panel according to claim 2 is characterized in that:
Said processor clock signal (210) adopts the frequency division d type flip flop; The signal input part D termination of said frequency division d type flip flop is received clock signal of system, and the clock signal input terminal with interior all d type flip flops of said line driver (2) when the signal feedback of its signal output part Q end output hold to its signal input part D is connected.
4. according to the arbitrary described AMOLED display panel of claim 1-3, it is characterized in that:
Said row driver (3) comprises registers group (31) and digital to analog converter group (32);
Said registers group comprises first register (31a) and second register (31b); Said digital to analog converter group (32) comprises first digital to analog converter (32a) and second digital to analog converter (32b);
First vision signal (33a) that said first register (31a) receives and storage is imported also transfers to said first digital to analog converter (32a) with said first vision signal (33a) and carries out the digital-to-analog conversion processing, and the simulating signal after said first digital to analog converter (32a) will be changed exports the said first sub-column address conductor (5na) to;
Second vision signal (33b) that said second register (31b) receives and storage is imported also transfers to said second digital to analog converter (32b) with said second vision signal (33b) and carries out the digital-to-analog conversion processing, and the simulating signal after said second digital to analog converter (32b) will be changed exports the said second sub-column address conductor (5nb) to.
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| CN113035128A (en) * | 2019-08-02 | 2021-06-25 | 苹果公司 | Display with gate driver circuitry including shared register circuitry |
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| CN102737580B (en) | 2015-06-17 |
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Effective date of registration: 20201230 Address after: No.146 Tianying Road, high tech Zone, Chengdu, Sichuan Province Patentee after: Chengdu CHENXIAN photoelectric Co.,Ltd. Address before: No. 188, CHENFENG Road, Kunshan high tech Zone, Kunshan City, Suzhou City, Jiangsu Province Patentee before: Kunshan New Flat Panel Display Technology Center Co.,Ltd. |