CN101853636A - Display panel - Google Patents
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- CN101853636A CN101853636A CN200910129263A CN200910129263A CN101853636A CN 101853636 A CN101853636 A CN 101853636A CN 200910129263 A CN200910129263 A CN 200910129263A CN 200910129263 A CN200910129263 A CN 200910129263A CN 101853636 A CN101853636 A CN 101853636A
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Abstract
The invention relates to a display panel, which is provided with a plurality of source data lines and at least one first grid scanning line, comprises at least one first display column and at least one second display column. The first display column comprises a plurality of first pixel units, each first pixel unit is provided with a first drive transistor, the grids of the first drive transistors are connected with the first grid scanning line together, and the first sources/drains of the first drive transistors are respectively and sequentially connected with the source data lines in odd rows. The second display column comprises a plurality of second pixel units, and each second pixel unit is provided with a second drive transistor. The grids of the second drive transistors are connected with the first grid scanning line together, and the first sources/drains of the second drive transistors are respectively and sequentially connected with the source data lines in even rows.
Description
Technical field
The present invention relates to a kind of display technique, particularly a kind of display panel.
Background technology
Along with the progress of electronic technology, electronic product become in the people life indispensable important tool.With the display panel is example, and the user no longer can be satisfied with simple display panel in the past.The thing followed, high-quality, low price and the display panel with province's electrical efficiency are only the main flow of being pursued in now the electronic product.
Below please refer to Fig. 1, Fig. 1 is the synoptic diagram of existing display panels 100.Display panels 100 comprises that clock generator 110, source electrode driver 120, gate drivers 130 and a plurality of pixel cell 141 form.Pixel cell 141 is by being centered on many source electrode data line SL and gate pole sweep trace GL that source electrode driver 120 is connected with gate driver 130.In above-mentioned existing display panels 100, because picture frame rate (frame rate) is almost fixed, when scanning, must calculate the most-likely time of scanning at each grid according to the grid quantity of display panels 100.In case when the quantity of the controlling grid scan line of display panel was very big, what the most-likely time of scanning at each grid will be relative reduced.Thus, pixel data after source electrode data line SL is sent to pixel cell 141, can be used for storing pixel data duration of charging not enough situation just may take place.
Therefore, situation corresponding to above-mentioned duration of charging deficiency, prior art proposes many driving voltages that for example promote to pixel cell 141 (the over driving that overdrives, OD) mode, but, this mode of overdriving not only needs to provide outside the higher voltage source, also can cause redundant power consumption, can not satisfy cost and two energy-conservation requirements.
Summary of the invention
The present invention proposes a kind of display panel, can effectively increase the duration of charging of each gated sweep.
The present invention proposes a kind of display panel, and wherein this display panel has many source electrode data lines and at least one first grid sweep trace.This kind display panel comprises at least one first display column and at least one second display column.First display column comprises a plurality of first pixel cells, and each first pixel cell has first driving transistors.The grid of first driving transistors is connected to the first grid sweep trace jointly, and first source/drain electrode of first driving transistors connects the source electrode data line of odd-numbered line respectively in regular turn.In addition, second display column comprises a plurality of second pixel cells, and each second pixel cell has second driving transistors.The grid of second driving transistors connects the first grid sweep trace jointly, and first source/drain electrode of second driving transistors connects the source electrode data line of even number line respectively in regular turn.
In an embodiment of the present invention, the quantity of above-mentioned source electrode data line equals the quantity summation of first pixel cell and second pixel cell.
In an embodiment of the present invention, above-mentioned each first pixel cell more comprises first liquid crystal capacitance.First liquid crystal capacitance connects second source/drain electrode of first driving transistors.
In an embodiment of the present invention, above-mentioned each second pixel cell more comprises second liquid crystal capacitance.Second liquid crystal capacitance connects second source/drain electrode of second driving transistors.
In an embodiment of the present invention, above-mentioned first driving transistors and second driving transistors are thin film transistor (TFT).
In an embodiment of the present invention, above-mentioned display panel wherein more comprises at least one the 3rd display column and at least one the 4th display column.Wherein, the 3rd display column comprises a plurality of the 3rd pixel cells, each the 3rd pixel cell has the 3rd driving transistors, and the grid of the 3rd driving transistors connects the second grid sweep trace jointly, and first source/drain electrode of the 3rd driving transistors connects the source electrode data line of even number line respectively in regular turn.The 4th display column comprises a plurality of the 4th pixel cells, each the 4th pixel cell has the moving transistor of 4 wheel driven, the moving transistorized grid of 4 wheel driven connects the second grid sweep trace jointly, and the moving transistorized first source/drain electrode of 4 wheel driven connects the source electrode data line of odd-numbered line respectively in regular turn.And wherein the first, second, third and the 4th display column is configured on the display panel in regular turn.
In an embodiment of the present invention, the moving transistor of above-mentioned the 3rd driving transistors and 4 wheel driven is a thin film transistor (TFT)
In an embodiment of the present invention, above-mentioned first pixel cell more comprises the 3rd liquid crystal capacitance of the second source/drain electrode that connects the 3rd driving transistors.
In an embodiment of the present invention, above-mentioned the 4th pixel cell more comprises the 4th liquid crystal capacitance that connects the moving transistorized second source/drain electrode of 4 wheel driven.
In an embodiment of the present invention, above-mentioned display panel more comprises at least one source electrode driver, connects above-mentioned source electrode data line and transmits a plurality of pixel datas through the source electrode data line.
In an embodiment of the present invention, above-mentioned display panel wherein more comprises at least one gate drivers, in order to connect the first grid sweep trace and through the first grid sweep trace first, second display column to be carried out scanning motion.
Based on above-mentioned, the present invention utilizes a controlling grid scan line to be connected to two adjacent display columns of display panel.Make the quantity of controlling grid scan line effectively be kept to 1/2nd, and make that the duration of charging of every controlling grid scan line effectively increases when display panel is scanned, and then promote the display quality of display panel.
For the above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Fig. 1 is the synoptic diagram of the display panels 100 of prior art.
Fig. 2 is the synoptic diagram of the display panel 200 of one embodiment of the invention.
Fig. 3 is the action waveforms synoptic diagram of display panel 200.
Fig. 4 is the synoptic diagram of one embodiment of the invention display panel 400.
Critical piece label declaration in the accompanying drawing:
100,200,400: Display Panel
110,210,410: clock generator
120,220,420: source electrode driver
130,230,430: gate drivers
240,250,260,270,440,450,460,470: display column
141,2411-241M, 2511-21M: pixel cell
SL, SL1-SLN: source electrode data line
GL, GL1-GL3: controlling grid scan line
T1: driving transistors
C1, C2: electric capacity
LD: latch-up signal
D1, D2, Data: data
Embodiment
Below please be earlier referring to Fig. 2, Fig. 2 is the synoptic diagram of one embodiment of the invention display panel 200.Display panel 200 comprises clock generator 210, source electrode driver 220 and gate driver 230.In addition, source electrode driver 220 connects many source electrode data line SL1-SLN, and gate drivers 230 connects many controlling grid scan line GL1, GL2, GL3.Source electrode data line SL1-SLN and controlling grid scan line GL1, GL2, GL3 intersect layout mutually in the mode of checkerboard, and cook up display column 240,250 etc. by this.
Comprise a plurality of pixel cell 2411-241M in the display column 240, pixel cell 2411-241M wherein respectively has a driving transistors T1, and wherein above-mentioned N just equals the twice of M.As known to those skilled in the art, driving transistors T1 has grid, first source/drain electrode and second source/drain electrode.And in the present embodiment, be example with the driving transistors T1 in the pixel cell 2411, the grid of driving transistors T1 is connected to controlling grid scan line GL1, and its first source/drain electrode is connected to source electrode data line SL1, and its second source/drain electrode meets liquid crystal capacitance C1.
Then comprise a plurality of pixel cell 2511-21M in the display column 250, pixel cell 2511-21M wherein equally respectively has a driving transistors T2.In the present embodiment, be example with the driving transistors T2 in the pixel cell 2511, the grid of driving transistors T2 is connected to controlling grid scan line GL1, and its first source/drain electrode is connected to source electrode data line SL2, and its second source/drain electrode meets liquid crystal capacitance C2.
That is to say that first source/drain electrode of the driving transistors of display column 240 all is the source electrode data line that is connected to odd number, and first source/drain electrode of the driving transistors of display column 250 all is the source electrode data line that is connected to even number.
In addition, driving transistors T1, the T2 among above-mentioned pixel cell 2411-241M, the 2511-21M is thin film transistor (TFT), and the quantity of above-mentioned controlling grid scan line GL1-GL3 is not restricted to three yet.In fact, the quantity of controlling grid scan line is related with the size of display panel, and at this, the minimum number of controlling grid scan line can be one.
At this, please pay special attention to, in the display panel 200 in the present embodiment, the pixel cell 2411-241M of different two display columns 240,250 and the grid of the driving transistors among the 2511-21M all are connected to controlling grid scan line GL1 jointly.Thus, the display panel 200 of the embodiment of the invention just can more existing display panel (for example Fig. 1 shown in) removes the controlling grid scan line of half less.Relative, just when display panel 200 carries out gated sweep, and the assigned time of each grid just can double, and then the duration of charging of lifting pixel cell.
With reference to Fig. 2 and Fig. 3, Fig. 3 is the action waveforms synoptic diagram of display panel 200 when as follows.Wherein, clock generator 210 is orderly sent to pixel data Data in the source electrode driver 220.Because the pixel cell in the display column 240,250 can be transmitted in regular turn, so clock generator 210 is being used at data presented D1 on the display column 240 and being used for that data presented D2 reaches source electrode driver 220 according to sequencing on display column 250, and after finishing, the transmission of above-mentioned data D1, D2 enables latch-up signal LD.
220 of source electrode drivers enable according to this latch-up signal LD's, data D1, D2 breech lock are lived, and simultaneously data D1, D2 are sent out in the mode of voltage through source electrode data line SL1-SLN.Simultaneously data D1, D2 are sent out back (or simultaneously) in the mode of voltage at source electrode data line SL1-SLN, 210 of clock generators inform that gate drivers 230 enables controlling grid scan line GL1, display column 240 and display column 250 included pixel cell 2411-241N, 2511-251N are scanned simultaneously and charging.
GL1 enables at controlling grid scan line, and display column 240 and display column 250 and charging the time, clock generator 210 continues to transmit data D3, D4 to source electrode driver 220.Clock generator 210 is used on the display column 260 data presented D3 and is used for after the transmission of data presented D4 on the display column 270 having finished, then again enable latch-up signal LD.Identical, 220 of source electrode drivers again according to the enabling of this latch-up signal LD, data D3, D4 breech lock are lived, and simultaneously data D3, D4 are sent out in the mode of voltage through source electrode data line SL1-SLN.210 of clock generators inform that gate drivers 230 enables controlling grid scan line GL2, and display column 260 and display column 270 are charged.
Please pay special attention to, because having finished the pixel data transmission of two display columns, clock generator 210 just can enable latch-up signal LD one time, therefore, originally latch-up signal LD must transmit with regard to transition frequency halving once at the pixel data of finishing a display column, can effectively reduce the power of clock generator 210 and source electrode driver 220 required consumption like this, and can reduce circuit inner noise because of the tailing off of signal transition.
What is particularly worth mentioning is that, above-mentioned so-called source electrode driver 220 through source electrode data line SL1-SLN simultaneously with data D1, D2 or D3, D4 with the method that the mode of voltage transmits, be that data D1, D2 or D3, the D4 with digital format changes (for example mode of gamma voltage (gamma voltage) conversion) and produce aanalogvoltage to transmit.
Below referring again to Fig. 4, Fig. 4 is the synoptic diagram of the display panel 400 of one embodiment of the invention.Display panel 400 comprises clock generator 410, source electrode driver 420 and gate driver 430.Source electrode driver 420 connects many source electrode data line SL1-SLN, and gate drivers 430 connects many controlling grid scan line GL1, GL2, GL3.Source electrode data line SL1-SLN and controlling grid scan line GL1, GL2, GL3 intersect layout mutually in the mode of checkerboard, and cook up display column 460,470 etc. by this.
When as follows with reference to Fig. 2 and Fig. 4, please pay special attention at this, display panel 400 is with the difference of display panel 200 maximums of a last embodiment: display column 440,450 wherein is identical with the connected mode of driving transistors among the display column 240-270 and source electrode data line SL1-SLN, and the connected mode of driving transistors among display column 460,470 and the display column 240-270 and source electrode data line SL1-SLN is inequality.Wherein first source/drain electrode of the driving transistors in the pixel cell 461 in the display column 460 is connected to source electrode data line SL2 (the source electrode data line of even number), and first source/drain electrode of the driving transistors in the pixel cell 471 in the display column 470 is connected to source electrode data line SL1 (the source electrode data line of odd number).
At this, can only provide the pixel data voltage of a polarity owing to same source electrode data line.Therefore, the change of the mode that connects between the different pixel cell of display panel 200 and display panel 400 and source electrode data line SL1-SLN can make display panel produce the effect (counter-rotating of this indication then be well known to those skilled in the art as a counter-rotating (ot inversion), row counter-rotating (column inversion) or row counter-rotatings (row inversion) etc.) of different counter-rotatings (inversion).Certainly, also can release how different variations in conjunction with Fig. 2 and Fig. 4.For instance, pixel cell 2411 can keep connecing source electrode data line SL1 among Fig. 2, pixel cell 2412 then changes into and meets source electrode data line SL4, and corresponding pixel cell 2511 keeps meeting source electrode data line SL2, and pixel cell 2512 then changes into and meets source electrode data line SL3.
In sum, utilization of the present invention is carried out the mode of gated sweep simultaneously at adjacent different display columns, effectively reduces the number of the controlling grid scan line of display panel.Therefore, carry out the corresponding increase of time of gated sweep each time, effectively promote the demonstration usefulness of display panel.And the switching frequency of the relevant circuit signal (for example latch-up signal LD) of corresponding gated sweep number of times also is minimized, and effectively suppresses generating noise and effectively reduces consumed power.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit and scope of technical solution of the present invention.
Claims (11)
1. a display panel has many source electrode data lines and at least one first grid sweep trace, comprising:
At least one first display column, this first display column comprises:
A plurality of first pixel cells, respectively this first pixel cell has one first driving transistors, the grid of described first driving transistors connects described first grid sweep trace jointly, and first source/drain electrode of described first driving transistors connects the described source electrode data line of odd-numbered line respectively in regular turn; And
At least one second display column, this second display column comprises:
A plurality of second pixel cells, respectively this second pixel cell has one second driving transistors, the grid of described second driving transistors connects described first grid sweep trace jointly, and first source/drain electrode of described second driving transistors connects those source electrode data lines of even number line respectively in regular turn.
2. display panel according to claim 1 is characterized in that, the quantity of wherein said source electrode data line equals the quantity summation of described first pixel cell and described second pixel cell.
3. display panel according to claim 1, wherein each described first pixel cell more comprises: one first liquid crystal capacitance connects second source/drain electrode of this first driving transistors.
4. display panel according to claim 1, wherein each described second pixel cell more comprises: one second liquid crystal capacitance connects second source/drain electrode of this second driving transistors.
5. display panel according to claim 1, wherein said first driving transistors and described second driving transistors are thin film transistor (TFT).
6. display panel according to claim 1 wherein more comprises:
At least one the 3rd display column, the 3rd display column comprises:
A plurality of the 3rd pixel cells, each described the 3rd pixel cell has one the 3rd driving transistors, the grid of described the 3rd driving transistors connects a second grid sweep trace jointly, and first source/drain electrode of described the 3rd driving transistors connects those source electrode data lines of even number line respectively in regular turn; And
At least one the 4th display column, the 4th display column comprises:
A plurality of the 4th pixel cells, each described the 4th pixel cell has the moving transistor of a 4 wheel driven, the moving transistorized grid of described 4 wheel driven connects this second grid sweep trace jointly, and the moving transistorized first source/drain electrode of described 4 wheel driven connects those source electrode data lines of odd-numbered line respectively in regular turn;
Wherein this first, second, third and the 4th display column is configured on this display panel in regular turn.
7. display panel according to claim 6, the moving transistor of wherein said the 3rd driving transistors and described 4 wheel driven is a thin film transistor (TFT).
8. display panel according to claim 6, wherein each described first pixel cell more comprises: one the 3rd liquid crystal capacitance connects second source/drain electrode of the 3rd driving transistors.
9. display panel according to claim 6, wherein each described the 4th pixel cell more comprises: one the 4th liquid crystal capacitance connects the moving transistorized second source/drain electrode of this 4 wheel driven.
10. display panel according to claim 1 wherein more comprises: at least one source electrode driver connects described source electrode data line and transmits a plurality of pixel datas through described source electrode data line.
11. display panel according to claim 1 wherein more comprises: at least one gate drivers connects described first grid sweep trace and through described first grid sweep trace described first, second display column is carried out scanning motion.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910129263A CN101853636A (en) | 2009-04-03 | 2009-04-03 | Display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910129263A CN101853636A (en) | 2009-04-03 | 2009-04-03 | Display panel |
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| CN101853636A true CN101853636A (en) | 2010-10-06 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646405A (en) * | 2012-05-17 | 2012-08-22 | 青岛海信电器股份有限公司 | Liquid crystal display refreshing method, liquid crystal display screen, display and television |
| CN102737580A (en) * | 2012-06-29 | 2012-10-17 | 昆山工研院新型平板显示技术中心有限公司 | Active matrix organic light emitting diode (AMOLED) display panel |
| TWI463469B (en) * | 2012-05-31 | 2014-12-01 | Himax Tech Ltd | Image display |
| CN107004392A (en) * | 2016-11-28 | 2017-08-01 | 上海明遨电子科技有限公司 | The distributed driving of display panel |
| CN107065366A (en) * | 2017-06-19 | 2017-08-18 | 深圳市华星光电技术有限公司 | Array base palte and its driving method |
| CN113035128A (en) * | 2019-08-02 | 2021-06-25 | 苹果公司 | Display with gate driver circuitry including shared register circuitry |
| CN115202113A (en) * | 2022-06-14 | 2022-10-18 | 惠科股份有限公司 | Array substrate and display panel |
-
2009
- 2009-04-03 CN CN200910129263A patent/CN101853636A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646405A (en) * | 2012-05-17 | 2012-08-22 | 青岛海信电器股份有限公司 | Liquid crystal display refreshing method, liquid crystal display screen, display and television |
| TWI463469B (en) * | 2012-05-31 | 2014-12-01 | Himax Tech Ltd | Image display |
| CN102737580A (en) * | 2012-06-29 | 2012-10-17 | 昆山工研院新型平板显示技术中心有限公司 | Active matrix organic light emitting diode (AMOLED) display panel |
| WO2018095437A1 (en) * | 2016-11-28 | 2018-05-31 | Viewtrix Technology Co., Ltd. | Distributive-driving of liquid crystal display (lcd) panel |
| WO2017036430A3 (en) * | 2016-11-28 | 2017-08-31 | Viewtrix Technology Co., Ltd | Distributive-driving of display panel |
| CN107004392A (en) * | 2016-11-28 | 2017-08-01 | 上海明遨电子科技有限公司 | The distributed driving of display panel |
| US10210800B2 (en) | 2016-11-28 | 2019-02-19 | Viewtrix Technology Co., Ltd. | Distributive-driving of display panel |
| US10304376B2 (en) | 2016-11-28 | 2019-05-28 | Beijing Yunyinggu Technology Co., Ltd. | Distributive-driving of display panel |
| CN107004392B (en) * | 2016-11-28 | 2019-11-05 | 上海云英谷科技有限公司 | The distributed driving of display panel |
| US10762829B2 (en) | 2016-11-28 | 2020-09-01 | Beijing Yunyinggu Technology Co., Ltd. | Distributive-driving of display panel |
| CN107065366A (en) * | 2017-06-19 | 2017-08-18 | 深圳市华星光电技术有限公司 | Array base palte and its driving method |
| CN113035128A (en) * | 2019-08-02 | 2021-06-25 | 苹果公司 | Display with gate driver circuitry including shared register circuitry |
| CN115202113A (en) * | 2022-06-14 | 2022-10-18 | 惠科股份有限公司 | Array substrate and display panel |
| CN115202113B (en) * | 2022-06-14 | 2023-10-24 | 惠科股份有限公司 | Array substrate and display panel |
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Application publication date: 20101006 |