CN101226290A - Display panel and display device using the same as well as drive method of control signal - Google Patents
Display panel and display device using the same as well as drive method of control signal Download PDFInfo
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Abstract
The invention relates to a display panel and a drive method of relative display device and control signal, wherein each data line of the display panel comprise two sub data lines alternatively coupled with the pixels on the line. When the data line is driven by column inversion, the invention can generate dot inversion picture or 2line (2V1H) display effect, own enough charge time of horizontal scanning line, avoid large-capacity memory for pre-storing half picture data when in data transmission to reduce cost, only need one drive polarity on one sub data line in one picture and avoid frequent polarity conversion to reduce power consumption.
Description
Technical field
The present invention relates to a kind of display device, particularly relate to a kind of not enough and the display panel of reduction power consumption and display device of application thereof of horizontal scanning line duration of charging of improving.
Background technology
Thin Film Transistor-LCD (thin film transistor liquid crystal display abbreviates TFT LCD as) is because physical phenomenon more traditional iconoscope on the reaction velocity of animate of liquid crystal itself is slow.In order to improve dynamic afterimage (motion blur), industry utilization pulsed shows (Impulse TypeDisplay) technology, reduce the effect of picture ghost to insert black picture (black insertion) mode, simulate outside the solution with traditional iconoscope principle of similitude, and improve picture update rate (framerate or refresh rate) and shorten (vision) integral time, reach the purpose that reduces fuzzy edge (blur edge); In addition, when industry begins generally to use under the trend of double picture update rate (120Hz), existing structure some problems of will deriving, for example each is listed as horizontal time span and will reduces by half, and especially under high-resolution condition, will face not enough problem of duration of charging; And also have under the condition of double picture update rate, for the optimization of taking into account display panel drives, and adopted some counter-rotating (or 2V1H) type of drive, the output both positive and negative polarity bifurcation thixotroping rate (toggle rate) of source electrode driver will become original twice, the total power consumption of system will become multiple to grow up, derive heat problem simultaneously, will directly influence the fiduciary level of system.
The high-resolution display system structure that generally adopts as shown in Figure 1 at present, the display panel 101 of display device 100 is divided into block up and down, respectively by the gate drivers of both sides, come the activation of independent controlling level sweep trace, and be divided into block synchronous scanning up and down, because the time of each row horizontal scanning line (H_period)=1/ (picture update rate * horizontal scanning line number of times (V_toatl)), picture update rate is a twice in high-resolution applications.If panel is not divided into up and down block, the then horizontal time will become original half, and be the duration of charging that reaches capacity can become more not enough originally.So as the horizontal scanning line number of times of each block of Fig. 1 is original half, so the time of horizontal scanning line can keep the original length.The driving method of display panel 101 pictures counter-rotatings wherein, shown in the display panel structure figure of figure 2, M column scan line A1～AM, wherein M is a positive integer, during independent blocks synchronous scanning, each line data line all needs to do frequent polar switching up and down.Referring again to Fig. 3, Fig. 3 shows the data mapping figure into display panel, when synchronous scanning, Reginal-block scanning line AM/2+1 had been driven for the first time simultaneously under Reginal-block scanning line A1 reached on it, two Reginal-block scanning lines are driven in regular turn from top to bottom, and accomplish to reach down by Reginal-block scanning line AM/2 Reginal-block scanning line AM is driven the last time simultaneously always.This kind system architecture can face upper and lower region piece joint, and the phenomenon of picture inequality is arranged.And source electrode driver output both positive and negative polarity drives polarity and has the problem that number of transitions improves.And this mode must earlier put the data of a block (going up block) into internal memory (frame buffer), need deposit the data of half picture at least, so also improved the cost of system.
Summary of the invention
The invention provides a kind of display panel, when satisfying the operation of high picture update rate, can take into account the duration of charging of each row horizontal scanning line simultaneously and reduce power consumption, and display panel can produce the display effect of a counter-rotating.
The present invention also provides a kind of display device, and its display panel has some the display effect of counter-rotating image quality, and when satisfying high picture update rate operation, can take into account the duration of charging of each row horizontal scanning line simultaneously and reduce power consumption.
The present invention also provides a kind of display panel, when satisfying the operation of high picture update rate, can take into account the duration of charging of each row horizontal scanning line simultaneously and reduce power consumption, and panel can produce the display effect of 2line counter-rotating (2V1H).
The present invention also provides a kind of display device, and its display panel has the display effect of 2V1H image quality, and when satisfying the operation of high picture update rate, can take into account the duration of charging of each row horizontal scanning line simultaneously and reduce power consumption.
For realizing above-mentioned and other purpose, the present invention proposes a kind of display panel, is applicable to a flat display apparatus, comprises M column scan line, N line data line and M*N pixel, and wherein M, N are positive integer.Each line data line comprises one first subdata line and one second subdata line, M*N pixel lined up a matrix, make that i, j are integer, and 1≤i≤M, and 1≤j≤N, then the position is that i row and the capable pixel of j are expressed as P (i, j), the first subdata line that j is capable be coupled to pixel P (i, j), the second subdata line that j is capable be coupled to pixel P (i+1, j).
From another viewpoint, the present invention also proposes a kind of display device, comprises time schedule controller, gate drivers, first source electrode driver, second source electrode driver and display panel.Gate drivers, first source electrode driver and second source electrode driver all are coupled to time schedule controller.Display panel is coupled between source electrode driver and the gate drivers, and display panel comprises M column scan line, N line data line and M*N pixel, and wherein M, N are positive integer.M column scan line is driven by gate drivers.N line data line, its each line data line comprises one first subdata line and one second subdata line, and the first subdata line of each row is driven by first source electrode driver, the second subdata line of each row is driven by second source electrode driver.M*N pixel lined up a matrix, the position be i row and the capable pixel of j be expressed as P (i, j), wherein i, j are integer, and 1≤i≤M, and 1≤j≤N, and the first capable subdata line of j is coupled to pixel P (i, j), the second subdata line that j is capable be coupled to pixel P (i+1, j).Time sequence controller grid driver, first source electrode driver and second source electrode driver, make when being coupled to pixel P (i, during j) sweep trace activation, be coupled to pixel P (i+1, j) the also activation of sweep trace, and by first source electrode driver, the first subdata line that data-driven to the j is capable, the second subdata line that second source electrode driver is capable with data-driven to the j.
The present invention also proposes a kind of display panel, is applicable to a flat display apparatus, comprises M column scan line, N line data line and M*N pixel, and wherein M, N are positive integer.N line data line, each line data line comprise one first subdata line and one second subdata line.M*N pixel lined up a matrix, the position be i row and the capable pixel of j be expressed as P (i, j), wherein i, j are integer, and 1≤i≤M, and 1≤j≤N, and the first capable subdata line of j be coupled to pixel P (i, j) and pixel P (i+3, j), the second subdata line that j is capable be coupled to pixel P (i+1, j) and pixel P (i+2, j).
The present invention also proposes a kind of display device, comprises time schedule controller, gate drivers, first source electrode driver, second source electrode driver and display panel.Gate drivers, first source electrode driver and second source electrode driver all are coupled to time schedule controller.Display panel is coupled between source electrode driver and the gate drivers, and display panel comprises M column scan line, N line data line and M*N pixel, and wherein M, N are positive integer.M column scan line is driven by gate drivers.N line data line, its each line data line comprises one first subdata line and one second subdata line, and the first subdata line of each row is driven by first source electrode driver, the second subdata line of each row is driven by second source electrode driver.M*N pixel lined up a matrix, the position be i row and the capable pixel of j be expressed as P (i, j), wherein i, j are integer, and 1≤i≤M, and 1≤j≤N, and the first capable subdata line of j be coupled to pixel P (i, j) and pixel P (i+3, j), the second subdata line that j is capable be coupled to pixel P (i+1, j) and pixel P (i+2, j).The time sequence controller grid driver, first source electrode driver and second source electrode driver, make when being coupled to pixel P (i, during j) sweep trace activation, be coupled to pixel P (i+1, j) the also activation of sweep trace, by first source electrode driver with pixel P (i, j) the first subdata line that data-driven to the j is capable, second source electrode driver is with pixel P (i+1, j) the second subdata line that data-driven to the j is capable, (i+2 is during j) sweep trace activation when being coupled to pixel P, be coupled to pixel P (i+3, j) the also activation of sweep trace, by first source electrode driver with pixel P (i+3, the first subdata line that data-driven to the j j) is capable, second source electrode driver is with pixel P (i+2, the second subdata line that data-driven to the j j) is capable.
Display panel of the present invention, its each line data line adopts two strip data lines and the staggered structure that couples the pixel on this row of subdata line, the subdata line but can produce the display effect of a counter-rotating image quality or 2 line counter-rotatings (2V1H) when driving with the hurdle inversion mode, and the duration of charging of enough horizontal scanning lines is arranged.During these structural transmission data, need not use the high capacity internal memory and store the picture data mode in advance half again, and reduce cost.And each strip data line on the same picture has only one to drive polarity, need not frequently do the conversion of polarity bifurcation, therefore reduces power consumption.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment of the present invention cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 is existing display system structural drawing.
Fig. 2 is existing display panel structure figure.
Fig. 3 is the data mapping figure of existing display panel.
Fig. 4 is the display system structural drawing of one embodiment of the invention.
Fig. 5 is the data circuit gauge structure figure of the display panel of Fig. 4.
Fig. 6 is the design concept figure of the display panel of Fig. 4.
Fig. 7 is the data mapping figure of the display panel of Fig. 4.
Fig. 8 is the gate drivers sequential chart of Fig. 4.
Fig. 9 is the data circuit gauge structure figure of the display panel of another embodiment.
Figure 10 is the design concept figure of Fig. 9.
Figure 11 is the data mapping figure of Fig. 9.
The reference numeral explanation
100,400: display device
101,404,900: display panel
401,402: source electrode driver
403: gate drivers
405: time schedule controller
A1～AM, AM/2, AM/2+1, AM-1, Ai, Ai+1, Ai+2, Ai+3: sweep trace
CPV: gate clock signal
D1～DN: the second subdata line
P (1,1)～P (M, N): pixel
S1～Sn: the clock of source electrode driver
STV: grid initial pulse signal
U1～UN: the first subdata line
Embodiment
Please refer to Fig. 4, Fig. 4 shows the display system structural drawing of one embodiment of the invention.Display device 400 comprises time schedule controller 405, source electrode driver 401,402, gate drivers 403 and display panel 404.Gate drivers 403 is coupled to time schedule controller 405.Source electrode driver 401,402 is coupled to time schedule controller 405.Display panel 404 is coupled between source electrode driver 401,402 and the gate drivers 403.Time schedule controller 405 control gate drivers 403, source electrode driver 401 and 402.
For describing the structure of display panel 404 in detail, referring again to Fig. 5, Fig. 5 is the data circuit gauge structure figure of display panel 404.Display panel 404 comprises capable data line and M*N pixel of sweep trace A1～AM, N of M row, and wherein M, N are positive integer.The data line that N is capable comprises capable first subdata line U1～UN of N and the capable second subdata line D1～DN of N, and the first subdata line of each row is driven by source electrode driver 401, and the second subdata line of each row is driven by source electrode driver 402.Please Fig. 5 with Fig. 6 reference, Fig. 6 shows the design concept of display panel 404, because M*N pixel lined up a matrix, assumed position is that i row and the capable pixel of j are expressed as P (i, j), wherein i, j are integer, and 1≤i≤M, and 1≤j≤N, then the first subdata line that j is capable is coupled to pixel P (i, j), the second subdata line that j is capable be coupled to pixel P (i+1, j).When being coupled to pixel P (i, during j) sweep trace Ai activation, be coupled to pixel P (i+1, also activation of sweep trace Ai+1 j), by source electrode driver 401 (Fig. 4) the first subdata line that data-driven to the j is capable, the second subdata line that source electrode driver 402 (Fig. 4) is capable with data-driven to the j.When that is to say sweep trace Ai activation, sweep trace Ai+1 is activation in a gate clock also, and time schedule controller 405 (Fig. 4) Controlling Source driver 401 is simultaneously with the first subdata line U1～UN of data-driven to N line data line, and Controlling Source driver 402 is simultaneously with the second subdata line D1～DN of data-driven to N line data line, the first subdata line that wherein j is capable transmits data and gives pixel P (i, j), and the capable second subdata line of j transmit data give pixel P (i+1, j).
Please continue the diagram with reference to Fig. 5 and Fig. 6, furthermore bright driving method is supposed the driving polarity of first, second subdata line U1～UN and D1～DN, and+expression positive polarity drives, and-expression negative polarity drives.When same picture, the first subdata line U1, U3, U5 ..., UN-3, UN-1 and the second subdata line D2, D4, D6..., DN-2, DN be that positive polarity drives, the first subdata line U2, U4, U6 ..., UN-2, UN and the second subdata line D1, D3, D5..., DN-3, DN-1 be that negative polarity drives, and when the activation of different lines sweep trace, the polarity of voltage of first, second subdata line need not reverse.When entering next picture, the polarity of voltage of first, second subdata line just reverses, just the first subdata line U1, U3, U5 ..., UN-3, UN-1 and the second subdata line D2, D4, D6..., DN-2, DN be that negative polarity drives, the first subdata line U2, U4, U6 ..., UN-2, UN be the positive polarity driving with the second subdata line D1, D3, D5..., DN-3, DN-1.As can be seen, in same picture, no matter level or vertical direction, adjacent pixels all has opposite driving polarity, and same pixel arrived next picture, and it drives polarity and also can reverse.Display panel 404 its each line data lines have two strip data lines and staggered structure and the type of drive that couples the pixel on this row, but can make display panel 404 reach the best image image quality effect of a counter-rotating when source electrode driver uses hurdle counter-rotating (column inversion).Also have because of noting be used in to enter the next column sweep trace, do data line voltage reversal of poles, and reduce the cross-pressure number of times, so power consumption is less.
Fig. 7 shows the data mapping figure of display panel 404.When sweep trace A1 activation, sweep trace A2 is activation in a gate clock also, and time schedule controller 405 (Fig. 4) Controlling Source driver 401 (Fig. 4) in regular turn reading of data U1～U3 (clock S1), U4～U6 (clock S2) ..., UN-2～UN (clock Sn), and simultaneously with the first subdata line of data-driven to N line data line, and Controlling Source driver 402 (Fig. 4) in regular turn reading of data D1～D3 (clock S1), D4～D6 (clock S2) ..., DN-2～DN (clock Sn), and simultaneously with the second subdata line of data-driven to N line data line.With should sweep trace AM-1 activation the time, sweep trace AM is activation in a gate clock also, and the data mapping situation is as shown in scheming to go up.
Fig. 8 shows the sequential chart of gate drivers 403.When the time schedule controller 405 of display device 400 (Fig. 4) sends after grid initial pulse signal STV comes activation gate drivers 403, gate drivers 403 cooperates its gate clock signal CPV to send the M column scan signal, with activation M column scan line A1～AM, and being divided into M/2 time altogether, sweep signal sends, send the sweep signal of the adjacent two column scan lines of activation at every turn, as shown in the figure sweep signal in regular turn simultaneously activation sweep trace A1～A2, the sweep trace of activation simultaneously A3～A4 ..., the sweep trace of activation simultaneously AM-1～AM.Again because time=1/ (picture update rate * horizontal scanning line number of times) of each row horizontal scanning line, picture update rate is a twice in high-resolution applications, the horizontal scanning line number of times is original half, so the time of horizontal scanning line can keep the original length.
Can know the driving method of the display panel 403 of the embodiment of the invention from the explanation of Fig. 4～Fig. 8, comprise the following steps: step 1, please refer to the sequential chart of Fig. 8, after grid initial pulse signal STV activation, send the M column scan signal, with activation M column scan line A1～AM, and being divided into M/2 time altogether, sweep signal sends, send the sweep signal of the adjacent two column scan lines of activation at every turn; And step 2, please refer to the data mapping figure of Fig. 7, when sweep trace Ai, Ai+1 (or be AM-1 and AM as A1 and the A2 of Fig. 7) activation, with data-driven to N line data line, the capable first subdata line of y transmit data give pixel P (i, y), and the capable second subdata line of y transmits data and gives pixel P (i+1, y), and y is incremented to N in regular turn from 1, and y is a positive integer.
Another embodiment of the present invention is used the display system structural drawing as Fig. 4, but display panel wherein has different data circuit gauge structures, and the order of source electrode driver driving data is also slightly different.For describing the structure of display panel among this embodiment in detail, referring again to Fig. 9, Fig. 9 is the data circuit gauge structure figure of display panel.Display panel 900 comprises capable data line and M*N pixel of sweep trace A1～AM, N of M row, and wherein M, N are positive integer.The data line that N is capable comprises capable first subdata line U1～UN of N and the capable second subdata line D1～DN of N, and the first subdata line of each row is driven by source electrode driver 401, and the second subdata line of each row is driven by source electrode driver 402.Please Fig. 9 with Figure 10 reference, Figure 10 shows the design concept of display panel, M*N pixel lined up a matrix, assumed position be i row and the capable pixel of j be expressed as P (i, j), wherein i, j are integer, and 1≤i≤M, and 1≤j≤N, then the first subdata line that j is capable be coupled to pixel P (i, j) and pixel P (i+3, j), the second subdata line that j is capable be coupled to pixel P (i+1, j) and pixel P (i+2, j).If when being coupled to pixel P (i, during j) sweep trace Ai activation, be coupled to pixel P (i+1, j) also activation in a gate clock of sweep trace Ai+1, by source electrode driver 401 (Fig. 4) with pixel P (i, j) the first subdata line that data-driven to the j is capable, source electrode driver 402 (Fig. 4) is with pixel P (i+1, the second subdata line that data-driven to the j j) is capable.If when being coupled to pixel P (i+2, during j) sweep trace Ai+2 activation, be coupled to pixel P (i+3, j) also activation in a gate clock of sweep trace Ai+3, by source electrode driver 401 with pixel P (i+3, j) the first subdata line that data-driven to the j is capable, source electrode driver 402 is with pixel P (i+2, the second subdata line that data-driven to the j j) is capable.That is to say, if when sweep trace Ai activation, sweep trace Ai+1 is activation in a gate clock also, and time schedule controller 405 (Fig. 4) Controlling Source driver 401 is simultaneously with the first subdata line U1～UN of data-driven to N line data line, and Controlling Source driver 402 is simultaneously with the second subdata line D1～DN of data-driven to N line data line, the first subdata line that wherein j is capable transmit data give pixel P (i, j), and the capable second subdata line of j transmit data give pixel P (i+1, j).If when sweep trace Ai+2 activation, sweep trace Ai+3 is activation in a gate clock also, and time schedule controller 405 Controlling Source drivers 401 are simultaneously with the first subdata line U1～UN of data-driven to N line data line, and Controlling Source driver 402 is simultaneously with the second subdata line D1～DN of data-driven to N line data line, the first subdata line that wherein j is capable transmits data and gives pixel P (i+3, j), and the capable second subdata line of j transmit data give pixel P (i+2, j).
Please continue to refer again to the diagram of Fig. 9 and Figure 10, furthermore bright driving method.Suppose the driving polarity of first, second subdata line U1～UN and D1～DN ,+expression positive polarity drives, and-expression negative polarity drives.When same picture, the first subdata line U1, U3, U5 ..., UN-3, UN-1 and the second subdata line D2, D4, D6..., DN-2, DN be that positive polarity drives, the first subdata line U2, U4, U6 ..., UN-2, UN and the second subdata line D1, D3, D5..., DN-3, DN-1 be that negative polarity drives, and when the activation of different lines sweep trace, the polarity of voltage of first, second subdata line need not reverse.When entering next picture, the polarity of voltage of first, second subdata line just reverses, just the first subdata line U1, U3, U5 ..., UN-3, UN-1 and the second subdata line D2, D4, D6..., DN-2, DN be that negative polarity drives, the first subdata line U2, U4, U6 ..., UN-2, UN be the positive polarity driving with the second subdata line D1, D3, D5..., DN-3, DN-1.As can be seen, in same picture, from horizontal direction, the pixel of adjacent lines all has opposite driving polarity, and from vertical direction, the pixels of adjacent two row all have opposite driving polarity, and same pixel arrived next picture, and it drives polarity and also can reverse.Display panel 900 its each line data lines have two strip data lines and staggered structure and the type of drive that couples the pixel on this row of subdata line, when using hurdle counter-rotating (column inversion), source electrode driver but can make display panel 900 reach the display effect of 2line counter-rotating (2V1H), also have because not be used in and enter the next column sweep trace and will do data line voltage reversal of poles and reduce the cross-pressure number of times, so power consumption is less.
Figure 11 shows the data mapping figure of display panel 900.When sweep trace Ai activation, sweep trace Ai+1 is activation in a gate clock also, and time schedule controller 405 (Fig. 4) Controlling Source driver 401 (Fig. 4) in regular turn reading of data U1～U3 (clock S1), U4～U6 (clock S2) ..., UN-2～UN (clock Sn), and simultaneously with the first subdata line of data-driven to N line data line, and Controlling Source driver 402 (Fig. 4) in regular turn reading of data D1～D3 (clock S1), D4～D6 (clock S2) ..., DN-2～DN (clock Sn), and simultaneously with the second subdata line of data-driven to N line data line.With should sweep trace Ai+2 activation the time, sweep trace Ai+3 is activation in a gate clock also, and the data mapping situation is as shown in scheming to go up.
Can know the driving method of the display panel 900 of the embodiment of the invention from the explanation of Fig. 9～Figure 11, comprise the following steps: step 1, please refer to the sequential chart of Fig. 8, suppose after grid initial pulse signal STV activation, send the M column scan signal, with activation M column scan line A1～AM, and being divided into M/2 time altogether, sweep signal sends, send the sweep signal of the adjacent two column scan lines of activation at every turn; And step 2, please refer to the data mapping figure of Figure 11, when sweep trace Ai, Ai+1 activation, with data-driven to N line data line, the first subdata line that y is capable transmits data and gives pixel P (i, y), and the capable second subdata line of y transmit data give pixel P (i+1, y), when sweep trace Ai+2, Ai+3 activation, the capable second subdata line of y transmits data and gives pixel P (i+2, y), and the capable first subdata line of y transmit data give pixel P (i+3, y), and y is incremented to N in regular turn from 1, and y is a positive integer.
By the explanation of the invention described above embodiment as can be known, its each line data line of display panel has two strip data lines, and the staggered structure that couples the pixel on this row of subdata line, cooperate each adjacent two column scan line activations and data line with the hurdle inversion driving mode, but can produce the display effect of a counter-rotating image quality or 2line counter-rotating (2V1H), and make each row horizontal scanning line that enough duration of charging be arranged.Again during the transmission data of this structure, need not use jumbo internal memory and store picture data half, and the polarity of voltage because of each strip data line need not reverse in same picture, and each strip data line has only one to drive frequently bifurcation conversion of polarity.So the present invention can improve picture quality, and significantly reduce the cross-pressure number of times, reduce system power consumption.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (16)
1. display panel comprises:
M column scan line, wherein M is a positive integer;
N line data line, wherein N is a positive integer, and each line data line comprises one first subdata line and one second subdata line; And
M*N pixel lined up a matrix, the position be i row and the capable pixel of j be expressed as P (i, j), wherein i, j are integer, and 1≤i≤M, and 1≤j≤N, and the first capable subdata line of j is coupled to pixel P (i, j), the second subdata line that j is capable be coupled to pixel P (i+1, j).
2. display panel as claimed in claim 1, it is coupled to a gate drivers, one first source electrode driver, and one second source electrode driver, wherein, described sweep trace is driven by this gate drivers, the first subdata line of each row is driven by this first source electrode driver, the second subdata line of each row is driven by this second source electrode driver, when being coupled to pixel P (i, during j) sweep trace activation, be coupled to pixel P (i+1, j) sweep trace is also activation in a gate clock, by this first source electrode driver this first subdata line that data-driven to the j is capable, this second subdata line that this second source electrode driver is capable with data-driven to the j.
3. display device comprises:
Time schedule controller;
One gate drivers is coupled to this time schedule controller;
One first source electrode driver is coupled to this time schedule controller;
One second source electrode driver is coupled to this time schedule controller; And
One display panel is coupled between this source electrode driver and this gate drivers, and this display panel comprises:
M column scan line is driven by this gate drivers, and wherein M is a positive integer;
N line data line, each line data line comprises one first subdata line and one second subdata line, wherein N is a positive integer, and the first subdata line of each row is driven by this first source electrode driver, and the second subdata line of each row is driven by this second source electrode driver; And
M*N pixel lined up a matrix, the position be i row and the capable pixel of j be expressed as P (i, j), wherein i, j are integer, and 1≤i≤M, and 1≤j≤N, and the first capable subdata line of j is coupled to pixel P (i, j), the second subdata line that j is capable be coupled to pixel P (i+1, j)
Wherein, this time schedule controller is controlled this gate drivers, this first source electrode driver and this second source electrode driver, make when being coupled to pixel P (i, during j) sweep trace activation, be coupled to pixel P (i+1, j) sweep trace is also activation in a gate clock, by this first source electrode driver this first subdata line that data-driven to the j is capable, this second subdata line that this second source electrode driver is capable with data-driven to the j.
4. display device as claimed in claim 3, wherein after a grid initial pulse signal activation, this gate drivers sends the M column scan signal, with activation M column scan line, send and described sweep signal is divided into M/2 time altogether, send the sweep signal of the adjacent two column scan lines of activation at every turn.
5. display device as claimed in claim 4, wherein, when i row, the activation of i+1 column scan line, the capable first subdata line of y transmit data give pixel P (i, y), and the capable second subdata line of y transmits data and gives pixel P (i+1, y), and y is incremented to N in regular turn from 1, and y is a positive integer.
6. display device comprises:
Time schedule controller;
One gate drivers is coupled to this time schedule controller;
One first source electrode driver is coupled to this time schedule controller;
One second source electrode driver is coupled to this time schedule controller; And
One display panel is coupled between this source electrode driver and this gate drivers, and this display panel comprises:
M column scan line is driven by this gate drivers, and wherein M is a positive integer;
N line data line, each line data line comprises one first subdata line and one second subdata line, wherein N is a positive integer, and the first subdata line of each row is driven by this first source electrode driver, and the second subdata line of each row is driven by this second source electrode driver; And
M*N pixel, line up a matrix, the position be i row and the capable pixel of j be expressed as P (i, j), wherein i, j are integer, and 1≤i≤M, and 1≤j≤N, and the capable first subdata line and the i column scan line of j is coupled to pixel P (i, j), second subdata line that j is capable and i+1 column scan line be coupled to pixel P (i+1, j)
Wherein, this time schedule controller is controlled this gate drivers and is made when i column scan line activates, i+1 column scan line also activates, and this time schedule controller control this first source electrode driver simultaneously with data-driven to the first subdata line of described data line and control this second source electrode driver simultaneously with the second subdata line of data-driven to described data line.
7. display device as claimed in claim 6, wherein after a grid initial pulse signal activation, this gate drivers sends the M column scan signal, with activation M column scan line, send and described sweep signal is divided into M/2 time altogether, send the sweep signal of the adjacent two column scan lines of activation at every turn.
8. the driving method of a control signal, be applicable to a display panel, this display panel comprises M column scan line, N line data line, and M*N pixel, each line data line comprises one first subdata line and one second subdata line, all pixels are lined up a matrix, the position is that i row and the capable pixel of j are expressed as P (i, j), and the first capable subdata line of j be coupled to pixel P (i, j), the second subdata line that j is capable is coupled to pixel P (i+1, j), M wherein, N, i, j is a positive integer, and 1≤i≤M, and 1≤j≤N, the driving method of this control signal comprises the following steps:
After a grid initial pulse signal activation, send the M column scan signal, with activation M column scan line,, described sweep signal sends and being divided into M/2 time altogether, send the sweep signal of the adjacent two column scan lines of activation at every turn; And
When i row, the activation of i+1 column scan line, the first subdata line that y is capable transmit data give pixel P (i, y), and the capable second subdata line of y transmit data give pixel P (i+1, y), and y is incremented to N in regular turn from 1, y is a positive integer.
9. display panel comprises:
M column scan line, wherein M is a positive integer;
N line data line, wherein N is a positive integer, and each line data line comprises one first subdata line and one second subdata line; And
M*N pixel lined up a matrix, and the position is that i row and the capable pixel of j are expressed as P (i, j), wherein i, j are integer, and 1≤i≤M, and 1≤j≤N, and the first capable subdata line of j is coupled to pixel P (i, j) and pixel P (i+3, j), the second subdata line that j is capable is coupled to pixel P (i+1, j) and pixel P (i+2, j).
10. display panel as claimed in claim 9, it is coupled to a gate drivers, one first source electrode driver, and one second source electrode driver, wherein, described sweep trace is driven by this gate drivers, the first subdata line of each row is driven by this first source electrode driver, the second subdata line of each row is driven by this second source electrode driver, when being coupled to pixel P (i, during j) sweep trace activation, be coupled to pixel P (i+1, j) sweep trace is also activation in a gate clock, by this first source electrode driver with pixel P (i, j) this first subdata line that data-driven to the j is capable, this second source electrode driver is with pixel P (i+1, j) this second subdata line that data-driven to the j is capable, when being coupled to pixel P (i+2, during j) sweep trace activation, be coupled to pixel P (i+3, j) sweep trace is also activation in a gate clock, by this first source electrode driver with pixel P (i+3, j) this first subdata line that data-driven to the j is capable, this second source electrode driver is with pixel P (i+2, this second subdata line that data-driven to the j j) is capable.
11. a display device comprises:
Time schedule controller;
One gate drivers is coupled to this time schedule controller;
One first source electrode driver is coupled to this time schedule controller;
One second source electrode driver is coupled to this time schedule controller; And
One display panel is coupled between this source electrode driver and this gate drivers, and this display panel comprises:
M column scan line is driven by this gate drivers, and wherein M is a positive integer;
N line data line, each line data line comprises one first subdata line and one second subdata line, wherein N is a positive integer, and the first subdata line of each row is driven by this first source electrode driver, and the second subdata line of each row is driven by this second source electrode driver; And
M*N pixel, line up a matrix, the position is that i row and the capable pixel of j are expressed as P (i, j), i wherein, j is an integer, and 1≤i≤M, and 1≤j≤N, and the first capable subdata line of j is coupled to pixel P (i, j) and pixel P (i+3, j), the second subdata line that j is capable be coupled to pixel P (i+1, j) and pixel P (i+2, j), wherein, this time schedule controller is controlled this gate drivers, this first source electrode driver and this second source electrode driver make that (i is during j) sweep trace activation when being coupled to pixel P, be coupled to pixel P (i+1, j) the also activation of sweep trace, by this first source electrode driver with pixel P (i, this first subdata line that data-driven to the j j) is capable, this second source electrode driver is with pixel P (i+1, j) this second subdata line that data-driven to the j is capable, (i+2 is during j) sweep trace activation when being coupled to pixel P, be coupled to pixel P (i+3, j) the also activation of sweep trace, by this first source electrode driver with pixel P (i+3, this first subdata line that data-driven to the j j) is capable, this second source electrode driver is with pixel P (i+2, this second subdata line that data-driven to the j j) is capable.
12. display device as claimed in claim 11, wherein after a grid initial pulse signal activation, this gate drivers sends the M column scan signal, with activation M column scan line, send and described sweep signal is divided into M/2 time altogether, send the sweep signal of the adjacent two column scan lines of activation at every turn.
13. display device as claimed in claim 12, wherein, when i row, the activation of i+1 column scan line, the capable first subdata line of y transmit data give pixel P (i, y), and the capable second subdata line of y transmits data and gives pixel P (i+1, y), when i+2 row, the activation of i+3 column scan line, the first subdata line that y is capable transmit data give pixel P (i+3, y), and the capable second subdata line of y transmits data and gives pixel P (i+2, y), and y is incremented to N in regular turn from 1, and y is a positive integer.
14. a display device comprises:
Time schedule controller;
One gate drivers is coupled to this time schedule controller;
One first source electrode driver is coupled to this time schedule controller;
One second source electrode driver is coupled to this time schedule controller; And
One display panel is coupled between this source electrode driver and this gate drivers, and this display panel comprises:
M column scan line is driven by this gate drivers, and wherein M is a positive integer;
N line data line, each line data line comprises one first subdata line and one second subdata line, wherein N is a positive integer, and the first subdata line of each row is driven by this first source electrode driver, and the second subdata line of each row is driven by this second source electrode driver; And
M*N pixel, line up a matrix, the position is that i row and the capable pixel of j are expressed as P (i, j), i wherein, j is an integer, and 1≤i≤M, and 1≤j≤N, and the capable first subdata line and the i column scan line of j is coupled to pixel P (i, j), second subdata line that j is capable and i+1 column scan line be coupled to pixel P (i+1, j), the second subdata line and i+2 column scan line that j is capable are coupled to pixel P (i+2, j), first subdata line that j is capable and i+3 column scan line be coupled to pixel P (i+3, j), wherein, this time schedule controller is controlled this gate drivers and make that when i column scan line activated, i+1 column scan line also activated, when i+2 column scan line activates in a gate clock, i+3 column scan line also activates in a gate clock, and this time schedule controller control this first source electrode driver simultaneously with data-driven to the first subdata line of described data line and control this second source electrode driver simultaneously with the second subdata line of data-driven to described data line.
15. display device as claimed in claim 14, wherein after a grid initial pulse signal activation, this gate drivers sends the M column scan signal, with activation M column scan line, send and described sweep signal is divided into M/2 time altogether, send the sweep signal of the adjacent two column scan lines of activation at every turn.
16. the driving method of a control signal, be applicable to a display panel, this display panel comprises M column scan line, N line data line, and M*N pixel, each line data line comprises one first subdata line and one second subdata line, all pixels are lined up a matrix, the position be i row and the capable pixel of j be expressed as P (i, j), and the first capable subdata line of j is coupled to pixel P (i, j) and pixel P (i+3, j), the second subdata line that j is capable is coupled to pixel P (i+1, j) and pixel P (i+2, j), M wherein, N, i, j is a positive integer, and 1≤i≤M, and 1≤j≤N, the driving method of this control signal comprises the following steps:
After a grid initial pulse signal activation, send the M column scan signal, with activation M column scan line,, described sweep signal sends and being divided into M/2 time altogether, send the sweep signal of the adjacent two column scan lines of activation at every turn; And
When i row, the activation of i+1 column scan line, the capable first subdata line of y transmit data give pixel P (i, y), and the capable second subdata line of y transmits data and gives pixel P (i+1, y), when i+2 row, the activation of i+3 column scan line, the first subdata line that y is capable transmit data give pixel P (i+3, y), and the capable second subdata line of y transmits data and gives pixel P (i+2, y), and y is incremented to N in regular turn from 1, and y is a positive integer.
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