CN101226290A - Display panel, display device using same and driving method of control signal - Google Patents

Abstract

A display panel and display device using the same and driving method of control signal, each row of data link of the display panel adopts two sub data link and sub data link cross-coupling to the structure of the pixel on this row, while the sub data link will produce the display effect of the dot inversion picture quality or 2line inversion (2V1H) with the column inversion (column inversion) driving mode, and there is sufficient charging time of the horizontal scanning line, and does not need to use the large-capacity memory to store half a picture data mode in advance and reduce the cost while transmitting the data, and each sub data link has only one driving polarity on the same picture, do not need to make the polarity conversion frequently, therefore reduce the power consumption.

Description

Display panel and display device for its application and driving method of control signal

technical field

The present invention relates to a display device, in particular to a display panel which improves the insufficient charging time of horizontal scanning lines and reduces power consumption, and a display device for its application.

Background technique

Thin film transistor liquid crystal display (referred to as TFT LCD) due to the physical phenomenon of liquid crystal itself, the reaction speed of animation performance is slower than that of traditional image tubes. In order to improve the motion blur, the industry uses Impulse Type Display technology to reduce the effect of image residue by inserting a black screen (black insertion) to simulate one of the solutions similar to the principle of traditional image tubes. In addition, and increase the frame rate (frame or refresh rate) to shorten the (visual) integration time, to achieve the purpose of reducing the blur edge (blur edge); in addition, when the industry began to generally use double frame rate (120Hz) under the trend , the current structure will lead to some problems, such as the time length of each column of horizontal lines will be halved, especially under the condition of high resolution, it will face the problem of insufficient charging time; and under the condition of double picture update rate, for Taking into account the optimal driving of the display panel, and adopting the dot inversion (or 2V1H) driving method, the output positive and negative polarity toggle rate of the source driver will be doubled, and the system The total power consumption will grow exponentially, and at the same time, thermal problems will be derived, which will directly affect the reliability of the system.

The system structure of a high-resolution display device commonly used at present is shown in FIG. 1 . The display panel 101 of the display device 100 is divided into upper and lower blocks, and the gate drivers on both sides are used to independently control the enablement of the horizontal scanning lines. And it is divided into upper and lower blocks for synchronous scanning, because the time (H_period) of each column of horizontal scanning lines=1/(frame update rate*number of horizontal scan lines (V_toatl)), the frame refresh rate is doubled in high-resolution applications. If the panel is not divided into upper and lower blocks, the time of the horizontal line will become half of the original, and the charging time that has already reached the limit will become more insufficient. Therefore, the number of horizontal scanning lines in each block as shown in FIG. 1 is half of the original, so the time of the horizontal scanning lines can maintain the original length. Wherein, the driving method of display panel 101 picture inversion is shown in the structure diagram of the display panel with reference to FIG. Do frequent polarity reversals. Please refer to FIG. 3 again. FIG. 3 shows the data map of the display panel. When scanning synchronously, the scanning line A1 of the upper block and the scanning line AM/2+1 of the lower block are simultaneously driven for the first time. The scanning lines of the two blocks are driven sequentially from top to bottom until the scanning line AM/2 of the upper block and the scanning line AM of the lower block are driven at the same time for the last time. This kind of system structure will face the joint of the upper and lower blocks, and there will be picture unevenness. In addition, there is a problem that the number of times of switching of the positive and negative driving polarities of the source driver output increases. Moreover, this method must first put the data of one block (upper block) into the memory (frame buffer), at least half of the frame data needs to be stored, so the cost of the system is also increased.

Contents of the invention

The present invention provides a display panel, which can simultaneously take into account the charging time of each horizontal scanning line and reduce power consumption when operating at a high frame update rate, and the display panel can produce a display effect of dot inversion.

The present invention also provides a display device, the display panel of which has the display effect of dot inversion image quality, and can simultaneously take into account the charging time of each row of horizontal scanning lines and reduce power consumption when operating at a high frame refresh rate.

The present invention also provides a display panel, which can simultaneously take into account the charging time of each horizontal scanning line and reduce power consumption when operating at a high frame refresh rate, and the panel can produce a 2-line inversion (2V1H) display effect.

The present invention also provides a display device, the display panel of which has the display effect of 2V1H image quality, and can simultaneously take into account the charging time of each row of horizontal scanning lines and reduce power consumption when operating at a high frame refresh rate.

To achieve the above and other objectives, the present invention proposes a display panel suitable for a flat display device, including M columns of scanning lines, N rows of data lines and M*N pixels, wherein M and N are positive integers. Each row of data lines includes a first sub-data line and a second sub-data line, M*N pixels are arranged in a matrix, let i, j be integers, and 1≤i≤M, and 1≤j≤N, Then the pixel at the i-th column and the j-th row is represented as P(i, j), the first sub-data line in the j-th row is coupled to the pixel P(i, j), and the second sub-data line in the j-th row coupled to pixel P(i+1, j).

From another point of view, the present invention also provides a display device including a timing controller, a gate driver, a first source driver, a second source driver and a display panel. The gate driver, the first source driver and the second source driver are all coupled to the timing controller. The display panel is coupled between the source driver and the gate driver. The display panel includes M columns of scan lines, N rows of data lines and M*N pixels, wherein M and N are positive integers. M columns of scan lines are driven by a gate driver. N rows of data lines, each row of data lines includes a first sub-data line and a second sub-data line, and the first sub-data line of each row is driven by the first source driver, and the second sub-data line of each row line is driven by a second source driver. M*N pixels are arranged in a matrix, and the pixel at the i-th column and j-th row is expressed as P(i, j), where i, j are integers, and 1≤i≤M, and 1≤j≤N , and the first sub-data line in the j-th row is coupled to the pixel P(i, j), and the second sub-data line in the j-th row is coupled to the pixel P(i+1, j). The timing controller controls the gate driver, the first source driver and the second source driver so that when the scan line coupled to the pixel P(i,j) is enabled, the scan line coupled to the pixel P(i+1,j) ) is also enabled, and the first source driver drives data to the first sub-data line in row j, and the second source driver drives data to the second sub-data line in row j.

The present invention also proposes a display panel suitable for a flat display device, including M columns of scanning lines, N rows of data lines, and M*N pixels, wherein M and N are positive integers. N rows of data lines, each row of data lines includes a first sub-data line and a second sub-data line. M*N pixels are arranged in a matrix, and the pixel at the i-th column and j-th row is expressed as P(i, j), where i, j are integers, and 1≤i≤M, and 1≤j≤N , and the first sub-data line of the j-th row is coupled to the pixel P(i, j) and the pixel P(i+3, j), and the second sub-data line of the j-th row is coupled to the pixel P(i+1 , j) and pixel P(i+2, j).

The present invention also provides a display device, including a timing controller, a gate driver, a first source driver, a second source driver and a display panel. The gate driver, the first source driver and the second source driver are all coupled to the timing controller. The display panel is coupled between the source driver and the gate driver. The display panel includes M columns of scan lines, N rows of data lines and M*N pixels, wherein M and N are positive integers. M columns of scan lines are driven by a gate driver. N rows of data lines, each row of data lines includes a first sub-data line and a second sub-data line, and the first sub-data line of each row is driven by the first source driver, and the second sub-data line of each row line is driven by a second source driver. M*N pixels are arranged in a matrix, and the pixel at the i-th column and j-th row is expressed as P(i, j), where i, j are integers, and 1≤i≤M, and 1≤j≤N , and the first sub-data line of the j-th row is coupled to the pixel P(i, j) and the pixel P(i+3, j), and the second sub-data line of the j-th row is coupled to the pixel P(i+1 , j) and pixel P(i+2, j). The timing controller controls the gate driver, the first source driver and the second source driver so that when the scan line coupled to the pixel P(i,j) is enabled, the scan line coupled to the pixel P(i+1,j) ) is also enabled, the first source driver drives the data of the pixel P(i, j) to the first sub-data line of the j-th row, and the second source driver drives the data of the pixel P(i+1, j ) is driven to the second sub-data line of the j-th row, when the scan line coupled to the pixel P(i+2,j) is enabled, the scan line coupled to the pixel P(i+3,j) It is also enabled, the first source driver drives the data of the pixel P(i+3, j) to the first sub-data line of the j-th row, and the second source driver drives the data of the pixel P(i+2, j) Data is driven to the second sub-data line of the j-th row.

In the display panel of the present invention, each row of data lines adopts the structure of two sub-data lines and the sub-data lines are interleavedly coupled to the pixels on this row, but when the sub-data lines are driven in a column inversion manner, dot inversion image quality or 2 line inversion (2V1H) display effect, and there is enough charging time for horizontal scanning lines. Furthermore, when data is transmitted with this structure, there is no need to use a large-capacity memory to pre-store half of the screen data, thereby reducing costs. Moreover, each sub-data line on the same screen has only one driving polarity, so there is no need for frequent polarity switching, thus reducing power consumption.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments of the present invention are specifically cited below, and are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a structural diagram of a conventional display device system.

FIG. 2 is a structural diagram of a conventional display panel.

FIG. 3 is a data mapping diagram of a conventional display panel.

FIG. 4 is a structural diagram of a display device system according to an embodiment of the present invention.

FIG. 5 is a structural diagram of data line paths of the display panel shown in FIG. 4 .

FIG. 6 is a schematic design diagram of the display panel shown in FIG. 4 .

FIG. 7 is a data map of the display panel of FIG. 4 .

FIG. 8 is a timing diagram of the gate driver in FIG. 4 .

FIG. 9 is a structural diagram of data line paths of a display panel according to another embodiment.

FIG. 10 is a design schematic diagram of FIG. 9 .

FIG. 11 is a data map of FIG. 9 .

Description of reference symbols

100, 400: display device

101, 404, 900: display panel

401, 402: source driver

403: Gate Driver

405: timing controller

A1～AM, AM/2, AM/2+1, AM-1, Ai, Ai+1, Ai+2, Ai+3: scan line

CPV: gate clock signal

D1～DN: the second sub-data line

P(1,1)~P(M,N): Pixels

S1～Sn: Clock of source driver

STV: gate start pulse signal

U1～UN: the first sub-data line

Detailed ways

Please refer to FIG. 4 , which shows a structural diagram of a display device system according to an embodiment of the present invention. The display device 400 includes a timing controller 405 , source drivers 401 , 402 , a gate driver 403 and a display panel 404 . The gate driver 403 is coupled to the timing controller 405 . The source drivers 401 and 402 are coupled to a timing controller 405 . The display panel 404 is coupled between the source drivers 401 , 402 and the gate driver 403 . The timing controller 405 controls the gate driver 403 , the source drivers 401 and 402 .

To describe the structure of the display panel 404 in detail, please refer to FIG. 5 , which is a structure diagram of the data line routing of the display panel 404 . The display panel 404 includes M columns of scan lines A1 -AM, N rows of data lines and M*N pixels, wherein M and N are positive integers. N rows of data lines include N rows of first sub-data lines U1-UN and N rows of second sub-data lines D1-DN. The first sub-data lines of each row are driven by the source driver 401, and the second sub-data lines of each row The data lines are driven by source drivers 402 . Please refer to FIG. 5 and FIG. 6 together. FIG. 6 shows the design principle of the display panel 404, because M*N pixels are arranged in a matrix, assuming that the pixel at the i-th column and the j-th row is represented as P(i, j), where i and j are integers, and 1≤i≤M, and 1≤j≤N, then the first sub-data line in row j is coupled to pixel P(i, j), and the first sub-data line in row j is coupled to pixel P(i, j). The two sub-data lines are coupled to the pixel P(i+1, j). When the scan line Ai coupled to the pixel P(i, j) is enabled, the scan line Ai+1 coupled to the pixel P(i+1, j) is also enabled, and the source driver 401 ( FIG. 4 ) The data is driven to the first sub-data line of the j-th row, and the source driver 402 ( FIG. 4 ) drives the data to the second sub-data line of the j-th row. That is to say, when the scan line Ai is enabled, the scan line Ai+1 is also enabled within one gate clock, and the timing controller 405 ( FIG. 4 ) controls the source driver 401 to simultaneously drive data to the first data line of the N rows. One sub-data line U1-UN, and control source driver 402 to simultaneously drive data to the second sub-data line D1-DN of the N rows of data lines, wherein the first sub-data line in the jth row transmits data to the pixel P(i , j), and the second sub-data line in the j-th row transmits data to the pixel P(i+1, j).

Please continue to refer to the illustrations in Figure 5 and Figure 6 to further explain the driving method, assuming the driving polarities of the first and second sub-data lines U1~UN and D1~DN, + means positive polarity driving, - means negative polarity driving . In the same screen, the first sub-data lines U1, U3, U5, ..., UN-3, UN-1 and the second sub-data lines D2, D4, D6..., DN-2, DN are positive polarity drive, the first sub-data lines U2, U4, U6, ..., UN-2, UN and the second sub-data lines D1, D3, D5 ..., DN-3, DN-1 are driven by negative polarity, and When the scan lines of different columns are enabled, the voltage polarities of the first and second sub-data lines do not need to be reversed. When entering the next screen, the voltage polarities of the first and second sub-data lines are reversed, that is, the first sub-data lines U1, U3, U5, ..., UN-3, UN-1 and the first sub-data lines U1, U3, U5, ..., UN-3, UN-1 and the The second sub-data lines D2, D4, D6..., DN-2, DN are driven by negative polarity, the first sub-data lines U2, U4, U6, ..., UN-2, UN and the second sub-data line D1 , D3, D5..., DN-3, DN-1 are positive drive. It can be seen that in the same picture, no matter in the horizontal or vertical direction, adjacent pixels have opposite driving polarities, and the driving polarity of the same pixel will also be reversed in the next picture. Each row of data lines of the display panel 404 has two sub-data lines and the structure and driving method of interleavingly coupling the pixels on this row, when the source driver uses column inversion (column inversion), the display panel 404 can achieve dot inversion The best display quality effect for . In addition, because there is no need to invert the polarity of the data line voltage when entering the next row of scan lines, the number of voltage crossings is reduced, so the power consumption is relatively small.

FIG. 7 shows a data map of the display panel 404 . When the scan line A1 is enabled, the scan line A2 is also enabled within a gate clock, and the timing controller 405 ( FIG. 4 ) controls the source driver 401 ( FIG. 4 ) to sequentially read data U1-U3 (clock S1 ), U4～U6 (clock S2), ..., UN-2～UN (clock Sn), and simultaneously drive the data to the first sub-data line of the N row data lines, and control the source driver 402 (Figure 4 ) sequentially read data D1~D3 (clock S1), D4~D6 (clock S2), ..., DN-2~DN (clock Sn), and drive the data to the second sub-section of the N row of data lines at the same time data line. Similarly, when the scan line AM-1 is enabled, the scan line AM is also enabled within one gate clock, and the data mapping situation is shown in the figure.

FIG. 8 shows a timing diagram of the gate driver 403 . After the timing controller 405 of the display device 400 (FIG. 4) sends out the gate start pulse signal STV to enable the gate driver 403, the gate driver 403 sends M column scanning signals in conjunction with its gate clock signal CPV to enable M scan lines A1-AM, and the scan signal is divided into M/2 times to send out, each time a scan signal that enables two adjacent scan lines is sent out, as shown in the figure, the scan signals enable the scan lines A1-A2 in sequence . Simultaneously enabling the scanning lines A3 - A4 , . . . and simultaneously enabling the scanning lines AM- 1 -AM. And because the time of each row of horizontal scanning lines=1/(picture update rate*horizontal scanning line times), in high-resolution applications, the picture updating rate is doubled, and the number of horizontal scanning lines is half of the original, so the horizontal scanning line Time can maintain the original length.

From the descriptions in FIGS. 4 to 8, it can be known that the driving method of the display panel 403 in the embodiment of the present invention includes the following steps: Step 1, please refer to the timing diagram in FIG. 8, when the gate start pulse signal STV is enabled, send M columns of scanning signals to enable M columns of scanning lines A1 to AM, and the scanning signals are divided into M/2 times to be sent out, and each time a scanning signal for enabling two adjacent columns of scanning lines is sent; and step 2, please refer to FIG. 7 The data mapping diagram, when the scan lines Ai, Ai+1 (such as A1 and A2 in Figure 7 or AM-1 and AM) are enabled, the data is driven to the N rows of data lines, the first sub-line of the yth row The data line transmits data to the pixel P(i, y), and the second sub-data line in the yth row transmits data to the pixel P(i+1, y), and y is sequentially incremented from 1 to N, and y is a positive integer .

Another embodiment of the present invention uses the system structure diagram of the display device shown in FIG. 4 , but the display panel therein has a different data line path structure, and the sequence of driving data by the source driver is also slightly different. To describe the structure of the display panel in this embodiment in detail, please refer to FIG. 9 again, which is a structural diagram of the routing of the data lines of the display panel. The display panel 900 includes M columns of scan lines A1 -AM, N rows of data lines and M*N pixels, wherein M and N are positive integers. N rows of data lines include N rows of first sub-data lines U1-UN and N rows of second sub-data lines D1-DN. The first sub-data lines of each row are driven by the source driver 401, and the second sub-data lines of each row The data lines are driven by source drivers 402 . Please refer to Figure 9 and Figure 10 together. Figure 10 shows the design principle of the display panel. M*N pixels are arranged in a matrix. Assume that the pixel at the i-th column and the j-th row is represented as P(i, j) , where i and j are integers, and 1≤i≤M, and 1≤j≤N, then the first sub-data line in row j is coupled to pixel P(i, j) and pixel P(i+3, j), the second sub-data line in the jth row is coupled to the pixel P(i+1, j) and the pixel P(i+2, j). If when the scan line Ai coupled to the pixel P(i, j) is enabled, the scan line Ai+1 coupled to the pixel P(i+1, j) is also enabled within a gate clock, the source The electrode driver 401 (FIG. 4) drives the data of the pixel P(i, j) to the first sub-data line of the j-th row, and the source driver 402 (FIG. 4) drives the data of the pixel P(i+1, j) to the second sub-data line in row j. If the scan line Ai+2 coupled to the pixel P(i+2,j) is enabled, the scan line Ai+3 coupled to the pixel P(i+3,j) is also activated within one gate clock. can, the source driver 401 drives the data of the pixel P(i+3, j) to the first sub-data line of the j-th row, and the source driver 402 drives the data of the pixel P(i+2, j) to the first sub-data line of the jth row. The second sub-data line of row j. That is to say, if when the scan line Ai is enabled, the scan line Ai+1 is also enabled within one gate clock, and the timing controller 405 ( FIG. 4 ) controls the source driver 401 to simultaneously drive data to N rows of data The first sub-data lines U1-UN of the line, and the control source driver 402 to drive data to the second sub-data lines D1-DN of the data lines of N rows at the same time, wherein the first sub-data line of the j-th row transmits data to the pixel P(i, j), and the second sub-data line in the jth row transmits data to the pixel P(i+1, j). If when the scan line Ai+2 is enabled, the scan line Ai+3 is also enabled within one gate clock, and the timing controller 405 controls the source driver 401 to simultaneously drive data to the first sub-data of the N rows of data lines Lines U1-UN, and control source driver 402 to simultaneously drive data to the second sub-data lines D1-DN of N rows of data lines, wherein the first sub-data line in the j-th row transmits data to the pixel P(i+3, j), and the second sub-data line in the jth row transmits data to the pixel P(i+2, j).

Please continue to refer to FIG. 9 and FIG. 10 to further describe the driving method. Assuming the driving polarities of the first and second sub-data lines U1-UN and D1-DN, + indicates positive polarity driving, and - indicates negative polarity driving. In the same screen, the first sub-data lines U1, U3, U5, ..., UN-3, UN-1 and the second sub-data lines D2, D4, D6..., DN-2, DN are positive polarity drive, the first sub-data lines U2, U4, U6, ..., UN-2, UN and the second sub-data lines D1, D3, D5 ..., DN-3, DN-1 are driven by negative polarity, and When the scan lines of different columns are enabled, the voltage polarities of the first and second sub-data lines do not need to be reversed. When entering the next screen, the voltage polarities of the first and second sub-data lines are reversed, that is, the first sub-data lines U1, U3, U5, ..., UN-3, UN-1 and the first sub-data lines U1, U3, U5, ..., UN-3, UN-1 and the The second sub-data lines D2, D4, D6..., DN-2, DN are driven by negative polarity, the first sub-data lines U2, U4, U6, ..., UN-2, UN and the second sub-data line D1 , D3, D5..., DN-3, DN-1 are positive drive. It can be seen that in the same picture, from the horizontal direction, the pixels in adjacent rows have opposite driving polarities, and from the vertical direction, the pixels in two adjacent columns have opposite driving polarities, and the same pixel arrives In the next frame, the driving polarity will also be reversed. In the display panel 900, each row of data lines has two sub-data lines and the sub-data lines are interleavedly coupled to the structure and driving mode of the pixels on this row. When the source driver uses column inversion (column inversion), the display panel 900 can achieve The display effect of 2line inversion (2V1H), and because there is no need to invert the polarity of the data line voltage when entering the next row of scanning lines, the number of voltage crossings is reduced, so the power consumption is small.

FIG. 11 shows a data map of the display panel 900 . When the scan line Ai is enabled, the scan line Ai+1 is also enabled within one gate clock, and the timing controller 405 ( FIG. 4 ) controls the source driver 401 ( FIG. 4 ) to sequentially read data U1-U3 ( clock S1), U4～U6 (clock S2), ..., UN-2～UN (clock Sn), and simultaneously drive the data to the first sub-data line of the N row data lines, and control the source driver 402 ( Figure 4) Read data D1~D3 (clock S1), D4~D6 (clock S2), ..., DN-2~DN (clock Sn) in sequence, and drive the data to the first row of N data lines at the same time Second sub-data line. Similarly, when the scan line Ai+2 is enabled, the scan line Ai+3 is also enabled within one gate clock, and the data mapping situation is shown in the figure.

From the descriptions of FIGS. 9 to 11 , it can be known that the driving method of the display panel 900 according to the embodiment of the present invention includes the following steps: Step 1, please refer to the timing diagram of FIG. 8 , assuming that after the gate start pulse signal STV is enabled, Send M columns of scanning signals to enable M columns of scanning lines A1~AM, and the scanning signals are divided into M/2 times to send out, and each time a scanning signal is sent to enable two adjacent scanning lines; and step 2, please refer to the figure In the data map of 11, when the scan lines Ai and Ai+1 are enabled, the data is driven to the data lines of N rows, and the first sub-data line in the yth row transmits data to the pixel P(i, y), and the yth row The second sub-data line in the row transmits data to the pixel P(i+1, y). When the scan lines Ai+2 and Ai+3 are enabled, the second sub-data line in the y-th row transmits data to the pixel P(i+2 , y), and the first sub-data line in the yth row transmits data to the pixel P(i+3, y), and y is sequentially incremented from 1 to N, and y is a positive integer.

It can be seen from the description of the above-mentioned embodiments of the present invention that each row of data lines of the display panel has two sub-data lines, and the sub-data lines are alternately coupled to the structure of pixels on this row, and each time two adjacent columns of scan lines enable and The data line is driven by column inversion, but it will produce dot inversion image quality or 2line inversion (2V1H) display effect, and make each horizontal scanning line have sufficient charging time. When transmitting data with this structure, there is no need to use a large-capacity memory to store half of the screen data, and because the voltage polarity of each sub-data line does not need to be reversed in the same screen, each sub-data line has only one The drive polarity does not need to toggle frequently. Therefore, the present invention can improve the image quality, greatly reduce the number of voltage crossings, and reduce the power consumption of the system.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection is based on the claims of the present invention.

Claims (16)

1. A display panel, comprising: M columns of scan lines, where M is a positive integer; N rows of data lines, wherein N is a positive integer, and each row of data lines includes a first sub-data line and a second sub-data line; and M*N pixels are arranged in a matrix, and the pixels at the i-th column and j-th row are expressed as P(i, j), where i, j are integers, and 1≤i≤M, and 1≤j≤ N, and the first sub-data line of the jth row is coupled to the pixel P(i, j), and the second sub-data line of the jth row is coupled to the pixel P(i+1, j). 2. The display panel according to claim 1, which is coupled to a gate driver, a first source driver, and a second source driver, wherein the scan lines are driven by the gate driver, The first sub-data line of each row is driven by the first source driver, and the second sub-data line of each row is driven by the second source driver. When the scan line coupled to the pixel P(i, j) When enabled, the scan line coupled to the pixel P(i+1, j) is also enabled within a gate clock, and the first source driver drives data to the first sub-data line of the j-th row , the second source driver drives data to the second sub-data line in the j-th row. 3. A display device, comprising: a timing controller; a gate driver coupled to the timing controller; a first source driver coupled to the timing controller; a second source driver coupled to the timing controller; and A display panel, coupled between the source driver and the gate driver, the display panel includes: M columns of scan lines are driven by the gate driver, where M is a positive integer; N rows of data lines, each row of data lines includes a first sub-data line and a second sub-data line, wherein N is a positive integer, the first sub-data line of each row is driven by the first source driver, each row The second sub-data line is driven by the second source driver; and M*N pixels are arranged in a matrix, and the pixels at the i-th column and j-th row are expressed as P(i, j), where i, j are integers, and 1≤i≤M, and 1≤j≤ N, and the first sub-data line of the j-th row is coupled to the pixel P(i, j), and the second sub-data line of the j-th row is coupled to the pixel P(i+1, j), Wherein, the timing controller controls the gate driver, the first source driver and the second source driver so that when the scan line coupled to the pixel P(i, j) is enabled, the scan line coupled to the pixel P The scan line (i+1, j) is also enabled within a gate clock, and the first source driver drives the data to the first sub-data line of the j-th row, and the second source driver drives the data driven to the second sub-data line in row j. 4. The display device as claimed in claim 3 , wherein after a gate start pulse signal is enabled, the gate driver sends M columns of scan signals to enable M columns of scan lines, and the scan signals are divided into M/2 times are sent out, each time a scan signal enabling two adjacent scan lines is sent out. 5. The display device according to claim 4, wherein when the i-th column and the i+1th column scan line are enabled, the first sub-data line in the y-th row transmits data to the pixel P(i, y), And the second sub-data line in the yth row transmits data to the pixel P(i+1, y), and y is sequentially incremented from 1 to N, and y is a positive integer. 6. A display device comprising: a timing controller; a gate driver coupled to the timing controller; a first source driver coupled to the timing controller; a second source driver coupled to the timing controller; and A display panel, coupled between the source driver and the gate driver, the display panel includes: M columns of scan lines are driven by the gate driver, where M is a positive integer; N rows of data lines, each row of data lines includes a first sub-data line and a second sub-data line, wherein N is a positive integer, the first sub-data line of each row is driven by the first source driver, each row The second sub-data line is driven by the second source driver; and M*N pixels are arranged in a matrix, and the pixels at the i-th column and j-th row are expressed as P(i, j), where i, j are integers, and 1≤i≤M, and 1≤j≤ N, and the first sub-data line of row j and the scan line of column i are coupled to the pixel P(i, j), the second sub-data line of row j and the scan line of column i+1 are coupled to the pixel P(i+1,j), Wherein, the timing controller controls the gate driver so that when the i-th column scan line is actuated, the i+1th column scan line is also actuated, and the timing controller controls the first source driver to simultaneously drive data to the The first sub-data line of the data line and the second sub-data line for controlling the second source driver to drive data to the data line at the same time. 7. The display device as claimed in claim 6 , wherein after a gate start pulse signal is enabled, the gate driver sends M columns of scan signals to enable M columns of scan lines, and the scan signals are divided into M/2 times are sent out, each time a scan signal enabling two adjacent scan lines is sent out. 8. A driving method of a control signal, applicable to a display panel, the display panel includes M columns of scan lines, N rows of data lines, and M*N pixels, each row of data lines includes a first sub-data line and a For the second sub-data line, all pixels are arranged in a matrix, and the pixel at the i-th column and the j-th row is represented as P(i, j), and the first sub-data line of the j-th row is coupled to the pixel P(i , j), the second sub-data line in row j is coupled to pixel P(i+1, j), where M, N, i, j are positive integers, and 1≤i≤M, and 1≤j≤ N, the driving method of the control signal includes the following steps: After a grid start pulse signal is enabled, M columns of scanning signals are issued to enable M columns of scanning lines, and the scanning signals are divided into M/2 times to be issued, and each time the scanning signals are issued to enable two adjacent columns of scanning lines scan signal; and When the i-th column and the i+1th column scan line are enabled, the first sub-data line in the y-th row transmits data to the pixel P(i, y), and the second sub-data line in the y-th row transmits data to the pixel P (i+1, y), and y increases sequentially from 1 to N, and y is a positive integer. 9. A display panel, comprising: M columns of scan lines, where M is a positive integer; N rows of data lines, wherein N is a positive integer, and each row of data lines includes a first sub-data line and a second sub-data line; and M*N pixels are arranged in a matrix, and the pixels at the i-th column and j-th row are expressed as P(i, j), where i, j are integers, and 1≤i≤M, and 1≤j≤ N, and the first sub-data line of row j is coupled to pixel P(i, j) and pixel P(i+3, j), and the second sub-data line of row j is coupled to pixel P(i+3, j). 1, j) and pixel P(i+2, j). 10. The display panel as claimed in claim 9, which is coupled to a gate driver, a first source driver, and a second source driver, wherein the scan lines are driven by the gate driver, The first sub-data line of each row is driven by the first source driver, and the second sub-data line of each row is driven by the second source driver. When the scan line coupled to the pixel P(i, j) When enabled, the scan line coupled to the pixel P(i+1, j) is also enabled within a gate clock, and the first source driver drives the data of the pixel P(i, j) to the jth The first sub-data line of the row, the second source driver drives the data of the pixel P(i+1, j) to the second sub-data line of the j-th row, when coupled to the pixel P(i+2 , j) when the scanning line is enabled, the scanning line coupled to the pixel P (i+3, j) is also enabled within a gate clock, and the pixel P (i+3, j) is driven by the first source driver The data of j) is driven to the first sub-data line of the j-th row, and the second source driver drives the data of the pixel P(i+2, j) to the second sub-data line of the j-th row. 11. A display device comprising: a timing controller; a gate driver coupled to the timing controller; a first source driver coupled to the timing controller; a second source driver coupled to the timing controller; and A display panel, coupled between the source driver and the gate driver, the display panel includes: M columns of scan lines are driven by the gate driver, where M is a positive integer; N rows of data lines, each row of data lines includes a first sub-data line and a second sub-data line, wherein N is a positive integer, the first sub-data line of each row is driven by the first source driver, each row The second sub-data line is driven by the second source driver; and M*N pixels are arranged in a matrix, and the pixels at the i-th column and j-th row are expressed as P(i, j), where i, j are integers, and 1≤i≤M, and 1≤j≤ N, and the first sub-data line of row j is coupled to pixel P(i, j) and pixel P(i+3, j), and the second sub-data line of row j is coupled to pixel P(i+3, j). 1, j) and a pixel P(i+2, j), wherein the timing controller controls the gate driver, the first source driver and the second source driver so that when coupled to the pixel P(i , j) when the scanning line is enabled, the scanning line coupled to the pixel P(i+1, j) is also enabled, and the first source driver drives the data of the pixel P(i, j) to the jth The first sub-data line of the row, the second source driver drives the data of the pixel P(i+1, j) to the second sub-data line of the j-th row, when coupled to the pixel P(i+2 , when the scanning line of j) is enabled, the scanning line coupled to the pixel P(i+3, j) is also enabled, and the data of the pixel P(i+3, j) is driven by the first source driver to For the first sub-data line in the j-th row, the second source driver drives the data of the pixel P(i+2, j) to the second sub-data line in the j-th row. 12. The display device as claimed in claim 11 , wherein after a gate start pulse signal is enabled, the gate driver sends M columns of scan signals to enable M columns of scan lines, and the scan signals are divided into M/2 times are sent out, each time a scan signal enabling two adjacent scan lines is sent out. 13. The display device according to claim 12, wherein when the i-th column and the i+1-th column scan line are enabled, the first sub-data line in the y-th row transmits data to the pixel P(i, y), And the second sub-data line in the yth row transmits data to the pixel P(i+1, y). When the i+2 and i+3th column scan lines are enabled, the first sub-data line in the y-th row transmits The data is sent to the pixel P(i+3, y), and the second sub-data line in the yth row transmits the data to the pixel P(i+2, y), and y is sequentially increased from 1 to N, and y is a positive integer. 14. A display device comprising: a timing controller; a gate driver coupled to the timing controller; a first source driver coupled to the timing controller; a second source driver coupled to the timing controller; and A display panel, coupled between the source driver and the gate driver, the display panel includes: M columns of scan lines are driven by the gate driver, where M is a positive integer; N rows of data lines, each row of data lines includes a first sub-data line and a second sub-data line, wherein N is a positive integer, the first sub-data line of each row is driven by the first source driver, each row The second sub-data line is driven by the second source driver; and M*N pixels are arranged in a matrix, and the pixels at the i-th column and j-th row are expressed as P(i, j), where i, j are integers, and 1≤i≤M, and 1≤j≤ N, and the first sub-data line of row j and the scan line of column i are coupled to the pixel P(i, j), the second sub-data line of row j and the scan line of column i+1 are coupled to the pixel P(i+1, j), the second sub-data line in row j and the scan line in column i+2 are coupled to pixel P(i+2, j), the first sub-data line in row j and the scan line in column i The i+3 column scanning line is coupled to the pixel P(i+3, j), wherein the timing controller controls the gate driver so that when the i-th column scanning line is activated, the i+1-th column scanning line is in a The gate clock is also activated, when the scan line in the i+2 column is activated, the scan line in the i+3 column is also activated in a gate clock, and the timing controller controls the first source driver at the same time Driving data to a first sub-data line of the data line and controlling the second source driver to simultaneously drive data to a second sub-data line of the data line. 15. The display device as claimed in claim 14 , wherein after a gate start pulse signal is enabled, the gate driver sends M columns of scan signals to enable M columns of scan lines, and the scan signals are divided into M/2 times are sent out, each time a scan signal enabling two adjacent scan lines is sent out. 16. A method for driving a control signal, suitable for a display panel, the display panel includes M columns of scan lines, N rows of data lines, and M*N pixels, each row of data lines includes a first sub-data line and a For the second sub-data line, all pixels are arranged in a matrix, and the pixel at the i-th column and the j-th row is represented as P(i, j), and the first sub-data line of the j-th row is coupled to the pixel P(i , j) and pixel P(i+3, j), the second sub-data line of j row is coupled to pixel P(i+1, j) and pixel P(i+2, j), wherein M, N , i, j are positive integers, and 1≤i≤M, and 1≤j≤N, the driving method of the control signal includes the following steps: After a grid start pulse signal is enabled, M columns of scanning signals are issued to enable M columns of scanning lines, and the scanning signals are divided into M/2 times to be issued, and each time the scanning signals are issued to enable two adjacent columns of scanning lines scan signal; and When the i-th column and the i+1th column scan line are enabled, the first sub-data line in the y-th row transmits data to the pixel P(i, y), and the second sub-data line in the y-th row transmits data to the pixel P (i+1, y), when the scan lines in the i+2 and i+3 columns are enabled, the first sub-data line in the y-th row transmits data to the pixel P(i+3, y), and the The second sub-data line in row y transmits data to the pixel P(i+2, y), and y is sequentially incremented from 1 to N, and y is a positive integer.

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