CN102723338A - Bi-polycrystal strain SiGe SOI (Silicon On Insulator) Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and preparation method thereof - Google Patents

Abstract

The invention discloses a bi-polycrystal strain SiGe SOI (Silicon On Insulator) Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and a preparation method of the device. The preparation process is as follows: growing an N type Si epitaxial layer on an SOI substrate to be taken as a collector region of a bipolar device, preparing a deep-trench isolator, then sequentially preparing base polycrystal, a base region and an emitter region to form a SiGe HBT (Heterojunction Bipolar Transistor) device; and growing strain SiGe material on the substrate, conducting photoetching on the active regions of an NMOS (N-Channel Metal Oxide Semiconductor) device and a PMOS (P-Channel Metal Oxide Semiconductor) device, injecting P type ions in the region of the NMOS device to prepare virtual grid, conducting self alignment to generate source-drain regions of the NMOS device and the PMOS device, removing the virtual grid, preparing a grid medium and wolfram (W) to form a grid electrode, conducting photoetching on a lead wire to form the bi-plycrystal strain SiGe SOI Bi CMOS integrated device and a circuit. Due to the preparation of the bi-plycrystal strain SiGe SOI Bi CMOS integrated circuit, the performances of a conventional analogue integrated circuit and a digital-analogue mixed integrated circuit are improved greatly.

Description

A kind of pair of polycrystalline strain SiGe SOI BiCMOS integrated device and preparation method

Technical field

The invention belongs to the semiconductor integrated circuit technical field, relate in particular to a kind of pair of polycrystalline, strain SiGe SOI BiCMOS integrated device and preparation method.

Background technology

The semiconductor integrated circuit technology is the core technology of high-tech and information industry; Having become the important symbol of weighing national science technical merit, overall national strength and a defense force, is that the microelectric technique of representative then is the key of semiconductor technology with the integrated circuit.Semiconductor industry is the infrastructural industries of country, and why it develops so soon, and except the huge contribution of technology to economic development itself, also application is relevant widely with it.

One of the founder of Intel (Intel) Gordon's mole (Gordon Moore) has proposed " Moore's Law " in nineteen sixty-five, and this theorem is pointed out: the transistor size on the IC chip, increased by 1 times in per approximately 18 months, and performance also promotes 1 times.For many years, the world semiconductor industry is being followed this law all the time and is constantly being advanced, and especially the Si basis set becomes circuit engineering, develops so far, and whole world number drops into technology with trillion dollars equipment, has made Si base technology form very powerful industry ability.Represent in the global information summit that February in 2004, the CEO Ke Laigebeiruite of Intel on the 23rd held in Tokyo; Moore's Law will be still effective at following 15 to 20 years, yet the technology dynamics that the promotion Moore's Law moves on is: constantly dwindle the chip feature size.At present, external 45nm technology has got into the large-scale production stage, and 32nm technical office is in the introduction period, and according to ITRS ITRS, next node is 22nm.

But, along with the continuation development of integrated circuit technique, the chip feature size is constantly dwindled, and in the microminiaturized process of Si chip manufacturing industry, is faced with the Material Physics attribute, manufacturing process technology, the challenge of the aspect limit such as device architecture.Such as when characteristic size is following less than 100nm because problems such as tunnelling leakage current and reliabilities, traditional gate dielectric material SiO ₂Can't satisfy the requirement of low-power consumption; The short-channel effect of nano-device and narrow-channel effect are obvious all the more, have had a strong impact on device performance; Traditional photoetching technique can't satisfy the lithographic accuracy that dwindles day by day.Therefore traditional Si base technology device more and more is difficult to satisfy the needs of design.

In order to satisfy the needs that further develop of semiconductor technology, carry out of a large amount of researchers aspect new construction, new material and new technology deep research, and obtained remarkable progress in the application in some field.These new constructions and new material are greatly improved to device performance, can satisfy integrated circuit technique and continue to meet the needs that " mole theorem " develops rapidly.

SOI (Silicon-On-Insulator, the silicon on the dielectric substrate) technology is to have introduced one deck between at the bottom of top layer silicon and the backing to bury oxide layer.Through on insulator, forming semiconductive thin film, the SOI material had body silicon incomparable advantage; Realize the dielectric isolation of components and parts in the integrated circuit, thoroughly eliminated the parasitic latch-up in the body silicon CMOS circuit; The integrated circuit that adopts this material to process has also that parasitic capacitance is little, integration density is high, speed is fast, technology is simple, short-channel effect is little and is specially adapted to advantage such as low-voltage and low-power dissipation circuit, therefore we can say that SOI might become the low pressure of deep-submicron, the mainstream technology of low power consumption integrated circuit.In addition, the SOI material also is used to make mems optical switch, as utilizes body silicon Machining Technology.

Therefore; Industrial quarters is when manufacturing large scale integrated circuit especially hybrid digital-analog integrated circuit at present; Still adopt Si BiCMOS or SiGe BiCMOS technology (Si BiCMOS is Si bipolar transistor BJT+Si CMOS, and SiGe BiCMOS is SiGe heterojunction bipolar transistor HBT+Si CMOS).

Summary of the invention

The objective of the invention is to be utilized in preparation strain SiGe planar channeling PMOS device, strain SiGe planar channeling nmos device and bipolar transistor on the substrate slice, constitute plane BiCMOS integrated device, to realize the optimization of device and performance of integrated circuits.

The object of the present invention is to provide a kind of pair of polycrystalline, strain SiGe SOI BiCMOS integrated device, nmos device is the strain SiGe planar channeling, and the PMOS device is the strain SiGe planar channeling, and the bipolar device base is the SiGe material.

Further, PMOS device conducting channel is the strain SiGe material, is compressive strain along channel direction.

Further, the PMOS device adopts quantum well structure.

Further, device substrate is the SOI material.

Further, the emitter of SiGe HBT device adopts polysilicon to contact with base stage.

Further, its preparation process adopts self-registered technology, and is the whole plane structure.

Another object of the present invention is to provide the preparation method of a kind of pair of polycrystalline, strain SiGe SOI BiCMOS integrated device, comprise the steps:

The first step, to choose oxidated layer thickness be 150 ~ 400nm, and upper strata Si thickness is 100～150nm, and N type doping content is 1 * 10 ¹⁶～1 * 10 ¹⁷Cm ^-3The SOI substrate slice;

Second goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the N type Si epitaxial loayer of 50～100nm on substrate, and as collector region, this layer doping content is 1 * 10 ¹⁶～1 * 10 ¹⁷Cm ^-3

The 3rd the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO ₂, the photoetching isolated area is utilized dry etch process, etches the deep trouth that the degree of depth is 2.5～3.5 μ m in isolated area, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO ₂And layer of sin, the deep trouth inner surface is all covered last deposit SiO ₂With filling up in the deep trouth, form deep trench isolation;

The 4th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 500 ~ 700nm at epitaxy Si laminar surface deposit one layer thickness ₂Layer, photoetching collector electrode contact zone window carries out phosphorus to substrate and injects, and making collector electrode contact zone doping content is 1 * 10 ¹⁹～1 * 10 ²⁰Cm ^-3, form collector contact area, again with substrate under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation;

The 5th step, etch away the oxide layer of substrate surface, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit two layer materials: ground floor is SiO ₂Layer, thickness is 20 ~ 40nm; The second layer is a P type Poly-Si layer, and thickness is 200 ~ 400nm, and doping content is 1 * 10 ²⁰～1 * 10 ²¹Cm ^-3

The 6th step, photoetching Poly-Si form outer base area, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit SiO ₂Layer, thickness is 200 ~ 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂

The 7th step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, deposit one SiN layer, thickness is 50 ~ 100nm, the photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window; Utilize chemical vapor deposition (CVD) method again, at 600～800 ℃, at substrate surface deposit one SiN layer, thickness is 10 ~ 20nm, and dry etching falls emitter window SiN, forms side wall;

The 8th the step, utilize wet etching, to SiO in the window ₂Layer carries out excessive erosion, forms the zone, base, utilizes chemical vapor deposition (CVD) method, at 600～750 ℃, and the regioselectivity growth SiGe base in the base, the Ge component is 15 ~ 25%, doping content is 5 * 10 ¹⁸~ 5 * 10 ¹⁹Cm ^-3, thickness is 20 ~ 60nm;

The 9th goes on foot, utilizes chemical vapor deposition (CVD) method; At 600～800 ℃; At substrate surface deposit Poly-Si, thickness is 200 ~ 400nm, again substrate is carried out phosphorus and injects; And utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter contact hole zone with outer surface, form emitter;

The tenth the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit SiO ₂Layer, under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation;

The 11 step, photoetching MOS active area; Utilize dry etch process; Etch the shallow slot that the degree of depth is 100～140nm at the MOS active area, utilize chemical vapor deposition (CVD) method, at 600～750 ℃; Continuous growth trilaminate material in this shallow slot: ground floor is that thickness is the N type Si resilient coating of 80～120nm, and this layer doping content is 5 ~ 5 * 10 ¹⁵Cm ^-3The second layer is that thickness is the N type SiGe epitaxial loayer of 10～15nm, and this layer Ge component is 15～30%, and doping content is 1～5 * 10 ¹⁶Cm ^-3The 3rd layer is that thickness is the intrinsic relaxation type Si cap layer of 3 ~ 5nm;

The 12 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, be the SiO of 300～500nm at extension material surface deposit one layer thickness ₂Layer; Photoetching PMOS device active region carries out N type ion to the PMOS device active region and injects, and makes its doping content reach 1～5 * 10 ¹⁷Cm ^-3Photoetching nmos device active area utilizes ion implantation technology that P type ion is carried out in the nmos device zone and injects, and forms nmos device active area P trap, and P trap doping content is 1～5 * 10 ¹⁷Cm ^-3

The 13 the step, utilize wet etching, etch away the surface SiO ₂Layer; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is that the SiN layer of 3～5nm is the intrinsic Poly-Si layer of 300～500nm as a gate medium and a layer thickness at substrate surface deposit one layer thickness; Photoetching Poly-Si grid and gate medium form the long pseudo-grid of 22～350nm;

The 14 goes on foot, utilizes ion to inject, and respectively nmos device active area and PMOS device active region is carried out N type and the injection of P type ion, forms N type lightly-doped source drain structure (N-LDD) and P type lightly-doped source drain structure (P-LDD), and doping content is 1～5 * 10 ¹⁸Cm ^-3

The 15 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, be the SiO of 5～15nm at substrate surface deposit one layer thickness ₂Layer utilizes dry etch process, etches away the SiO on surface ₂Layer, the SiO of reservation Poly-Si grid and gate medium side ₂, form side wall;

The 16 step, make the PMOS device active region by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of PMOS device; Make the nmos device active area by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of nmos device; Under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation with substrate;

The 17 the step, with chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO ₂, thickness is 300 ~ 500nm, utilizes chemico-mechanical polishing (CMP) technology, with SiO ₂Be planarized to gate surface;

The 18 step, utilizing wet etching that dummy grid is removed fully, stay the autoregistration impression that the grid on the oxide layer pile up, is the lanthana (La of 2 ~ 5nm at the substrate surface layer thickness of growing ₂O ₃); At substrate surface sputter layer of metal tungsten (W), utilize chemico-mechanical polishing (CMP) technology at last with tungsten (W) and lanthana (La beyond the area of grid ₂O ₃) remove;

The 19 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, superficial growth one deck SiO ₂Layer, and lithography fair lead;

The 20 step, metallization, photoetching lead-in wire; Form drain electrode, source electrode and the grid of MOS device and emitter, base stage, the collector electrode metal lead-in wire of SiGe HBT, constituting conducting channel is two polycrystalline, the strain SiGe SOI BiCMOS integrated device of 22～350nm.

Further, related maximum temperature is according to the 8th chemical vapor deposition (CVD) the technological temperature decision that go on foot in the 20 step in the strain SiGe SOI BiCMOS integrated device manufacture process of two polycrystalline among this preparation method, maximum temperature is smaller or equal to 800 ℃.

Further, wherein base thickness decides according to the epitaxy layer thickness of the 8th step SiGe, gets 20～60nm.

Another object of the present invention is to provide the preparation method of a kind of pair of polycrystalline, strain SiGe SOI BiCMOS integrated circuit, comprise the steps:

Step 1, epitaxially grown implementation method is:

(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO ₂, thickness is 150nm, upper layer of material is that doping content is 1 * 10 ¹⁶Cm ^-3N type Si, thickness is 100nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type epitaxy Si layer of 50nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 ¹⁶Cm ^-3

Step 2, the implementation method of deep trench isolation preparation is:

(2a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO ₂

(2b) photoetching isolated area is utilized dry etch process, etches the deep trouth that the degree of depth is 2.5 μ m in isolated area;

(2c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at deep trouth inner surface deposit SiO ₂Layer all covers the deep trouth inner surface;

(2d) utilize chemical vapor deposition (CVD) method, at 600 ℃, SiO in deep trouth ₂The layer of deposit layer of sin more all covers the deep trouth inner surface on the layer;

(2e) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ ₂, utilize chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form deep trench isolation;

Step 3, the implementation method of collector electrode contact zone preparation is:

(3a) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the oxide layer of 500nm at epitaxy Si laminar surface deposit one layer thickness;

(3b) photoetching collector electrode contact zone window;

(3c) substrate is carried out phosphorus and inject, making collector electrode contact zone doping content is 1 * 10 ¹⁹Cm ^-3, form collector contact area;

(3d) with substrate under 950 ℃ of temperature, annealing 15s, carry out impurity activation;

Step 4, the implementation method of base contact preparation is:

(4a) etch away the substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one SiO ₂Layer, thickness is 20nm;

(4b) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one P type Poly-Si layer, as the contact zone, base, this layer thickness is 200nm, and doping content is 1 * 10 ²⁰Cm ^-3

(4c) photoetching Poly-Si forms outer base area, at 600 ℃, at substrate surface deposit SiO ₂Layer, thickness is 200nm, utilizes the method for chemico-mechanical polishing (CMP), removes the SiO on Poly-Si surface ₂

(4d) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one SiN layer, thickness is 50nm;

(4e) photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window;

(4f) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit layer of sin layer, thickness is 10nm;

Step 5, the implementation method of base material preparation is:

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5b) utilize wet etching, to SiO in the window ₂Layer carries out excessive erosion, forms the zone, base;

(5c) utilize chemical vapor deposition (CVD) method, at 600 ℃, the regioselectivity growth SiGe base in the base, the Ge component is 15%, doping content is 5 * 10 ¹⁸Cm ^-3, thickness is 20nm;

Step 6, the implementation method of emitter region preparation is:

(6a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit Poly-Si, thickness is 200nm;

(6b) substrate is carried out phosphorus and inject, and utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter contact hole zone, form emitter with outer surface;

(6c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO ₂Layer, the 120s that under 950 ℃ of temperature, anneals, activator impurity;

Step 7, the implementation method of strain SiGe material preparation is:

(7a) photoetching MOS active area;

(7b) utilize dry etch process, etch the shallow slot that the degree of depth is 100nm at the MOS active area;

(7c) utilize chemical vapor deposition (CVD) method, at 600 ℃, growth thickness is the N type Si resilient coating of 80nm in shallow slot, and this layer doping content is 1 * 10 ¹⁵Cm ^-3

(7d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the N type SiGe epitaxial loayer of 10nm at the substrate surface growth thickness, and this layer Ge component is 15%, and doping content is 1 * 10 ¹⁶Cm ^-3

(7e) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the intrinsic relaxation type Si cap layer of 3nm at the substrate surface growth thickness;

Step 8, the implementation method that nmos device and PMOS device form is:

(8a) utilize chemical vapor deposition (CVD) method, at 600 ℃, the SiO of growth one deck 300nm on substrate ₂

(8b) photoetching PMOS device active region carries out N type ion to the PMOS device active region and injects, and makes its doping content reach 1 * 10 ¹⁷Cm ^-3

(8c) photoetching nmos device active area utilizes ion implantation technology that P type ion is carried out in the nmos device zone and injects, and forms nmos device active area P trap, and P trap doping content is 1 * 10 ¹⁷Cm ^-3

(8d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the SiN layer of 3nm at superficial growth one layer thickness;

(8e) utilize chemical vapor deposition (CVD) method, at 600 ℃, the polysilicon of growth one deck 300nm on the SiN layer;

(8f) photoetching Poly-Si grid and gate medium form the long pseudo-grid of 22nm;

(8g) photoetching nmos device active area carries out N type ion to the nmos device active area and injects, and forms N type lightly-doped source drain structure (N-LDD), and doping content is 1 * 10 ¹⁸Cm ^-3

(8h) photoetching PMOS device active region carries out P type ion to the PMOS device active region and injects, and forms P type lightly-doped source drain structure (P-LDD), and doping content is 1 * 10 ¹⁸Cm ^-3

(8i) at substrate surface, utilize chemical vapor deposition (CVD) method, at 600 ℃, growth one deck SiO ₂, thickness is 10nm, utilizes the dry etch process photoetching to fall unnecessary SiO subsequently ₂, keep gate lateral wall SiO ₂, form side wall;

(8j) make the PMOS device active region by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of PMOS device;

(8k) make the nmos device active area by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of nmos device;

(8l) with substrate under 950 ℃ of temperature, annealing 120s, carry out impurity activation;

Step 9, the implementation method of grid preparation is:

(9a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO ₂Layer, SiO ₂Thickness is 300nm thickness;

(9b) utilize chemico-mechanical polishing (CMP) method, the surface is planarized to gate level;

(9c) utilize wet etching that dummy grid is removed fully, stay the autoregistration impression that the grid on the oxide layer pile up;

Be the lanthana (La of 2nm (9d) at the substrate surface layer thickness of growing ₂O ₃);

(9e) at substrate surface sputter layer of metal tungsten (W);

(9f) utilize chemico-mechanical polishing (CMP) technology with tungsten (W) and lanthana (La beyond the area of grid ₂O ₃) remove;

Step 10, the implementation method that constitutes the BiCMOS integrated circuit is:

(10a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at superficial growth one deck SiO ₂Layer;

(10b) lithography fair lead;

(10c) metallization;

(10d) photoetching lead-in wire; Form MOS device drain metal lead wire, source metal lead-in wire and gate metal lead-in wire; Bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, constituting the MOS conducting channel is two polycrystalline, strain SiGe SOI BiCMOS integrated device and the circuit of 22nm.

The present invention has following advantage:

1. adopt the SOI substrate in two polycrystalline of the present invention's preparation, the strain SiGe SOI BiCMOS integrated device, reduced the power consumption and the cut-in voltage of device and circuit, improved the reliability of device and circuit;

2. adopted lightly-doped source leakage (LDD) structure in two polycrystalline of the present invention's preparation, the strain SiGe SOI BiCMOS integrated device structure, suppressed the influence of hot carrier effectively device performance;

3. two polycrystalline, the strain SiGe SOI BiCMOS integrated device of the present invention's preparation have all adopted quantum well structure in the PMOS device architecture; Can be effectively hole confinement in the SiGe layer; Reduce interface scattering, improved the electric property such as frequency, current driving ability of device;

4. two polycrystalline, the strain SiGe SOI BiCMOS integrated device of the present invention's preparation have adopted high-K gate dielectric, have improved the grid-control ability of MOS device, have strengthened the electric property of device;

5. to prepare the maximum temperature that relates in two polycrystalline, the strain SiGe SOI BiCMOS integrated device process be 800 ℃ in the present invention; Be lower than the technological temperature that causes strain SiGe channel stress relaxation; Therefore this preparation method can keep strain SiGe channel stress effectively, improves the performance of integrated circuit;

6. in two polycrystalline of the present invention's preparation, the strain SiGe SOI BiCMOS integrated device; When preparation nmos device and PMOS device gate electrode, adopted metal gate mosaic technology (damascene process); Used tungsten (W) as metal electrode in this technology; Reduce the resistance of gate electrode, improved the flexibility and the reliability of designs;

7. two polycrystalline, the strain SiGe SOI BiCMOS integrated device of the present invention's preparation in the preparation process, adopt fully self aligned technology, have reduced dead resistance and electric capacity effectively, have improved the electric current and the frequency characteristic of device;

8. two polycrystalline, the strain SiGe SOI BiCMOS integrated device of the present invention preparation, the emitter of SiGeHBT adopts polycrystalline with base stage, can obtain the junction depth that approaches, reduces the parasitic parameter of device, the raising device performance;

9. in two polycrystalline of the present invention's preparation, the strain SiGe SOI BiCMOS integrated device, bipolar device adopts the SOI substrate, and collector region thickness is thin than traditional devices; Therefore; There is collector region effect extending transversely in this device, and can form two dimensional electric field at collector region, thereby has improved the reverse breakdown voltage and the Early voltage of this device; Under identical breakdown characteristics, have the characteristic frequency more excellent than traditional devices.

Description of drawings

Fig. 1 is provided by the invention pair of polycrystalline, strain SiGe SOI BiCMOS integrated device and circuit preparation method's realization flow figure.

Embodiment

In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.

The embodiment of the invention provides a kind of pair of polycrystalline, strain SiGe SOI BiCMOS integrated device, and nmos device is the strain SiGe planar channeling, and the PMOS device is the strain SiGe planar channeling, and the bipolar device base is the SiGe material.

As a prioritization scheme of the embodiment of the invention, PMOS device conducting channel is the strain SiGe material, is compressive strain along channel direction.

As a prioritization scheme of the embodiment of the invention, the PMOS device adopts quantum well structure.

As a prioritization scheme of the embodiment of the invention, device substrate is the SOI material.

As a prioritization scheme of the embodiment of the invention, the emitter of SiGeHBT device adopts polysilicon to contact with base stage.

As a prioritization scheme of the embodiment of the invention, its preparation process adopts self-registered technology, and is the whole plane structure.

Following with reference to accompanying drawing 1, the technological process that the present invention is prepared two polycrystalline, strain SiGe SOI BiCMOS integrated device and the circuit of 22～350nm channel length describes in further detail.

Embodiment 1: the preparation channel length is two polycrystalline, the strain SiGe SOI BiCMOS integrated device of 22nm, and concrete steps are following:

Step 1, epitaxial growth.

(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO ₂, thickness is 150nm, upper layer of material is that doping content is 1 * 10 ¹⁶Cm ^-3N type Si, thickness is 100nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type epitaxy Si layer of 50nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 ¹⁶Cm ^-3

Step 2, the deep trench isolation preparation.

(2a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO ₂

(2b) photoetching isolated area is utilized dry etch process, etches the deep trouth that the degree of depth is 2.5 μ m in isolated area;

(2c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at deep trouth inner surface deposit SiO ₂Layer all covers the deep trouth inner surface;

(2d) utilize chemical vapor deposition (CVD) method, at 600 ℃, SiO in deep trouth ₂The layer of deposit layer of sin more all covers the deep trouth inner surface on the layer;

(2e) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ ₂, utilize chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form deep trench isolation.

Step 3, the preparation of collector electrode contact zone.

(3a) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the oxide layer of 500nm at epitaxy Si laminar surface deposit one layer thickness;

(3b) photoetching collector electrode contact zone window;

(3c) substrate is carried out phosphorus and inject, making collector electrode contact zone doping content is 1 * 10 ¹⁹Cm ^-3, form collector contact area;

(3d) with substrate under 950 ℃ of temperature, annealing 15s, carry out impurity activation.

Step 4, the base contact preparation.

(4a) etch away the substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one SiO ₂Layer, thickness is 20nm;

(4b) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one P type Poly-Si layer, as the contact zone, base, this layer thickness is 200nm, and doping content is 1 * 10 ²⁰Cm ^-3

(4c) photoetching Poly-Si forms outer base area, at 600 ℃, at substrate surface deposit SiO ₂Layer, thickness is 200nm, utilizes the method for chemico-mechanical polishing (CMP), removes the SiO on Poly-Si surface ₂

(4d) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one SiN layer, thickness is 50nm;

(4e) photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window;

(4f) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit layer of sin layer, thickness is 10nm.

Step 5, the base material preparation.

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5b) utilize wet etching, to SiO in the window ₂Layer carries out excessive erosion, forms the zone, base;

(5c) utilize chemical vapor deposition (CVD) method, at 600 ℃, the regioselectivity growth SiGe base in the base, the Ge component is 15%, doping content is 5 * 10 ¹⁸Cm ^-3, thickness is 20nm.

Step 6, the emitter region preparation.

(6a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit Poly-Si, thickness is 200nm;

(6b) substrate is carried out phosphorus and inject, and utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter contact hole zone, form emitter with outer surface;

(6c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO ₂Layer, the 120s that under 950 ℃ of temperature, anneals, activator impurity.

Step 7, the strain SiGe material preparation.

(7a) photoetching MOS active area;

(7b) utilize dry etch process, etch the shallow slot that the degree of depth is 100nm at the MOS active area;

(7c) utilize chemical vapor deposition (CVD) method, at 600 ℃, growth thickness is the N type Si resilient coating of 80nm in shallow slot, and this layer doping content is 1 * 10 ¹⁵Cm ^-3

(7d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the N type SiGe epitaxial loayer of 10nm at the substrate surface growth thickness, and this layer Ge component is 15%, and doping content is 1 * 10 ¹⁶Cm ^-3

(7e) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the intrinsic relaxation type Si cap layer of 3nm at the substrate surface growth thickness.

Step 8, nmos device and PMOS device form.

(8a) utilize chemical vapor deposition (CVD) method, at 600 ℃, the SiO of growth one deck 300nm on substrate ₂

(8b) photoetching PMOS device active region carries out N type ion to the PMOS device active region and injects, and makes its doping content reach 1 * 10 ¹⁷Cm ^-3

(8c) photoetching nmos device active area utilizes ion implantation technology that P type ion is carried out in the nmos device zone and injects, and forms nmos device active area P trap, and P trap doping content is 1 * 10 ¹⁷Cm ^-3

(8d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the SiN layer of 3nm at superficial growth one layer thickness;

(8e) utilize chemical vapor deposition (CVD) method, at 600 ℃, the polysilicon of growth one deck 300nm on the SiN layer;

(8f) photoetching Poly-Si grid and gate medium form the long pseudo-grid of 22nm;

(8g) photoetching nmos device active area carries out N type ion to the nmos device active area and injects, and forms N type lightly-doped source drain structure (N-LDD), and doping content is 1 * 10 ¹⁸Cm ^-3

(8h) photoetching PMOS device active region carries out P type ion to the PMOS device active region and injects, and forms P type lightly-doped source drain structure (P-LDD), and doping content is 1 * 10 ¹⁸Cm ^-3

(8i) at substrate surface, utilize chemical vapor deposition (CVD) method, at 600 ℃, growth one deck SiO ₂, thickness is 10nm, utilizes the dry etch process photoetching to fall unnecessary SiO subsequently ₂, keep gate lateral wall SiO ₂, form side wall;

(8j) make the PMOS device active region by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of PMOS device;

(8k) make the nmos device active area by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of nmos device;

(8l) with substrate under 950 ℃ of temperature, annealing 120s, carry out impurity activation.

Step 9, the grid preparation.

(9a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO ₂Layer, SiO ₂Thickness is 300nm thickness;

(9b) utilize chemico-mechanical polishing (CMP) method, the surface is planarized to gate level;

(9c) utilize wet etching that dummy grid is removed fully, stay the autoregistration impression that the grid on the oxide layer pile up;

Be the lanthana (La of 2nm (9d) at the substrate surface layer thickness of growing ₂O ₃);

(9e) at substrate surface sputter layer of metal tungsten (W);

(9f) utilize chemico-mechanical polishing (CMP) technology with tungsten (W) and lanthana (La beyond the area of grid ₂O ₃) remove.

Step 10 constitutes the BiCMOS integrated circuit.

(10a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at superficial growth one deck SiO ₂Layer;

(10b) lithography fair lead;

(10c) metallization;

(10d) photoetching lead-in wire; Form MOS device drain metal lead wire, source metal lead-in wire and gate metal lead-in wire; Bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, constituting the MOS conducting channel is two polycrystalline, strain SiGe SOI BiCMOS integrated device and the circuit of 22nm.

Embodiment 2: the preparation channel length is two polycrystalline, the strain SiGe SOI BiCMOS integrated device of 130nm, and concrete steps are following:

Step 1, epitaxial growth.

(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO ₂, thickness is 300nm, upper layer of material is that doping content is 5 * 10 ¹⁶Cm ^-3N type Si, thickness is 120nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the N type epitaxy Si layer of 80nm on the Si material of upper strata, and as collector region, this layer doping content is 5 * 10 ¹⁶Cm ^-3

Step 2, the deep trench isolation preparation.

(2a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiO ₂

(2b) photoetching isolated area is utilized dry etch process, etches the deep trouth that the degree of depth is 3 μ m in isolated area;

(2c) utilize chemical vapor deposition (CVD) method, at 700 ℃, at deep trouth inner surface deposit SiO ₂Layer all covers the deep trouth inner surface;

(2d) utilize chemical vapor deposition (CVD) method, at 700 ℃, SiO in deep trouth ₂The layer of deposit layer of sin more all covers the deep trouth inner surface on the layer;

(2e) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 700 ℃ ₂, utilize chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form deep trench isolation.

Step 3, the preparation of collector electrode contact zone.

(3a) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the oxide layer of 600nm at epitaxy Si laminar surface deposit one layer thickness;

(3b) photoetching collector electrode contact zone window;

(3c) substrate is carried out phosphorus and inject, making collector electrode contact zone doping content is 5 * 10 ¹⁹Cm ^-3, form collector contact area;

(3d) with substrate under 1000 ℃ of temperature, annealing 60s, carry out impurity activation.

Step 4, the base contact preparation.

(4a) etch away the substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one SiO ₂Layer, thickness is 30nm;

(4b) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one P type Poly-Si layer, as the contact zone, base, this layer thickness is 300nm, and doping content is 5 * 10 ²⁰Cm ^-3

(4c) photoetching Poly-Si forms outer base area, at 700 ℃, at substrate surface deposit SiO ₂Layer, thickness is 300nm, utilizes the method for chemico-mechanical polishing (CMP), removes the SiO on Poly-Si surface ₂

(4d) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one SiN layer, thickness is 80nm;

(4e) photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window;

(4f) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit layer of sin layer, thickness is 15nm.

Step 5, the base material preparation.

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5b) utilize wet etching, to SiO in the window ₂Layer carries out excessive erosion, forms the zone, base;

(5c) utilize chemical vapor deposition (CVD) method, at 700 ℃, the regioselectivity growth SiGe base in the base, the Ge component is 20%, doping content is 1 * 10 ¹⁹Cm ^-3, thickness is 40nm.

Step 6, the emitter region preparation.

(6a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit Poly-Si, thickness is 300nm;

(6b) substrate is carried out phosphorus and inject, and utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter contact hole zone, form emitter with outer surface;

(6c) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit SiO ₂Layer, the 60s that under 1000 ℃ of temperature, anneals, activator impurity.

Step 7, the strain SiGe material preparation.

(7a) photoetching MOS active area;

(7b) utilize dry etch process, etch the shallow slot that the degree of depth is 100nm at the MOS active area;

(7c) utilize chemical vapor deposition (CVD) method, at 700 ℃, growth thickness is the N type Si resilient coating of 100nm in shallow slot, and this layer doping content is 3 * 10 ¹⁵Cm ^-3

(7d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the N type SiGe epitaxial loayer of 12nm at the substrate surface growth thickness, and this layer Ge component is 20%, and doping content is 3 * 10 ¹⁶Cm ^-3

(7e) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is the intrinsic relaxation type Si cap layer of 4nm at the substrate surface growth thickness.

Step 8, nmos device and PMOS device form.

(8a) utilize chemical vapor deposition (CVD) method, at 700 ℃, the SiO of growth one deck 400nm on substrate ₂

(8b) photoetching PMOS device active region carries out N type ion to the PMOS device active region and injects, and makes its doping content reach 3 * 10 ¹⁷Cm ^-3

(8c) photoetching nmos device active area utilizes ion implantation technology that P type ion is carried out in the nmos device zone and injects, and forms nmos device active area P trap, and P trap doping content is 3 * 10 ¹⁷Cm ^-3

(8d) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is the SiN layer of 4nm at superficial growth one layer thickness;

(8e) utilize chemical vapor deposition (CVD) method, at 700 ℃, the polysilicon of growth one deck 400nm on the SiN layer;

(8f) photoetching Poly-Si grid and gate medium form the long pseudo-grid of 130nm;

(8g) photoetching nmos device active area carries out N type ion to the nmos device active area and injects, and forms N type lightly-doped source drain structure (N-LDD), and doping content is 3 * 10 ¹⁸Cm ^-3

(8h) photoetching PMOS device active region carries out P type ion to the PMOS device active region and injects, and forms P type lightly-doped source drain structure (P-LDD), and doping content is 3 * 10 ¹⁸Cm ^-3

(8i) at substrate surface, utilize chemical vapor deposition (CVD) method, at 700 ℃, growth one deck SiO ₂, thickness is 15nm, utilizes the dry etch process photoetching to fall unnecessary SiO subsequently ₂, keep gate lateral wall SiO ₂, form side wall; Three

(8j) make the PMOS device active region by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of PMOS device;

(8k) make the nmos device active area by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of nmos device;

(8l) with substrate under 1000 ℃ of temperature, annealing 60s, carry out impurity activation.

Step 9, the grid preparation.

(9a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiO ₂Layer, SiO ₂Thickness is 400nm thickness;

(9b) utilize chemico-mechanical polishing (CMP) method, the surface is planarized to gate level;

(9c) utilize wet etching that dummy grid is removed fully, stay the autoregistration impression that the grid on the oxide layer pile up;

Be the lanthana (La of 4nm (9d) at the substrate surface layer thickness of growing ₂O ₃);

(9e) at substrate surface sputter layer of metal tungsten (W);

(9f) utilize chemico-mechanical polishing (CMP) technology with tungsten (W) and lanthana (La beyond the area of grid ₂O ₃) remove.

Step 10 constitutes the BiCMOS integrated circuit.

(10a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at superficial growth one deck SiO ₂Layer;

(10b) lithography fair lead;

(10c) metallization;

(10d) photoetching lead-in wire; Form MOS device drain metal lead wire, source metal lead-in wire and gate metal lead-in wire; Bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, constituting the MOS conducting channel is two polycrystalline, strain SiGe SOI BiCMOS integrated device and the circuit of 130nm.

Embodiment 3: the preparation channel length is two polycrystalline, the strain SiGe SOI BiCMOS integrated device of 350nm, and concrete steps are following:

Step 1, epitaxial growth.

(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO ₂, thickness is 400nm, upper layer of material is that doping content is 1 * 10 ¹⁷Cm ^-3N type Si, thickness is 150nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the N type epitaxy Si layer of 100nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 ¹⁷Cm ^-3

Step 2, the deep trench isolation preparation.

(2a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO ₂

(2b) photoetching isolated area is utilized dry etch process, etches the deep trouth that the degree of depth is 3.5 μ m in isolated area;

(2c) utilize chemical vapor deposition (CVD) method, at 800 ℃, at deep trouth inner surface deposit SiO ₂Layer all covers the deep trouth inner surface;

(2d) utilize chemical vapor deposition (CVD) method, at 800 ℃, SiO in deep trouth ₂The layer of deposit layer of sin more all covers the deep trouth inner surface on the layer;

(2e) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 800 ℃ ₂, utilize chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form deep trench isolation.

Step 3, the preparation of collector electrode contact zone.

(3a) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the oxide layer of 700nm at epitaxy Si laminar surface deposit one layer thickness;

(3b) photoetching collector electrode contact zone window;

(3c) substrate is carried out phosphorus and inject, making collector electrode contact zone doping content is 1 * 10 ²⁰Cm ^-3, form collector contact area;

(3d) with substrate under 1100 ℃ of temperature, annealing 15s, carry out impurity activation.

Step 4, the base contact preparation.

(4a) etch away the substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one SiO ₂Layer, thickness is 40nm;

(4b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one P type Poly-Si layer, as the contact zone, base, this layer thickness is 400nm, and doping content is 1 * 10 ²¹Cm ^-3

(4c) photoetching Poly-Si forms outer base area, at 800 ℃, at substrate surface deposit SiO ₂Layer, thickness is 400nm, utilizes the method for chemico-mechanical polishing (CMP), removes the SiO on Poly-Si surface ₂

(4d) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one SiN layer, thickness is 100nm;

(4e) photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window;

(4f) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit layer of sin layer, thickness is 20nm.

Step 5, the base material preparation.

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5b) utilize wet etching, to SiO in the window ₂Layer carries out excessive erosion, forms the zone, base;

(5c) utilize chemical vapor deposition (CVD) method, at 750 ℃, the regioselectivity growth SiGe base in the base, the Ge component is 25%, doping content is 5 * 10 ¹⁹Cm ^-3, thickness is 60nm.

Step 6, the emitter region preparation.

(6a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit Poly-Si, thickness is 400nm;

(6b) substrate is carried out phosphorus and inject, and utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter contact hole zone, form emitter with outer surface;

(6c) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO ₂Layer, the 15s that under 1100 ℃ of temperature, anneals, activator impurity.

Step 7, the strain SiGe material preparation.

(7a) photoetching MOS active area;

(7b) utilize dry etch process, etch the shallow slot that the degree of depth is 100nm at the MOS active area;

(7c) utilize chemical vapor deposition (CVD) method, at 750 ℃, growth thickness is the N type Si resilient coating of 120nm in shallow slot, and this layer doping content is 5 * 10 ¹⁵Cm ^-3

(7d) utilizing chemical vapor deposition (CVD) method, at 750 ℃, is the N type SiGe epitaxial loayer of 15nm at the substrate surface growth thickness, and this layer Ge component is 30%, and doping content is 5 * 10 ¹⁶Cm ^-3

(7e) utilizing chemical vapor deposition (CVD) method, at 750 ℃, is the intrinsic relaxation type Si cap layer of 5nm at the substrate surface growth thickness.

Step 8, nmos device and PMOS device form.

(8a) utilize chemical vapor deposition (CVD) method, at 800 ℃, the SiO of growth one deck 500nm on substrate ₂

(8b) photoetching PMOS device active region carries out N type ion to the PMOS device active region and injects, and makes its doping content reach 5 * 10 ¹⁷Cm ^-3

(8c) photoetching nmos device active area utilizes ion implantation technology that P type ion is carried out in the nmos device zone and injects, and forms nmos device active area P trap, and P trap doping content is 5 * 10 ¹⁷Cm ^-3

(8d) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is the SiN layer of 5nm at superficial growth one layer thickness;

(8e) utilize chemical vapor deposition (CVD) method, at 800 ℃, the polysilicon of growth one deck 500nm on the SiN layer;

(8f) photoetching Poly-Si grid and gate medium form the long pseudo-grid of 350nm;

(8g) photoetching nmos device active area carries out N type ion to the nmos device active area and injects, and forms N type lightly-doped source drain structure (N-LDD), and doping content is 5 * 10 ¹⁸Cm ^-3

(8h) photoetching PMOS device active region carries out P type ion to the PMOS device active region and injects, and forms P type lightly-doped source drain structure (P-LDD), and doping content is 5 * 10 ¹⁸Cm ^-3

(8i) at substrate surface, utilize chemical vapor deposition (CVD) method, at 800 ℃, growth one deck SiO ₂, thickness is 5nm, utilizes the dry etch process photoetching to fall unnecessary SiO subsequently ₂, keep gate lateral wall SiO ₂, form side wall;

(8j) make the PMOS device active region by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of PMOS device;

(8k) make the nmos device active area by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of nmos device;

(8l) with substrate under 1100 ℃ of temperature, annealing 15s, carry out impurity activation.

Step 9, the grid preparation.

(9a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO ₂Layer, SiO ₂Thickness is 500nm thickness;

(9b) utilize chemico-mechanical polishing (CMP) method, the surface is planarized to gate level;

(9c) utilize wet etching that dummy grid is removed fully, stay the autoregistration impression that the grid on the oxide layer pile up;

Be the lanthana (La of 5nm (9d) at the substrate surface layer thickness of growing ₂O ₃);

(9e) at substrate surface sputter layer of metal tungsten (W);

(9f) utilize chemico-mechanical polishing (CMP) technology with tungsten (W) and lanthana (La beyond the area of grid ₂O ₃) remove.

Step 10 constitutes the BiCMOS integrated circuit.

(10a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at superficial growth one deck SiO ₂Layer;

(10b) lithography fair lead;

(10c) metallization;

(10d) photoetching lead-in wire; Form MOS device drain metal lead wire, source metal lead-in wire and gate metal lead-in wire; Bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, constituting the MOS conducting channel is two polycrystalline, strain SiGe SOI BiCMOS integrated device and the circuit of 350nm.

Two polycrystalline that the embodiment of the invention provides, strain SiGe SOI BiCMOS integrated device preparation method have following advantage:

1. adopt the SOI substrate in two polycrystalline of the present invention's preparation, the strain SiGe SOI BiCMOS integrated device, reduced the power consumption and the cut-in voltage of device and circuit, improved the reliability of device and circuit;

2. adopted lightly-doped source leakage (LDD) structure in two polycrystalline of the present invention's preparation, the strain SiGe SOI BiCMOS integrated device structure, suppressed the influence of hot carrier effectively device performance;

3. two polycrystalline, the strain SiGe SOI BiCMOS integrated device of the present invention's preparation have all adopted quantum well structure in the PMOS device architecture; Can be effectively hole confinement in the SiGe layer; Reduce interface scattering, improved the electric property such as frequency, current driving ability of device;

4. two polycrystalline, the strain SiGe SOI BiCMOS integrated device of the present invention's preparation have adopted high-K gate dielectric, have improved the grid-control ability of MOS device, have strengthened the electric property of device;

5. to prepare the maximum temperature that relates in two polycrystalline, the strain SiGe SOI BiCMOS integrated device process be 800 ℃ in the present invention; Be lower than the technological temperature that causes strain SiGe channel stress relaxation; Therefore this preparation method can keep strain SiGe channel stress effectively, improves the performance of integrated circuit;

6. in two polycrystalline of the present invention's preparation, the strain SiGe SOI BiCMOS integrated device; When preparation nmos device and PMOS device gate electrode, adopted the metal gate mosaic technology; Used tungsten (W) as metal electrode in this technology; Reduce the resistance of gate electrode, improved the flexibility and the reliability of designs;

7. two polycrystalline, the strain SiGe SOI BiCMOS integrated device of the present invention's preparation in the preparation process, adopt fully self aligned technology, have reduced dead resistance and electric capacity effectively, have improved the electric current and the frequency characteristic of device;

8. two polycrystalline, the strain SiGe SOI BiCMOS integrated device of the present invention preparation, the emitter of SiGeHBT adopts polycrystalline with base stage, can obtain the junction depth that approaches, reduces the parasitic parameter of device, the raising device performance;

9. in two polycrystalline of the present invention preparation, the strain SiGe SOI BiCMOS integrated device, bipolar device employing SOI substrate, collector region thickness thin than traditional devices; Therefore; There is collector region effect extending transversely in this device, and can form two dimensional electric field at collector region, thereby has improved the reverse breakdown voltage and the Early voltage of this device; Under identical breakdown characteristics, have the characteristic frequency more excellent than traditional devices.

The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. a two polycrystalline strain SiGe SOI BiCMOS integrated device is characterized in that nmos device is the strain SiGe planar channeling, and the PMOS device is the strain SiGe planar channeling, and the bipolar device base is the SiGe material.

2. according to claim 1 pair of polycrystalline strain SiGe SOI BiCMOS integrated device is characterized in that PMOS device conducting channel is the strain SiGe material, is compressive strain along channel direction.

3. according to claim 1 pair of polycrystalline strain SiGe SOI BiCMOS integrated device is characterized in that, the PMOS device adopts quantum well structure.

4. according to claim 1 pair of polycrystalline strain SiGe SOI BiCMOS integrated device is characterized in that device substrate is the SOI material.

5. according to claim 1 pair of polycrystalline strain SiGe SOI BiCMOS integrated device is characterized in that, the emitter of SiGe HBT device adopts polysilicon to contact with base stage.

6. according to claim 1 pair of polycrystalline strain SiGe SOI BiCMOS integrated device is characterized in that, its preparation process adopts self-registered technology, and is planar structure.

7. the preparation method of two polycrystalline strain SiGe SOI BiCMOS integrated devices is characterized in that, comprises the steps:

The first step, to choose oxidated layer thickness be 150 ~ 400nm, and upper strata Si thickness is 100～150nm, and N type doping content is 1 * 10 ¹⁶～1 * 10 ¹⁷Cm ^-3The SOI substrate slice;

Second goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the N type Si epitaxial loayer of 50～100nm on substrate, and as collector region, this layer doping content is 1 * 10 ¹⁶～1 * 10 ¹⁷Cm ^-3

The 3rd the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO ₂, the photoetching isolated area is utilized dry etch process, etches the deep trouth that the degree of depth is 2.5～3.5 μ m in isolated area, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO ₂And layer of sin, the deep trouth inner surface is all covered last deposit SiO ₂With filling up in the deep trouth, form deep trench isolation;

The 4th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 500 ~ 700nm at epitaxy Si laminar surface deposit one layer thickness ₂Layer, photoetching collector electrode contact zone window carries out phosphorus to substrate and injects, and making collector electrode contact zone doping content is 1 * 10 ¹⁹～1 * 10 ²⁰Cm ^-3, form collector contact area, again with substrate under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation;

The 5th step, etch away the oxide layer of substrate surface, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit two layer materials: ground floor is SiO ₂Layer, thickness is 20 ~ 40nm; The second layer is a P type Poly-Si layer, and thickness is 200 ~ 400nm, and doping content is 1 * 10 ²⁰～1 * 10 ²¹Cm ^-3

The 6th step, photoetching Poly-Si form outer base area, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit SiO ₂Layer, thickness is 200 ~ 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂

The 7th step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, deposit one SiN layer, thickness is 50 ~ 100nm, the photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window; Utilize chemical vapor deposition (CVD) method again, at 600～800 ℃, at substrate surface deposit one SiN layer, thickness is 10 ~ 20nm, and dry etching falls emitter window SiN, forms side wall;

The 8th the step, utilize wet etching, to SiO in the window ₂Layer carries out excessive erosion, forms the zone, base, utilizes chemical vapor deposition (CVD) method, at 600～750 ℃, and the regioselectivity growth SiGe base in the base, the Ge component is 15 ~ 25%, doping content is 5 * 10 ¹⁸~ 5 * 10 ¹⁹Cm ^-3, thickness is 20 ~ 60nm;

The 9th goes on foot, utilizes chemical vapor deposition (CVD) method; At 600～800 ℃; At substrate surface deposit Poly-Si, thickness is 200 ~ 400nm, again substrate is carried out phosphorus and injects; And utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter contact hole zone with outer surface, form emitter;

The tenth the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit SiO ₂Layer, under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation;

The 11 step, photoetching MOS active area; Utilize dry etch process; Etch the shallow slot that the degree of depth is 100～140nm at the MOS active area, utilize chemical vapor deposition (CVD) method, at 600～750 ℃; Continuous growth trilaminate material in this shallow slot: ground floor is that thickness is the N type Si resilient coating of 80～120nm, and this layer doping content is 5 ~ 5 * 10 ¹⁵Cm ^-3The second layer is that thickness is the N type SiGe epitaxial loayer of 10～15nm, and this layer Ge component is 15～30%, and doping content is 1～5 * 10 ¹⁶Cm ^-3The 3rd layer is that thickness is the intrinsic relaxation type Si cap layer of 3 ~ 5nm;

The 12 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, be the SiO of 300～500nm at extension material surface deposit one layer thickness ₂Layer; Photoetching PMOS device active region carries out N type ion to the PMOS device active region and injects, and makes its doping content reach 1～5 * 10 ¹⁷Cm ^-3Photoetching nmos device active area utilizes ion implantation technology that P type ion is carried out in the nmos device zone and injects, and forms nmos device active area P trap, and P trap doping content is 1～5 * 10 ¹⁷Cm ^-3

The 13 the step, utilize wet etching, etch away the surface SiO ₂Layer; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is that the SiN layer of 3～5nm is the intrinsic Poly-Si layer of 300～500nm as a gate medium and a layer thickness at substrate surface deposit one layer thickness; Photoetching Poly-Si grid and gate medium form the long pseudo-grid of 22～350nm;

The 14 goes on foot, utilizes ion to inject, and respectively nmos device active area and PMOS device active region is carried out N type and the injection of P type ion, forms N type lightly-doped source drain structure (N-LDD) and P type lightly-doped source drain structure (P-LDD), and doping content is 1～5 * 10 ¹⁸Cm ^-3

The 15 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, be the SiO of 5～15nm at substrate surface deposit one layer thickness ₂Layer utilizes dry etch process, etches away the SiO on surface ₂Layer, the SiO of reservation Poly-Si grid and gate medium side ₂, form side wall;

The 16 step, make the PMOS device active region by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of PMOS device; Make the nmos device active area by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of nmos device; Under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation with substrate;

The 17 the step, with chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO ₂, thickness is 300 ~ 500nm, utilizes chemico-mechanical polishing (CMP) technology, with SiO ₂Be planarized to gate surface;

The 18 step, utilizing wet etching that dummy grid is removed fully, stay the autoregistration impression that the grid on the oxide layer pile up, is the lanthana (La of 2 ~ 5nm at the substrate surface layer thickness of growing ₂O ₃); At substrate surface sputter layer of metal tungsten (W), utilize chemico-mechanical polishing (CMP) technology at last with tungsten (W) and lanthana (La beyond the area of grid ₂O ₃) remove;

The 19 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, superficial growth one deck SiO ₂Layer, and lithography fair lead;

The 20 step, metallization, photoetching lead-in wire; Form drain electrode, source electrode and the grid of MOS device and emitter, base stage, the collector electrode metal lead-in wire of SiGe HBT, constituting conducting channel is two polycrystalline, the strain SiGe SOI BiCMOS integrated device of 22～350nm.

8. preparation method according to claim 7; Related maximum temperature is according to the 8th chemical vapor deposition (CVD) the technological temperature decision that go on foot in the 20 step in the strain SiGe SOI BiCMOS integrated device manufacture process of two polycrystalline among this preparation method, and maximum temperature is smaller or equal to 800 ℃.

9. preparation method according to claim 7 is characterized in that, wherein base thickness decides according to the epitaxy layer thickness of the 8th step SiGe, gets 20～60nm.

10. the preparation method of two polycrystalline strain SiGe SOI BiCMOS integrated circuits is characterized in that, comprises the steps:

Step 1, epitaxially grown implementation method is:

(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO ₂, thickness is 150nm, upper layer of material is that doping content is 1 * 10 ¹⁶Cm ^-3N type Si, thickness is 100nm;

(1b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type epitaxy Si layer of 50nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 ¹⁶Cm ^-3

Step 2, the implementation method of deep trench isolation preparation is:

(2a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO ₂

(2b) photoetching isolated area is utilized dry etch process, etches the deep trouth that the degree of depth is 2.5 μ m in isolated area;

(2c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at deep trouth inner surface deposit SiO ₂Layer all covers the deep trouth inner surface;

(2d) utilize chemical vapor deposition (CVD) method, at 600 ℃, SiO in deep trouth ₂The layer of deposit layer of sin more all covers the deep trouth inner surface on the layer;

(2e) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ ₂, utilize chemico-mechanical polishing (CMP) method, remove unnecessary oxide layer, form deep trench isolation;

Step 3, the implementation method of collector electrode contact zone preparation is:

(3a) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the oxide layer of 500nm at epitaxy Si laminar surface deposit one layer thickness;

(3b) photoetching collector electrode contact zone window;

(3c) substrate is carried out phosphorus and inject, making collector electrode contact zone doping content is 1 * 10 ¹⁹Cm ^-3, form collector contact area;

(3d) with substrate under 950 ℃ of temperature, annealing 15s, carry out impurity activation;

Step 4, the implementation method of base contact preparation is:

(4a) etch away the substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one SiO ₂Layer, thickness is 20nm;

(4b) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one P type Poly-Si layer, as the contact zone, base, this layer thickness is 200nm, and doping content is 1 * 10 ²⁰Cm ^-3

(4c) photoetching Poly-Si forms outer base area, at 600 ℃, at substrate surface deposit SiO ₂Layer, thickness is 200nm, utilizes the method for chemico-mechanical polishing (CMP), removes the SiO on Poly-Si surface ₂

(4d) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one SiN layer, thickness is 50nm;

(4e) photoetching emitter window etches away SiN layer and Poly-Si layer in the emitter window;

(4f) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit layer of sin layer, thickness is 10nm;

Step 5, the implementation method of base material preparation is:

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5b) utilize wet etching, to SiO in the window ₂Layer carries out excessive erosion, forms the zone, base;

(5c) utilize chemical vapor deposition (CVD) method, at 600 ℃, the regioselectivity growth SiGe base in the base, the Ge component is 15%, doping content is 5 * 10 ¹⁸Cm ^-3, thickness is 20nm;

Step 6, the implementation method of emitter region preparation is:

(6a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit Poly-Si, thickness is 200nm;

(6b) substrate is carried out phosphorus and inject, and utilize chemico-mechanical polishing (CMP) to remove the Poly-Si of emitter contact hole zone, form emitter with outer surface;

(6c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO ₂Layer, the 120s that under 950 ℃ of temperature, anneals, activator impurity;

Step 7, the implementation method of strain SiGe material preparation is:

(7a) photoetching MOS active area;

(7b) utilize dry etch process, etch the shallow slot that the degree of depth is 100nm at the MOS active area;

(7c) utilize chemical vapor deposition (CVD) method, at 600 ℃, growth thickness is the N type Si resilient coating of 80nm in shallow slot, and this layer doping content is 1 * 10 ¹⁵Cm ^-3

(7d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the N type SiGe epitaxial loayer of 10nm at the substrate surface growth thickness, and this layer Ge component is 15%, and doping content is 1 * 10 ¹⁶Cm ^-3

(7e) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the intrinsic relaxation type Si cap layer of 3nm at the substrate surface growth thickness;

Step 8, the implementation method that nmos device and PMOS device form is:

(8a) utilize chemical vapor deposition (CVD) method, at 600 ℃, the SiO of growth one deck 300nm on substrate ₂

(8b) photoetching PMOS device active region carries out N type ion to the PMOS device active region and injects, and makes its doping content reach 1 * 10 ¹⁷Cm ^-3

(8c) photoetching nmos device active area utilizes ion implantation technology that P type ion is carried out in the nmos device zone and injects, and forms nmos device active area P trap, and P trap doping content is 1 * 10 ¹⁷Cm ^-3

(8d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the SiN layer of 3nm at superficial growth one layer thickness;

(8e) utilize chemical vapor deposition (CVD) method, at 600 ℃, the polysilicon of growth one deck 300nm on the SiN layer;

(8f) photoetching Poly-Si grid and gate medium form the long pseudo-grid of 22nm;

(8g) photoetching nmos device active area carries out N type ion to the nmos device active area and injects, and forms N type lightly-doped source drain structure (N-LDD), and doping content is 1 * 10 ¹⁸Cm ^-3

(8h) photoetching PMOS device active region carries out P type ion to the PMOS device active region and injects, and forms P type lightly-doped source drain structure (P-LDD), and doping content is 1 * 10 ¹⁸Cm ^-3

(8i) at substrate surface, utilize chemical vapor deposition (CVD) method, at 600 ℃, growth one deck SiO ₂, thickness is 10nm, utilizes the dry etch process photoetching to fall unnecessary SiO subsequently ₂, keep gate lateral wall SiO ₂, form side wall;

(8j) make the PMOS device active region by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of PMOS device;

(8k) make the nmos device active area by lithography, utilize the ion implantation technique autoregistration to form the source-drain area of nmos device;

(8l) with substrate under 950 ℃ of temperature, annealing 120s, carry out impurity activation;

Step 9, the implementation method of grid preparation is:

(9a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO ₂Layer, SiO ₂Thickness is 300nm thickness;

(9b) utilize chemico-mechanical polishing (CMP) method, the surface is planarized to gate level;

(9c) utilize wet etching that dummy grid is removed fully, stay the autoregistration impression that the grid on the oxide layer pile up;

Be the lanthana (La of 2nm (9d) at the substrate surface layer thickness of growing ₂O ₃);

(9e) at substrate surface sputter layer of metal tungsten (W);

(9f) utilize chemico-mechanical polishing (CMP) technology with tungsten (W) and lanthana (La beyond the area of grid ₂O ₃) remove;

Step 10, the implementation method that constitutes the BiCMOS integrated circuit is:

(10a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at superficial growth one deck SiO ₂Layer;

(10b) carve fairlead;

(10c) metallization;

(10d) photoetching lead-in wire; Form MOS device drain metal lead wire, source metal lead-in wire and gate metal lead-in wire; Bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, constituting the MOS conducting channel is two polycrystalline, strain SiGe SOI BiCMOS integrated device and the circuit of 22nm.

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