CN102710246A - Output stage quick response circuit and response method thereof - Google Patents
Output stage quick response circuit and response method thereof Download PDFInfo
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- CN102710246A CN102710246A CN2012102198709A CN201210219870A CN102710246A CN 102710246 A CN102710246 A CN 102710246A CN 2012102198709 A CN2012102198709 A CN 2012102198709A CN 201210219870 A CN201210219870 A CN 201210219870A CN 102710246 A CN102710246 A CN 102710246A
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Abstract
The invention discloses an output stage quick response circuit which comprises an input stage, an output stage, a drive stage and an accelerating stage; the accelerating stage is connected with the drive stage for reducing the rising edge time and the falling edge time of the output signal of the output stage; a predetermined amount of current is set in advance for the accelerating stage, when a second transistor MN1 of the output stage needs to be opened, the pre-set current quickly flows into the second transistor MN1 in order to shorten the opening time of the second transistor MN1 and the falling edge time of the output signal, when the second transistor MN1 of the output stage needs to change into the close state from the open state, the accelerating stage quickly extracts the surplus current carrier of a base electrode of the second transistor MN1 of the output stage so as to accelerate the state transformation and shorten the rising edge time of the output signal. With the adoption of the output stage quick response circuit and the response method of the circuit, the problems of too long rising edge time and falling edge time of the output stage signal in an analogue integrated circuit are solved.
Description
Technical field
The invention belongs to technical field of analog integrated circuit design, relate to a kind of fast response circuit, relate in particular to a kind of output stage fast response circuit; Simultaneously, the invention still further relates to the fast response method of above-mentioned output stage fast response circuit.
Background technology
The switching speed of integrated circuit is the parameter of a key, directly has influence on the operating frequency of circuit, the more important thing is, obtain then need reducing rising edge time and trailing edge time near desirable square wave as far as possible.Rising edge time and trailing edge time response are exactly transistor converts opening into from the opening to the closed condition or from closed condition time in circuit.According to Semiconductor Physics and Principles of Transistors, transistor becomes off state, becomes the flow process that opening is a charge carrier from off state from opening, needs the regular hour.
Become the process of the certain electric current of the similar usefulness of process of opening to the electric capacity charging from off state, after the conducting voltage of charging voltage more than or equal to transistor input knot, transistor becomes opening from off state, and the charging interval is current charging time.The way that reduces the charging interval is simple relatively, promptly increases charging current and reduces to be recharged electric capacity.
The process that becomes closed condition from opening is then complicated a lot, is operated in the transistor in supersaturation district during especially for opening.At first, transistor will become critical saturation condition from hypersaturated state, becomes closed condition from critical saturation condition at last, and the similar input knot of whole process excess charge carrier is through the capacitor discharge process.Reduce to become the time of closed condition from opening, the excess charge carrier number that as far as possible reduce input knot with reduce by discharge capacity, make the charge carrier of the transistor input knot entering cut-off region that discharges rapidly.
In the analog integrated circuit, heavy load output-stage circuit particularly, reducing rising edge and trailing edge time has two contradictions.At first, in order to satisfy driving force, the output transistor in the output-stage circuit needs bigger size, and the parasitic capacitance of large-size crystals pipe is bigger.In order to obtain big driving force, the on off state of the output transistor work in the output-stage circuit is in hypersaturated state and cut-off state conversion.Simultaneously, in order to obtain big driving force, the output transistor in the output-stage circuit often needs bigger preceding stage drive circuit, bigger preceding stage drive circuit, the transistor of the large-size that need change with cut-off region in the supersaturation district equally.Preceding stage drive circuit can adopt schottky transistor to realize; Stage drive circuit is in time that supersaturation district and cut-off region are changed each other before can reducing greatly; But schottky transistor needs special integrated circuit fabrication process, and technique controlling difficulty is bigger, and manufacturing cost increases.So reducing the rising edge and the trailing edge time of heavy load output-stage circuit is the design challenge that IC design person faces.
Fig. 1 is traditional open collector output-stage circuit sketch map.The input driving stage is by transistor MP1, and resistance R 1 is formed with resistance R 2, and transistor MN1 is an output transistor, and in order to guarantee enough driving forces, the size of output transistor MN1 is general bigger, and Rl is a load resistance.See that from the large-signal angle when input signal VIN was high level (VCC), transistor MP1 was a closed condition; There are not current flowing resistance R1 and R2; Then the voltage of resistance R 2 is ground level, and output transistor MN1 is a closed condition, and the output signal is high level VCC through pull-up resistor Rload.When input signal VIN becomes low level (being lower than VCC-0.7V) by high level (VCC); Transistor MP1 becomes open mode by closed condition; Electric current I p flows to ground level through resistance R 1 with R2 from transistorized collector electrode (corresponding CMOS technology is drain electrode, down together); The resistance multiplied result of electric current I p and resistance R 2 is the voltage Vr2 of resistance R 2, and about the value of Vr2 was greater than 0.7V, then output transistor MN1 became open mode by closed condition, and output voltage becomes low level (closely level) by high level; Reverse situation; If input signal VIN changes high level into by low level; Then the state of transistor MP1 is become by unlatching and closes, and then flows through the current vanishes of resistance R 1 and R2, and the voltage of resistance R 2 becomes ground level; Then the state of output transistor MN1 becomes from unlatching and closes, and output signal OUT then changes high level into by low level.From the small-signal angle analysis, output signal OUT from high level become the low level time (trailing edge time) and from time (rising edge time) that low level becomes high level respectively by following two formula decision:
Formula 1:Tfall=Tfp+Td+Tfn;
Tfall: the output signal becomes low level time by high level;
Tfp: transistor MP1 is become the time of opening by off state;
Td: representative connects lead and ohmically time delays etc.;
Tfn: output transistor MN1 is become the time of opening by off state;
Formula 2:Trise=Trp+Td+Trn;
Trise: the output signal transfers high level time to by low level;
Trp: transistor MP1 is become the time of off state by opening;
Td: representative connects lead and ohmically time delays etc.;
Trn: output transistor MN1 is become the time of off state by opening.
There are two problems in Fig. 1.(1) input transistors MP1 needs bigger driving force to drive output transistor MN1, and then the size of MP1 is bigger and be operated in the supersaturation district, i.e. Tfp, and Trp needs the long period; (2) output stage transistor MN1 size is very big, is operated in the saturation region equally, and promptly Tfn and Trn need the long period.
Fig. 2 is another kind of traditional output-stage circuit structure; Circuit with respect to Fig. 1; This circuit structure has increased a transistor MN2 and a resistance R 3, and wherein transistor MN1 and transistor MN2 form similar Darlington transistor structure, to increase the driving force of prime output-stage circuit.When input signal VIN becomes low level by high level; Transistor MP1 becomes opening from off state; Electric current flows out from the collector electrode (drain electrode) of transistor MP1; When opening output transistor MN1, also open transistor MN2 through resistance R 1 with R2, then also irritate the base stage (grid) of the electric current of some to output transistor from the collector electrode (drain electrode) of MN2.Like this, the electric current that flows to output transistor base stage (grid) has increased the branch road of coming from transistor MN2, and electrorheological is big, can reduce the opening time of output transistor to a certain extent.But this circuit structure has no help to the turn-off time of output transistor, just can't reduce the rising edge time of output stage output signal.
Summary of the invention
Technical problem to be solved by this invention is: a kind of output stage fast response circuit is provided, can reduces to export the rising edge and the trailing edge time of conversion, improve the output-stage circuit switching frequency.
In addition, the present invention also provides the fast response method of above-mentioned output stage fast response circuit, can reduce to export the rising edge and the trailing edge time of conversion, improves the output-stage circuit switching frequency.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of output stage fast response circuit, said circuit comprises:
Input stage is in order to receiving inputted signal;
Output stage comprises transistor seconds MN1, in order to output signal output;
Driving stage is connected with said input stage, in order to increase the output stage driving force
Accelerating stage is connected with said driving stage, in order to reduce rising edge time, the trailing edge time of output stage output signal; Said accelerating stage presets the electric current of set amount, and when the transistor seconds MN1 of output stage need open, the electric current that presets flowed into transistor seconds MN1 fast, thereby accelerates opening the time of transistor seconds MN1, reduces to export the trailing edge time of signal; When the transistor seconds MN1 of output stage need be when opening becomes closed condition, said accelerating stage extracts the base stage excess of the transistor seconds MN1 of output stage fast, acceleration mode conversion, the rising edge time that reduces to export signal.
As a kind of preferred version of the present invention, said input stage comprises the first transistor MP1; First utmost point of transistor MP1 connects the input signal end, and second utmost point connects driving stage, and the 3rd utmost point connects supply voltage VCC;
Said driving stage comprises the 3rd transistor MN2, first resistance R 1, second resistance R 2, the 3rd resistance R 3; First utmost point of the 3rd transistor MN2 connects second utmost point of the first transistor MP1, and second utmost point of the 3rd transistor MN2 connects supply voltage VCC through the 3rd resistance R 3, and the 3rd utmost point of the 3rd transistor MN2 connects second resistance R 2 and the accelerating stage; Second utmost point of said transistor MP1 connects first end of first resistance R 1, and second end of first resistance R 1 connects first end of second resistance R 2, the second end ground connection of second resistance R 2;
Said accelerating stage comprises the 4th transistor MN3, the 5th transistor MN4, the 6th transistor MN5; First utmost point of said the 4th transistor MN3, second utmost point connect between second utmost point of the 3rd resistance R 3 and the 3rd transistor MN2; The 3rd utmost point of the 4th transistor MN3 connects first utmost point of the 5th transistor MN4, second utmost point of the 5th transistor MN4, first utmost point of the 6th transistor MN5; The 3rd utmost point ground connection of the 5th transistor MN4, the 6th transistor MN5, second utmost point of the 6th transistor MN5 connects the 3rd utmost point of the 3rd transistor MN2;
First utmost point of the transistor seconds MN1 of said output stage connects second end of first resistance R 1; Second utmost point of transistor seconds MN1 connects second end of signal output part, the 4th resistance R load; First end of the 4th resistance R load connects supply voltage VCC, the 3rd utmost point ground connection of transistor seconds MN1;
The said first very base stage of triode or the grid of metal-oxide-semiconductor, the second very collector electrode of triode or the drain electrode of metal-oxide-semiconductor, the 3rd very emitter of triode or the source electrode of metal-oxide-semiconductor.
A kind of fast response method of above-mentioned output stage fast response circuit, said method comprises the steps:
Step S1: accelerating stage presets the electric current of set amount, and when the transistor seconds MN1 of output stage need open, the electric current that presets flowed into transistor seconds MN1 fast, thereby accelerates opening the time of transistor seconds MN1, reduces to export the trailing edge time of signal;
Step S2: when the transistor seconds MN1 of output stage need be when opening becomes closed condition, said accelerating stage extracts the base stage excess of the transistor seconds MN1 of output stage fast, acceleration mode conversion, the rising edge time that reduces to export signal.
Beneficial effect of the present invention is: output stage fast response circuit and response method thereof that the present invention proposes; Can solve the problem of the trailing edge overlong time of output stage signal in the analog integrated circuit; Through presetting a certain amount of electric current, when output stage transistor need be opened, the quick inflow transistor of the electric current that presets; Thereby accelerate transistorized opening the time, reduce to export the trailing edge time of signal.Can also solve simultaneously the problem of the rising edge overlong time of output stage signal in the analog integrated circuit; When output stage transistor need be when opening becomes closed condition; Extract the base stage excess of output stage transistor fast; The acceleration mode conversion, the rising edge time that reduces to export signal.The present invention only increases by three transistors on the basis of conventional circuit structure, and with the standard manufacture process compatible, with a kind of low cost but high-efficiency method has solved the rising edge of output stage signal and the problem of trailing edge time course in the analog integrated circuit.
Description of drawings
Fig. 1 is traditional output-stage circuit structure.
Fig. 2 is another kind of traditional output-stage circuit structure.
Fig. 3 is the output-stage circuit structure optimization schematic diagram that the present invention is based on bipolar process.
Fig. 4 is the output-stage circuit structure optimization schematic diagram that the present invention is based on CMOS technology.
Embodiment
Specify the preferred embodiments of the present invention below in conjunction with accompanying drawing.
Embodiment one
See also Fig. 3, the present invention has disclosed a kind of output stage fast response circuit, and said circuit comprises: input stage 10, driving stage 20, accelerating stage 30, output stage 40.Comprise some transistors in the present embodiment, transistor can be the triode based on bipolar process, also can be the metal-oxide-semiconductor based on CMOS technology; Present embodiment is that triode is an example with said transistor, introduces fast response circuit of the present invention.
Input stage 10 is in order to receiving inputted signal VIN.In the present embodiment, said input stage 10 comprises the first triode MP1; The base stage of triode MP1 connects input signal end VIN, and collector electrode connects driving stage 20, and emitter connects supply voltage VCC.
Output stage 40 comprises the second triode MN1, in order to output signal output OUT.The base stage of the second triode MN1 of said output stage connects second end of first resistance R 1; The collector electrode of the second triode MN1 connects second end of signal output part, the 4th resistance R load; First end of the 4th resistance R load connects supply voltage VCC, the grounded emitter of the second triode MN1.
Driving stage 20 is connected with said input stage, in order to increase the output stage load capacity.Said driving stage comprises the 3rd triode MN2, first resistance R 1, second resistance R 2, the 3rd resistance R 3; The base stage of the 3rd triode MN2 connects the collector electrode of the first triode MP1, and the collector electrode of the 3rd triode MN2 connects supply voltage VCC through the 3rd resistance R 3, and the emitter of the 3rd triode MN2 connects second resistance R 2 and the accelerating stage; The collector electrode of said triode MP1 connects first end of first resistance R 1, and second end of first resistance R 1 connects first end of second resistance R 2, the second end ground connection of second resistance R 2.
Accelerating stage 30 is connected with said driving stage 20, in order to reduce rising edge time, the trailing edge time of output stage output signal.Said accelerating stage 30 presets the electric current of set amount, and when the second triode MN1 of output stage need open, the electric current that presets flowed into the second triode MN1 fast, thereby accelerates opening the time of the second triode MN1, reduces to export the trailing edge time of signal; When the second triode MN1 of output stage need be when opening becomes closed condition, said accelerating stage extracts the base stage excess of the second triode MN1 of output stage fast, acceleration mode conversion, the rising edge time that reduces to export signal.
Particularly, as shown in Figure 3, said accelerating stage 30 comprises the 4th triode MN3, the 5th triode MN4, the 6th triode MN5; The base stage of said the 4th triode MN3, collector electrode connect between the collector electrode of the 3rd resistance R 3 and the 3rd triode MN2; The emitter of the 4th triode MN3 connects the base stage of the 5th triode MN4, the collector electrode of the 5th triode MN4, the base stage of the 6th triode MN5; The grounded emitter of the 5th triode MN4, the 6th triode MN5, the collector electrode of the 6th triode MN5 connects the emitter of the 3rd triode MN2.
Below will be that example is introduced operation principle of the present invention with Fig. 3.Suppose VCC=5V, the output load current Capability Requirement reaches 50mA, and other transistors and resistance size are as shown in Figure 3.
1) circuit initial condition
When input signal VIN initialize signal is high level; Transistor MP1 is in closed condition, does not have electric current to flow out from its collector electrode, and the voltage at resistance R 1 and R2 two ends all is low level; Then transistor MN1 and MN2 also are in closed condition, and output signal OUT is a high level; Passing through the resistance R 3 and the transistor MN3 of two diode connected modes and the electric current between MN4 and the ground from power supply VCC is: Ishunt=(VCC-2Vdio)/R3=(5V-2*0.7V)/5K=0.72mA, the voltage of transistor MN2 collector terminal is approximately the forward conduction voltage drop 1.4V of two diodes.Ishunt is the R3 that flows through, and three transistorized preset current of MN3 and MN4 will be accelerated transistor MN2 and MN1 become opening from closed condition process when input signal generation level conversion.
2) output stage from the time that off state becomes opening be trailing edge time T fall
After input signal VIN converts low level into from initial high level; Transistor MP1 converts opening into by off state; Approximately the electric current I p1 about 1mA flows out from its collector electrode, because output stage load current according to the invention will reach 50mA, so the size of transistor MN1 will be much larger than transistor MN2; Greater than 50 times, that is to say that the parasitic capacitance of transistor MN1 will be much larger than the parasitic capacitance of transistor MN2 in theory.So Ip1 will at first open transistor MN2, and then open transistor MN1, output signal OUT changes low level into from high level.Under this state, the voltage of resistance R 1 and R2 is reduced to about 1V, is operated in hypersaturated state to guarantee transistor MN1 and transistor MN2, reaches maximum current driving ability; Ir2=1V/5k=0.2mA; The voltage of transistor MN2 collector terminal is that transistor base-emitter voltage adds transistor MN2 emitter-collector voltage; Be approximately 1.0V; Thereby make transistor MN3 and transistor MN4 change closed condition into from opening, transistor MN5 still is in closed condition; The collector current of transistor MN2 is (VCC-1V)/R3=0.8mA; Transistor MN1 base current In1=1mA-0.2mA+0.8mA=1.6mA, its electric current amplifying power is reduced to 50 times from 100 under current state, and then the current driving ability of output-stage circuit of the present invention is 1.6mA*50=80mA in theory, satisfies the requirement of 50mA.
Fig. 2 compares with conventional circuit structure, and circuit structure of the present invention has reduced the trailing edge time T fall of output-stage circuit.In Fig. 2; Change to 0.8mA from 0mA during the collector current of transistor MN2, and among Fig. 3, through presetting the electric current of 0.72mA; After making transistor MN2 become opening from closed condition; Collector current becomes 0.8mA rapidly from the 0.72mA that presets, and has only the electric current drop of 0.08mA, has reduced transistor MN2 and has reached the time that maximum current is exported.According to Tfall=Tfp+Td+Tfn, the purpose of the trailing edge time of structure of the present invention through reducing Td, reach to reduce output-stage circuit.
3) output stage from the time that opening becomes off state be rising edge time T rise
After input signal VIN transfers high level to from low level; Transistor MP1 at first by opening become closed condition, then transistor MN2 from opening transfer closed condition to, then transistor MN3 and MN4 transfer opening to by off state; Be that transistor MN1 becomes closed condition from opening at last, causing output pin OUT is high level from low transition.According to Semiconductive Theory, it is a process that transistor becomes off state from opening, needs the regular hour, and there are much relations this time and the service area of transistor when opening.Transistor MN1 is operated in the supersaturation district under opening in this output circuit, and load current is maximum, and the time required from the opening to the closed condition is the longest, is example below with MN1, explains that the present invention reduces the principle of this time.
After transistor MP1 becomes closed condition from opening, its collector current Ip1 vanishing, but the charge carrier of transistor MN1 base stored and can not disappearing at once, emitter junction still is a forward bias, numerical value approximates forward conduction voltage.Because transistor is in saturation condition before turn-offing, collecting region has a large amount of carrier accumulations, promptly so-called collecting region excess storage; The excess storage is also arranged in the base; Though base current was injected by forward and became reverse extraction this moment, this part excess charge stored can not disappear immediately, and collector junction still is in forward in a period of time; Pressure drop Vce on the transistor is still very little, and it is constant that collector current still remains on Ics.Have only the excess stored charge of working as constantly to reduce, so that complete obiteration, collector junction changes into after the zero-bias, and collector current just begins to reduce.Therefore, be exactly the time that dark saturation condition excess stored charge disappears memory time.The length of memory time, the speed of what and this electric charge disappearance of depending on the excess stored charge.
The approach that stored charge disappears has two, and the one, the composite action of electric charge itself is seen from the external circuit angle, the composite action of electric charge is difficult to change through artificial mode after selected components and parts are confirmed.The 2nd, the decimate action of base current.Because base current is a reverse current, be equivalent to the hole and flow out from base stage, this just makes the hole of base and collector region accumulation constantly reduce.Because electroneutral requirement in the accumulative total hole, also should have the electronics accumulative total of equivalent, therefore when extracting the hole, also will extract electronics.When In1=0 constantly after, emitter current Ie=Ic+Ib=Ics-Iout (Iout is for extracting electric current).Still have the injected electrons electric current though can find emitter junction, the electric current I cs that flows out than collector electrode is little, and the electronics of excess storage at this moment flows away from collector electrode as the part of collector current Ics.After the excess stored charge was compound, transistor had been got back to critical saturation condition, from this moment beginning; Collector current begins to reduce, from being reduced to reverse leakage current near saturation value Ics, in the whole decline process; Electronics that accumulates in the base and hole are constantly compound, and the electric charge of accumulation continues to reduce.Stored charge has disappeared basically when the base, and the decline process is accomplished.In order to reduce the time of this process, by reducing emitter junction, collector junction barrier capacitance and base width, to reduce the total amount of electric charge of required extraction, these depend primarily on device itself on the one hand.Can strengthen base stage on the other hand and extract electric current.From Fig. 3, can see; Have no progeny when transistor MN2 closes, transistor MN3 and MN4 open, and have the electric current of about 0.72mA to be mirrored to the base stage of transistor MN1 through transistor MN5; Extract charge carrier to ground level from the base stage of MN1, thereby accelerate the turn off process of transistor MN1.
To sum up, transistorized turn off process is much more complicated than opening process, and the time that is spent is also long a lot.Output-stage circuit; The output-stage circuit operating frequency that particularly load capacity is bigger often is subject to the turn-off time of efferent duct; The present invention is through increasing by 3 transistor MN3, MN4 and MN5 after output transistor MN1 gets into off state; Extract the charge carrier that transistor MN1 excess stores fast, reach the purpose of accelerating transistor MN1 turn off process.Simultaneously, transistor MN3 and MN4 have preset certain electric current for transistor MN2 by resistance R 3, have accelerated the opening procedure of transistor MN2, and the required time of opening process of transistor MN1 is dwindled greatly.
Embodiment two
See also Fig. 4, the difference of present embodiment and embodiment one is that in the present embodiment, fast response circuit of the present invention utilizes the metal-oxide-semiconductor (replacing the triode among the embodiment one) based on CMOS technology to realize technical scheme of the present invention.
Input stage is in order to receiving inputted signal VIN.Said input stage comprises the first metal-oxide-semiconductor MP1; The grid of metal-oxide-semiconductor MP1 connects input signal end VIN, and drain electrode connects driving stage, and source electrode connects supply voltage VCC.
Output stage comprises the second metal-oxide-semiconductor MN1, in order to output signal output OUT.The grid of the second metal-oxide-semiconductor MN1 of said output stage connects second end of first resistance R 1; The drain electrode of the second metal-oxide-semiconductor MN1 connects second end of signal output part, the 4th resistance R load; First end of the 4th resistance R load connects supply voltage VCC, the source ground of the second metal-oxide-semiconductor MN1.
Driving stage 20 is connected with said input stage, in order to increase the output stage load capacity.Said driving stage comprises the 3rd metal-oxide-semiconductor MN2, first resistance R 1, second resistance R 2, the 3rd resistance R 3; The grid of the 3rd metal-oxide-semiconductor MN2 connects the drain electrode of the first metal-oxide-semiconductor MP1, and the drain electrode of the 3rd metal-oxide-semiconductor MN2 connects supply voltage VCC through the 3rd resistance R 3, and the source electrode of the 3rd metal-oxide-semiconductor MN2 connects second resistance R 2 and the accelerating stage; The drain electrode of said metal-oxide-semiconductor MP1 connects first end of first resistance R 1, and second end of first resistance R 1 connects first end of second resistance R 2, the second end ground connection of second resistance R 2.
Accelerating stage is connected with said driving stage, in order to reduce rising edge time, the trailing edge time of output stage output signal.Said accelerating stage presets the electric current of set amount, and when the second metal-oxide-semiconductor MN1 of output stage need open, the electric current that presets flowed into the second metal-oxide-semiconductor MN1 fast, thereby accelerates opening the time of the second metal-oxide-semiconductor MN1, reduces to export the trailing edge time of signal; When the second metal-oxide-semiconductor MN1 of output stage need be when opening becomes closed condition, said accelerating stage extracts the base stage excess of the second metal-oxide-semiconductor MN1 of output stage fast, acceleration mode conversion, the rising edge time that reduces to export signal.
As shown in Figure 4, said accelerating stage comprises the 4th metal-oxide-semiconductor MN3, the 5th metal-oxide-semiconductor MN4, the 6th metal-oxide-semiconductor MN5; The grid of said the 4th metal-oxide-semiconductor MN3, drain electrode connect between the drain electrode of the 3rd resistance R 3 and the 3rd metal-oxide-semiconductor MN2; The source electrode of the 4th metal-oxide-semiconductor MN3 connects the grid of the 5th metal-oxide-semiconductor MN4, the drain electrode of the 5th metal-oxide-semiconductor MN4, the grid of the 6th metal-oxide-semiconductor MN5; The source ground of the 5th metal-oxide-semiconductor MN4, the 6th metal-oxide-semiconductor MN5, the drain electrode of the 6th metal-oxide-semiconductor MN5 connects the source electrode of the 3rd metal-oxide-semiconductor MN2.
In sum; Output stage fast response circuit and response method thereof that the present invention proposes can solve the problem of the trailing edge overlong time of output stage signal in the analog integrated circuit, through presetting a certain amount of electric current; When output stage transistor need be opened; The quick inflow transistor of the electric current that presets, thus transistorized opening the time accelerated, reduce to export the trailing edge time of signal.Can also solve simultaneously the problem of the rising edge overlong time of output stage signal in the analog integrated circuit; When output stage transistor need be when opening becomes closed condition; Extract the base stage excess of output stage transistor fast; The acceleration mode conversion, the rising edge time that reduces to export signal.The present invention only increases by three transistors on the basis of conventional circuit structure, and with the standard manufacture process compatible, with a kind of low cost but high-efficiency method has solved the rising edge of output stage signal and the problem of trailing edge overlong time in the analog integrated circuit.
Here description of the invention and application is illustrative, is not to want with scope restriction of the present invention in the above-described embodiments.Here the distortion of the embodiment that is disclosed and change are possible, and the replacement of embodiment is known with the various parts of equivalence for those those of ordinary skill in the art.Those skilled in the art are noted that under the situation that does not break away from spirit of the present invention or substantive characteristics, and the present invention can be with other form, structure, layout, ratio, and realize with other assembly, material and parts.Under the situation that does not break away from the scope of the invention and spirit, can carry out other distortion and change here to the embodiment that is disclosed.
Claims (3)
1. an output stage fast response circuit is characterized in that, said circuit comprises:
Input stage is in order to receiving inputted signal;
Output stage comprises transistor seconds MN1, in order to output signal output;
Driving stage is connected with said input stage, in order to increase the output stage load capacity
Accelerating stage is connected with said driving stage, in order to reduce rising edge time, the trailing edge time of output stage output signal; Said accelerating stage presets the electric current of set amount, and when the transistor seconds MN1 of output stage need open, the electric current that presets flowed into transistor seconds MN1 fast, thereby accelerates opening the time of transistor seconds MN1, reduces to export the trailing edge time of signal; When the transistor seconds MN1 of output stage need be when opening becomes closed condition, said accelerating stage extracts the base stage excess of the transistor seconds MN1 of output stage fast, acceleration mode conversion, the rising edge time that reduces to export signal.
2. output stage fast response circuit according to claim 1 is characterized in that:
Said input stage comprises the first transistor MP1; First utmost point of transistor MP1 connects the input signal end, and second utmost point connects driving stage, and the 3rd utmost point connects supply voltage VCC;
Said driving stage comprises the 3rd transistor MN2, first resistance R 1, second resistance R 2, the 3rd resistance R 3; First utmost point of the 3rd transistor MN2 connects second utmost point of the first transistor MP1, and second utmost point of the 3rd transistor MN2 connects supply voltage VCC through the 3rd resistance R 3, and the 3rd utmost point of the 3rd transistor MN2 connects second resistance R 2 and the accelerating stage; Second utmost point of said transistor MP1 connects first end of first resistance R 1, and second end of first resistance R 1 connects first end of second resistance R 2, the second end ground connection of second resistance R 2;
Said accelerating stage comprises the 4th transistor MN3, the 5th transistor MN4, the 6th transistor MN5;
First utmost point of said the 4th transistor MN3, second utmost point connect between second utmost point of the 3rd resistance R 3 and the 3rd transistor MN2; The 3rd utmost point of the 4th transistor MN3 connects first utmost point of the 5th transistor MN4, second utmost point of the 5th transistor MN4, first utmost point of the 6th transistor MN5; The 3rd utmost point ground connection of the 5th transistor MN4, the 6th transistor MN5, second utmost point of the 6th transistor MN5 connects the 3rd utmost point of the 3rd transistor MN2;
First utmost point of the transistor seconds MN1 of said output stage connects second end of first resistance R 1; Second utmost point of transistor seconds MN1 connects second end of signal output part, the 4th resistance R load; First end of the 4th resistance R load connects supply voltage VCC, the 3rd utmost point ground connection of transistor seconds MN1;
The said first very base stage of triode or the grid of metal-oxide-semiconductor, the second very collector electrode of triode or the drain electrode of metal-oxide-semiconductor, the 3rd very emitter of triode or the source electrode of metal-oxide-semiconductor.
3. the fast response method of claim 1 or 2 described output stage fast response circuits is characterized in that said method comprises the steps:
Step S1: accelerating stage presets the electric current of set amount, and when the transistor seconds MN1 of output stage need open, the electric current that presets flowed into transistor seconds MN1 fast, thereby accelerates opening the time of transistor seconds MN1, reduces to export the trailing edge time of signal;
Step S2: when the transistor seconds MN1 of output stage need be when opening becomes closed condition, said accelerating stage extracts the base stage excess of the transistor seconds MN1 of output stage fast, acceleration mode conversion, the rising edge time that reduces to export signal.
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| CN201210219870.9A CN102710246B (en) | 2012-06-28 | 2012-06-28 | Output stage quick response circuit and response method thereof |
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| CN102710246A true CN102710246A (en) | 2012-10-03 |
| CN102710246B CN102710246B (en) | 2014-09-03 |
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| CN201210219870.9A Active CN102710246B (en) | 2012-06-28 | 2012-06-28 | Output stage quick response circuit and response method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5634230A (en) * | 1979-08-29 | 1981-04-06 | Fujitsu Ltd | Logical operation circuit |
| CN85109185A (en) * | 1985-01-15 | 1986-10-22 | 得克萨斯仪器公司 | The adjustable accelerating circuit that is used for transistor-transistor logic circuit type door |
| CN201467101U (en) * | 2009-04-02 | 2010-05-12 | 深圳市麦格米特驱动技术有限公司 | MOSFET tube drive circuit adopting bootstrap power supply |
-
2012
- 2012-06-28 CN CN201210219870.9A patent/CN102710246B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5634230A (en) * | 1979-08-29 | 1981-04-06 | Fujitsu Ltd | Logical operation circuit |
| CN85109185A (en) * | 1985-01-15 | 1986-10-22 | 得克萨斯仪器公司 | The adjustable accelerating circuit that is used for transistor-transistor logic circuit type door |
| CN201467101U (en) * | 2009-04-02 | 2010-05-12 | 深圳市麦格米特驱动技术有限公司 | MOSFET tube drive circuit adopting bootstrap power supply |
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|---|---|
| CN102710246B (en) | 2014-09-03 |
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Address after: 201306 Room 101, No. 9 and 10, Lane 1775, Qiushan Road, Lingang xinpian District, pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Saizhuo Electronic Technology (Shanghai) Co.,Ltd. Address before: 200241 room 2103, building B, No. 555, Dongchuan Road, Minhang District, Shanghai Patentee before: SENTRONIC TECHNOLOGY (SHANGHAI) Co.,Ltd. |