CN100561871C

CN100561871C - Level shifting circuit

Info

Publication number: CN100561871C
Application number: CNB2005100292123A
Authority: CN
Inventors: 董艺
Original assignee: Shanghai Fudan Microelectronics Co Ltd
Current assignee: Shanghai Fudan Microelectronics Group Co Ltd
Priority date: 2005-08-30
Filing date: 2005-08-30
Publication date: 2009-11-18
Anticipated expiration: 2025-08-30
Also published as: CN1734941A

Abstract

The invention discloses a kind of level shifting circuit, comprising: first order input buffering phase inverter; Second level buffer inverter, its input connect the output of described first order input buffering phase inverter; Level lifting circuit has a positive input terminal and a negative input end; Negative input end connects the output of described first order input buffering phase inverter, and positive input terminal connects the output of described second level buffer inverter; The output level signal of this level lifting circuit and its positive input terminal level signal logically are consistent.Having used the high withstand voltage high NDMOS that opens threshold value in described level lifting circuit and the second level buffer inverter, solved NDMOS and opened the bottleneck that threshold value is higher than 5V, will be the level conversion of the digital signal of power supply with 5V.

Description

Level shifting circuit

Technical field

The present invention relates to a kind of level shifting circuit, specifically, relate to technology, use height withstand voltage, have the high two level shifting circuits that inject metal-oxide-semiconductor (NDMOS pipe) of N type of opening threshold value based on BICMOS.

Background technology

Some are used for the quite high voltage of chip needs of controlling and driving machine operation.Because the restriction of voltage, it is inappropriate selecting common CMOS technology when these chips of design.Bipolar complementary metal oxide semiconductor (BICMOS) technology of compatible high tension apparatus then is first-selected.

BICMOS technology is because its special device architecture can be made withstand voltage very high metal-oxide-semiconductor, the highest can reaching more than the 80V.High pressure NMOS in the BICMOS technology is made into the NDMOS pipe, and its structure is different from common NMOS pipe fully.The P type substrate of NDMOS uses the doping content of NPN pipe base stage in the bipolar technology, and N type drain region doping content is lower and the drain region is longer.In the high pressure transoid, inversion layer is less to the propelling on one side of P type substrate like this, and the source drain breakdown when having prevented high pressure effectively makes NDMOS can bear quite high voltage.This withstand voltage enough is used to design the motor drive ic that maximum voltage value is 27V～70V.

Motor control chip generally is made up of logic control part and high pressure output.The supply voltage of logic control part is 5V.The high pressure output then can use the chip ceiling voltage of 27V～70V as required.At this moment solve the problem of level conversion with regard to needs.

The approach that prior art solves level conversion is by a common level shifting circuit.Its major part is 2 drop-down NMOS pipes and 2 PMOS pipes that are connected into the self feed back form.The digital logic signal of 0～5V of the grid input opposite phase of 2 NMOS pipes, 2 PMOS pipes are power supply with the high voltage, have so just realized from 5V to high-tension level conversion.But the prerequisite that sort circuit can operate as normal is that the unlatching threshold value of 2 pull-down NMOS pipe is less than 5V so that the NMOS pipe can normally be opened and end.

Yet use the words of the DMOS pipe in the BICMOS technology but can't satisfy above prerequisite.The turn-on threshold voltage of general metal-oxide-semiconductor is directly proportional with substrate doping, and promptly substrate doping is big more, and turn-on threshold voltage is also big more.The high-dopant concentration substrate of NDMOS pipe makes it open threshold value up to 7V.If the digital signal voltage of NDMOS tube grid input can not surpass 5V, whenever NDMOS is in cut-off region, and common level shifting circuit can't operate as normal.Therefore, using the common level shifting circuit of prior art is to solve high level conversion problem of opening threshold value NMOS pipe.

Summary of the invention

The objective of the invention is to, a kind of level shifting circuit is provided, to overcome at present the technical problem that can not reach the level conversion function with the NDMOS pipe that height is opened threshold value.

In order to achieve the above object, technical scheme of the present invention is as follows:

A kind of level shifting circuit comprises: first order input buffering phase inverter; Second level buffer inverter, its input connect the output of described first order input buffering phase inverter; Level lifting circuit has a positive input terminal and a negative input end; Negative input end connects the output of described first order input buffering phase inverter, and positive input terminal connects the output of described second level buffer inverter; Consistent on the level logic of the output level of this level lifting circuit and the input of its positive input terminal.

Level shifting circuit of the present invention, when a first order input buffering phase inverter input low level (signal of logical zero), it just exports a high level (signal of logical one) to the B point, at this moment second level buffer inverter will be exported a low level (signal of logical zero) to the A point, and third level level lifting circuit is exported a low level (signal of logical zero) after having received the voltage that A point and B order; When a first order input buffering phase inverter input high level (signal of logical one), it just exports a low level (signal of logical zero) to the B point, at this moment second level buffer inverter will be exported a high level (signal of logical one) to the A point, and third level level lifting circuit is exported a high level (signal of logical one) after having received the voltage that A point and B order.

Described level lifting circuit comprises that two can tolerate the NDMOS pipe of 70V voltage and the PDMOS pipe that two can tolerate 70V voltage; The grid of the one NDMOS pipe is as positive input terminal, source ground, and drain electrode connects the drain electrode of a PDMOS pipe and the grid of the 2nd PDMOS pipe; The grid of the 2nd NDMOS pipe is as negative input end, source ground, and drain electrode connects the grid of the drain electrode of the 2nd PDMOS pipe and a PDMOS pipe as output.Having used the high withstand voltage high NDMOS that opens threshold value in circuit, solved NDMOS and opened the bottleneck that threshold value is higher than 5V, will be the level conversion of the digital signal of power supply with 5V.

The grid of the one PDMOS pipe connects the drain electrode of the 2nd PDMOS pipe and the drain electrode of the 2nd NDMOS pipe, and source electrode connects power supply, and drain electrode connects the drain electrode of the grid and a NDMOS pipe of the 2nd PDMOS pipe.

The grid of the 2nd PDMOS pipe connects the drain electrode of a PDMOS pipe and the drain electrode of a NDMOS pipe, and source electrode connects power supply, and drain electrode connects the drain electrode of the grid and the 2nd NDMOS pipe of a PDMOS pipe.

Described supply voltage is set between 27V to 70V, and scalable.

Described second level buffer inverter comprises that one can tolerate the NDMOS pipe of 12V voltage and the PDMOS pipe that can tolerate 12V voltage, forms the structure of CMOS, and wherein the source electrode of PDMOS connects 12V voltage.

Described first order input buffering phase inverter comprises one can tolerate the PDMOS pipe of 12V voltage and the NPN pipe that can tolerate 12V voltage; NPN manages grounded emitter, and base stage is as input, and input signal is to be the digital signal of power supply with 5V, and collector electrode connects after the drain electrode of PDMOS pipe as output; The PDMOS pipe is as current source load usefulness, and its source electrode connects 12V voltage, and grid connects a bias voltage.

The substrate of described all PDMOS pipe and NDMOS pipe all and source shorted.

The unlatching threshold value of described NDMOS pipe is 7V.

Description of drawings

Fig. 1 is the line construction schematic diagram of whole level shifting circuit of the present invention;

Fig. 2 is the schematic circuit of first order input buffering phase inverter among Fig. 1;

Fig. 3 is the schematic circuit of second level buffer inverter among Fig. 1;

Fig. 4 is the schematic circuit of third level level lifting circuit among Fig. 1.

Embodiment

According to Fig. 1 to Fig. 4, provide preferred embodiment of the present invention, and described in detail below, enable to understand better function of the present invention, characteristics.

Fig. 1 is the line construction schematic diagram of whole level shifting circuit of the present invention.As shown in Figure 1, level shifting circuit of the present invention comprises first order input buffering phase inverter 1, second level buffer inverter 2 and third level level lifting circuit 3.The input of second level buffer inverter 2 connects the output of first order input buffering phase inverter 1.Level lifting circuit 3 has a positive input terminal and a negative input end.Negative input end connects the output of first order input buffering phase inverter 1, and positive input terminal connects the output of second level buffer inverter 2.If first order input buffering phase inverter 1 is transfused to the signal of a logical zero, it just exports the output signal of a logical one (VDD) to the B point, at this moment second level buffer inverter will export a logical zero (0V) signal to the A point, third level level lifting circuit has received the voltage of a logical zero of output (0V) behind the voltage that A point and B order; If first order input buffering phase inverter 1 is transfused to the signal of a logical one, it just exports the output signal of a logical zero (0V) to the B point, at this moment second level buffer inverter will export a logical one (VDD) signal to the A point, third level level lifting circuit has received the voltage of a logical one of output (VPP) behind the voltage that A point and B order.That is to say, consistent on the level logic of the output level of level lifting circuit 3 and the input of its positive input terminal.VDD=12V wherein, VPP=60V.

Fig. 2 is the schematic circuit of first order input buffering phase inverter.Its input is that chip internal is the output of the digital circuit of power supply with 5V.If input is a logical one, NPN pipe Q1 just moves output voltage about 0V to, and promptly output logic 0; If input is a logical zero, NPN pipe Q1 does not have electric current, and load P DMOS pipe MPI just is charged to VDD=12V with output, and promptly output logic 1.

Fig. 3 is the schematic circuit of second level buffer inverter.Its input is from the output of first order input buffering phase inverter.When being transfused to logical zero (0V), second level buffer inverter is with regard to output logic 1 (VDD=12V); When being transfused to logical one (VDD=12V), because the unlatching threshold value of NDMOS pipe is 7V, the NDMOS pipe can normally be opened and make output be pulled to logical zero (0V).

Fig. 4 is the schematic circuit of third level level lifting circuit.Its positive input terminal A is from the output of second level buffer inverter, and its negative input end B is from the output of first order input buffering phase inverter.The signal that A point and B are ordered logically is opposite.When A point input logic 1 (VDD, 12V) and B point input logic 0 (0V), MN2 turn-offs, MN1 opens and moves the grid of MP2 to 0V, MP2 is opened output is changed to VPP, promptly output logic 1, this output is simultaneously also turn-offed MP1 to prevent upward generation leakage current of MP1; As A point input logic 0 (0V) and B point input logic 1 (VDD, 12V), MN1 turn-offs, MN2 opens and moves output to 0V, promptly output logic 0, thereby the grid that MP1 is opened MP2 is changed to VPP, has turn-offed MP2 and has produced leakage current to prevent MP2.Though the unlatching threshold value of NDMOS pipe MN1 and MN2 is up to 7V, because the logical one that A point and B are ordered all is 12V rather than 5V, it is open-minded to be enough to make NDMOS to manage, and makes the entire circuit operate as normal.

The front provides the description to preferred embodiment, so that any technical staff in this area can use or utilize the present invention.To this preferred embodiment, those skilled in the art can make various modifications or conversion on the basis that does not break away from the principle of the invention.Should be appreciated that these modifications or conversion do not break away from protection scope of the present invention.

Claims

1, a kind of level shifting circuit is characterized in that, comprising:

First order input buffering phase inverter;

Second level buffer inverter, its input connect the output of described first order input buffering phase inverter;

Level lifting circuit has a positive input terminal and a negative input end; Negative input end connects the output of described first order input buffering phase inverter, and positive input terminal connects the output of described second level buffer inverter; The output level signal of this level lifting circuit and its positive input terminal level signal logically are consistent.

2, level shifting circuit as claimed in claim 1 is characterized in that, described level lifting circuit comprises that two can tolerate the NDMOS pipe of 70V voltage and the PDMOS pipe that two can tolerate 70V voltage; The grid of the one NDMOS pipe is as positive input terminal, source ground, and drain electrode connects the drain electrode of a PDMOS pipe and the grid of the 2nd PDMOS pipe; The grid of the 2nd NDMOS pipe is as negative input end, source ground, and drain electrode connects the grid of the drain electrode of the 2nd PDMOS pipe and a PDMOS pipe as output.

3, level shifting circuit as claimed in claim 2 is characterized in that, the grid of a PDMOS pipe connects the drain electrode of the 2nd PDMOS pipe and the drain electrode of the 2nd NDMOS pipe, and source electrode connects power supply, and drain electrode connects the drain electrode of the grid and a NDMOS pipe of the 2nd PDMOS pipe.

4, level shifting circuit as claimed in claim 2 is characterized in that, the grid of the 2nd PDMOS pipe connects the drain electrode of a PDMOS pipe and the drain electrode of a NDMOS pipe, and source electrode connects power supply, and drain electrode connects the drain electrode of the grid and the 2nd NDMOS pipe of a PDMOS pipe.

5, as claim 3 or 4 described level shifting circuits, it is characterized in that described supply voltage is set between 27V to 70V, and scalable.

As claim 3 or 4 described level shifting circuits, it is characterized in that 6, the unlatching threshold value of described NDMOS pipe is 7V.

As claim 3 or 4 described level shifting circuits, it is characterized in that 7, the substrate of described PDMOS pipe and NDMOS pipe all and source shorted.

8, level shifting circuit as claimed in claim 1, it is characterized in that described second level buffer inverter comprises that one can tolerate the NDMOS pipe of 12V voltage and the PDMOS pipe that can tolerate 12V voltage, form the structure of CMOS, wherein the source electrode of PDMOS connects 12V voltage.

9, level shifting circuit as claimed in claim 8 is characterized in that, the unlatching threshold value of described NDMOS pipe is 7V.

10, level shifting circuit as claimed in claim 8 is characterized in that, the substrate of described PDMOS pipe and NDMOS pipe all and source shorted.

11, level shifting circuit as claimed in claim 1 is characterized in that, described first order input buffering phase inverter comprises one can tolerate the PDMOS pipe of 12V voltage and the NPN pipe that can tolerate 12V voltage; NPN manages grounded emitter, and base stage is as input, and input signal is to be the digital signal of power supply with 5V, and collector electrode connects after the drain electrode of PDMOS pipe as output; The PDMOS pipe is as current source load usefulness, and its source electrode connects 12V voltage, and grid connects a bias voltage.

12, level shifting circuit as claimed in claim 11 is characterized in that, the substrate of described PDMOS pipe and source shorted.