CN101841228B - Clamping protection circuit and PFC control circuit utilizing same - Google Patents

Clamping protection circuit and PFC control circuit utilizing same Download PDF

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Publication number
CN101841228B
CN101841228B CN2009101062061A CN200910106206A CN101841228B CN 101841228 B CN101841228 B CN 101841228B CN 2009101062061 A CN2009101062061 A CN 2009101062061A CN 200910106206 A CN200910106206 A CN 200910106206A CN 101841228 B CN101841228 B CN 101841228B
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China
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module
low pressure
voltage
biasing
node
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CN2009101062061A
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Chinese (zh)
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CN101841228A (en
Inventor
谭润钦
郭丽芳
谷文浩
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辉芒微电子(深圳)有限公司
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    • Y02B70/126
    • Y02P80/112

Abstract

The invention relates to a clamping protection circuit and a PFC control circuit utilizing the same. The clamping protection circuit comprises a high-voltage isolation module (20), a low-voltage clamping module (22) and a low-voltage offset module (21), wherein the high-voltage isolation module (20) is used for receiving the current supply of a high-voltage power supply (Vcc) and outputting low-voltage voltage, the low-voltage clamping module (22) is used for receiving the output low-voltage voltage of the high-voltage isolation module (20) and realizing clamping protection, and the low-voltage offset module (21) is used for providing low-voltage offsets to the high-voltage isolation module (20) and the low-voltage clamping module (22).The clamping protection circuit of the invention can improve clamping level precision, simplifies design, reduces layout area and simultaneously improves transient response speed. When being applied in the PFC control circuit, the clamping protection circuit of the invention can further simplify the design of the whole PFC circuit, reduce the layout area and improve the clamping level precision and the transient response speed of the clamping protection circuit in the PFC control circuit.

Description

Clamping protection circuit and use the PFC control circuit of said clamping protection circuit

Technical field

The present invention relates to switching power circuit, more particularly, relate to the clamping protection circuit in the PFC control circuit and use the PFC control circuit of said clamping protection circuit.

Background technology

The clamping protection circuit as its name suggests, is for the current potential that guarantees the circuit part is no more than clamp value, with assurance circuit safety operate as normal, and is unlikely to damage device, destroys circuit function etc.Clamping protection commonly used divides high clamping protection and low clamping protection, and it applies to analog circuit widely, especially in the power management chip circuit, like AC-DC transducer, pfc controller etc.

In critical conduction mode boosts the typical application of APFC (PFC) control chip; The zero passage detection module detects the boost inductance current zero-crossing point; When detecting the inductive current zero passage, the conducting of power controlling switching tube triggers new switch periods; Guarantee that PFC is operated in critical conduction mode, reduce switching loss and noise.The zero passage detection module realizes through detecting transformer secondary current potential usually, shown in boost module among Fig. 1 10.When power switch pipe Q conducting, the alternating voltage Vg (t) behind over commutation is to inductance L b charging, and the diode D of output is anti-inclined to one side, output capacitance Co powering load, and inductive current is linear to be increased, and the current potential of Vz is-Vg (t)/n that n is that transformer is pricked the number ratio; When power switch pipe Q broke off, inductive current can not suddenly change, the pole reversal at inductance two ends, and output diode D positively biased, inductance L b is to load and output capacitance discharge, and this moment, the current potential of Vz was (Vo-Vg (t))/n.The AC-input voltage effective value changes between the 265V at 85V usually; The current potential of Vz will change between positive and negative tens volts even tens volts; If Vz directly is added on the pin ZCD of PFC control chip, then very high to the inner device withstand voltage Capability Requirement of PFC control chip, these are difficult the realization under common process conditions; Perhaps realize complicated circuit, required chip area is very big.In order to realize with common technology and device, simplify circuit, need to introduce the clamping protection circuit, do not burnt out with the device of protecting chip internal.

High clamp Zener diode regulator commonly used realizes, when the clamped point current potential was higher than the anti-puncture voltage partially of zener, zener punctured, with voltage clamp a relative fixed value.Low clamping protection circuit is commonly used to be realized like 100 circuit among Fig. 1.When the Vz current potential when negative; 106 conductings of isolated high-voltage device drag down device 104 grid potentials, produce branch current I1; High tension apparatus 105 mirror images amplify 104 branch current I1 and form branch current I2; I1 and I2 merge into the low clamp current I resistance R 1 of flowing through at clamped point ZCD, thus with the electronegative potential strangulation of ZCD pin on NodeA-Vgs (106) current potential, and be unlikely to burn the device of chip internal.Yet the excursion of Vz is big in different application, and low clamp current I changes between tens microamperes to several milliamperes, in circuit design, is often provided by the external high pressure power Vcc; Device 101,104 among Fig. 1 100, and 105; 106 all is high-voltage tubes, and chip area is bigger, and cost is higher.Device 106,104,105th, voltage control device along with clamp current changes, is followed the deviation of technology, variation of temperature etc., the clamp level precision of this low clamping protection circuit is relatively poor.And the source electrode of device 105 and drain electrode are connected across between ZCD pin and the Vcc pin, in the Electrostatic Discharge process, very easily form path, damage device, destroy the effect of low clamp, and design brings difficulty to electrostatic discharge (ESD) protection for this.

Therefore, need a kind of clamp level precision that improves, simplified design reduces the clamping protection circuit of chip area.

Summary of the invention

The technical problem that the present invention will solve is, to the above-mentioned defective of prior art, a kind of clamp level precision that improves is provided, and simplified design reduces the clamping protection circuit of chip area.

The technical solution adopted for the present invention to solve the technical problems is: construct a kind of clamping protection circuit, it is characterized in that, said clamping protection circuit comprises:

Be used to receive the high pressure isolation module of high voltage source power supply and output low voltage voltage;

Be used to the low pressure clamp module that receives the output low voltage voltage of said high pressure isolation module and realize clamping protection;

And be used to the low pressure biasing module that said high pressure isolation module and low pressure clamp module provide the low pressure biasing.

In clamping protection circuit of the present invention, said low pressure biasing module comprises:

Being used to said high pressure isolation module provides first biasing module of low pressure biasing and is used to second biasing module that said low pressure clamp module provides the low pressure biasing.

In clamping protection circuit of the present invention, said high pressure isolation module comprises high pressure isolated transistor, first diode; Input, drain electrode that first output, source electrode and the substrate that the grid of wherein said high pressure isolated transistor is connected to said first biasing module is connected to said low pressure clamp module are connected to high voltage source, and the plus earth of said first diode, negative electrode are connected to the input of said low pressure clamp module.

In clamping protection circuit of the present invention; Said low pressure clamp module comprises first switching tube; The base stage of said first switching tube be connected to said second biasing module second output, the very said low pressure clamp of current collection module input and be connected to the source electrode and the substrate of said high pressure isolated transistor, emitter is connected to clamped point.

In clamping protection circuit of the present invention, said second biasing module comprises bias current sources, at least one switching tube, transistor seconds; Wherein, the output of said bias current sources is said second output; The grounded emitter of said at least one switching tube; Collector electrode and base stage are connected to the output of said bias current sources, and input, drain electrode that the grid of said transistor seconds is connected to said low pressure clamp module are connected to first output that said second output, source electrode and substrate are connected to said first biasing module.

In clamping protection circuit of the present invention, second biasing module further comprises a plurality of switching tubes.

In clamping protection circuit of the present invention; Said first biasing module comprises: first resistance and second diode; The plus earth of said second diode, negative electrode are said first output, and said first resistance is connected between said high voltage source and said first output.

In clamping protection circuit of the present invention, said switching tube is a low pressure NPN triode, and said diode is a Zener diode.

Another technical scheme that the present invention solves its technical problem employing is; Construct a kind of PFC control circuit; Comprise boost module; Be used for detecting the boost module boost inductance current zero-crossing point zero passage detection module, PFC control chip and be connected to the clamping protection circuit on the pin ZCD of said PFC control chip, wherein, said clamping protection circuit comprises:

Be used to receive the high pressure isolation module of high voltage source power supply and output low voltage voltage;

Be used to the low pressure clamp module that receives the output low voltage voltage of said high pressure isolation module and realize clamping protection;

And be used to the low pressure biasing module that said high pressure isolation module and low pressure clamp module provide the low pressure biasing.

In PFC control circuit of the present invention, said clamping protection circuit comprises a plurality of low-voltage devices.

The clamping protection circuit of embodiment of the present invention can improve the clamp level precision, and simplified design reduces chip area, has improved the speed of transient response simultaneously.And with clamping protection circuit application of the present invention in the PFC control circuit, more can simplify the design of whole pfc circuit, reduce chip area and improve the clamp level precision of the clamping protection circuit in the PFC control circuit and the speed of transient response.

Description of drawings

To combine accompanying drawing and embodiment that the present invention is described further below, in the accompanying drawing:

Fig. 1 is the clamping protection circuit of prior art;

Fig. 2 is the theory diagram of first embodiment in the clamping protection circuit of the present invention;

Fig. 3 is the theory diagram of second embodiment in the clamping protection circuit of the present invention;

Fig. 4 is the circuit theory diagrams of the 3rd embodiment in the clamping protection circuit of the present invention;

Fig. 5 is that the clamping protection circuit of prior art and the clamp level of clamping protection circuit of the present invention change comparison of wave shape figure with clamp current;

Fig. 6 is the clamping protection circuit of prior art and the transient state clamp comparison of wave shape figure of clamping protection circuit of the present invention;

Fig. 7 is the theory diagram of first embodiment of PFC control circuit of the present invention.

Embodiment

Fig. 2 is the theory diagram of first embodiment in the clamping protection circuit of the present invention.As shown in the figure, clamping protection circuit of the present invention comprises: the high pressure isolation module 20 that is used to receive high voltage source Vcc power supply and output low voltage voltage; Be used to the low pressure clamp module 22 that receives the output low voltage voltage of said high pressure isolation module 20 and realize clamping protection; And be used to the low pressure biasing module 21 that said high pressure isolation module 20 and low pressure clamp module 22 provide the low pressure biasing.

Fig. 3 is the theory diagram of second embodiment in the clamping protection circuit of the present invention.In this embodiment, said low pressure biasing module 21 comprises: being used to said high pressure isolation module 20 provides first biasing module 2011 of low pressure biasing and is used to second biasing module 2012 that said low pressure clamp module 22 provides the low pressure biasing.

Fig. 4 is the circuit theory diagrams of the 3rd embodiment in the clamping protection circuit of the present invention.As shown in Figure 4, said high pressure isolation module 20 comprises high pressure isolated transistor 201, Zener diode 202; The grid of wherein said high pressure isolated transistor 201 is connected to that node Node B, source electrode and substrate are connected to Node C, drain electrode is connected to high voltage source Vcc.The P end ground connection of Zener diode 202, N terminated nodes Node B.

Said low pressure clamp module 22 comprises switching tube 221, and the base stage of said switching tube 221 is connected to Node D, and collector electrode is connected to the source electrode and the substrate of said high pressure isolated transistor 201, and emitter is connected to clamped point ZCD.

Said low pressure biasing module 21 can comprise first biasing module 2011 and second biasing module 2012.Wherein, said second biasing module 2012 comprises bias current sources 213, switching tube 212 and 211, transistor 214.Wherein, the output of said bias current sources 213 is Node D, is connected to Node D behind the base stage of said switching tube 212 and the collector electrode short circuit, and emitter is connected to the collector electrode and the base stage of switching tube 211, the grounded emitter of said switching tube 211.In other embodiments of the invention, can be provided with a plurality of switching tubes.And the clamp level height can be realized through the number that increases or reduce switching tube.The grid of said transistor 214 is connected to Node C, drain electrode is connected to Node D, source electrode and substrate and is connected to Node B.Said first biasing module 201 comprises: resistance 215 and diode 216, and the plus earth of said diode 216, negative electrode are Node B, said resistance 215 is connected between said high voltage source Vcc and the Node B.

In the preferred embodiment shown in Fig. 4, also comprise the boost module 10 that is connected to clamped point ZCD (the ZCD pin of PCF chip just).Wherein said boost module adopts any design well known in the prior art (as shown in fig. 1).In the embodiment show in figure 4, switching tube all can be low pressure NPN triode, and diode can be Zener diode, and transistor 214 can be low pressure PMOS pipe.

Embodiments of the invention below in conjunction with shown in the Fig. 5 and the 6 couples of Fig. 4 describe.The waveform that Fig. 5 changes with clamp current I for the clamp level of using the concrete clamping protection circuit of realizing of clamping protection circuit and the present invention always; In typical case; When clamp current I was changed to 5mA by 100uA, the clamp level of clamping protection circuit commonly used had changed 0.7V nearly, considers process deviation again; Variations in temperature etc., it will be bigger that the clamp level of clamping protection circuit commonly used changes.And low clamping protection circuit of the present invention utilizes in the low pressure clamp module 22 triode 221 process deviations little, and the advantage that current gain is high has overcome this problem, has improved precision, and has accelerated transient response speed.Concrete operation principle is following:

Because Vcc is a high voltage source, can be up to more than 20 volts, in common MOS technology, high pressure NPN device is difficult to obtain, and low-voltage device can not directly bear the high pressure of volt more than 20.In the physical circuit of Fig. 4 was realized, the high pressure isolation module of being made up of high pressure isolated transistor 201 and Zener diode 202 20 had stopped the high pressure of Vcc, thereby assurance NodeC place current potential is the trouble free service voltage of low-voltage device, as less than 6V.Low pressure biasing module 21 is by triode 211,212, bias current sources 213; Low pressure PMOS pipe 214 is formed, and wherein bias current sources 213, and triode 211,212 provides quiescent biasing for low pressure clamp module 22; When the ZCD pin level is lower than clamp level, the triode 221 emitter positively biaseds in the low pressure clamp module 22, collector electrode is anti-inclined to one side; Clamp current I flows out from the ZCD pin, the resistance R 1 in the boost module 10 of flowing through, thus pin ZCD low level is clamped at the NodeD-Vbe place.The clamp level height can be realized through the number that increases or reduce triode 211,212.When clamp current I increases to a certain degree; The current gain of triode 221 can descend; Need to extract more base current and satisfy clamp current I from Node D; Yet bias current sources 213 is constant relatively, and the current potential of Node D will be difficult to keep, and comes for Node D dynamic bias I3 to be provided so in low pressure biasing module 21, designed low pressure PMOS pipe 214.When clamp current I increased, the current potential of Node D reduced, and the gate source voltage of low pressure PMOS pipe 214 increases, and bigger electric current I 3 to Node D is provided, and provided more base current to triode 221 simultaneously, stablized clamp level.

As can beappreciated from fig. 5 the present invention realizes that specifically the low clamp level variation of circuit is no more than 0.15V, and the clamp precision has obtained bigger raising.In Fig. 4; Have only high pressure isolation module 20 mesohigh isolated transistors 201 be high-voltage tube (in the present embodiment; Can be that high pressure is isolated the NMOS pipe), all the other devices all are low-voltage tubes, chip area reduces about 30% than the chip area of the clamping protection circuit 100 shown in Fig. 1.And do not exist in the clamping protection circuit 200 among Fig. 4 very easily to receive ESD to damage path, reduced the difficulty of ESD circuit design.When the Vz current potential is suddenlyd change when being lower than clamp level by high level, the transient response waveform of clamping protection circuit is as shown in Figure 6, and clamping protection circuit of the present invention shows transient response faster, and overshoot voltage is very little.And use the clamping protection circuit always under similarity condition, clamp level is just got back in overshoot more than 1 volt, though the mirror image multiplication factor of the high tension apparatus 105 in clamping protection circuit 100 can reduce overshoot, increased the chip area of circuit board.

Can know that from top analysis and comparison clamping protection circuit of the present invention can be used common technology, littler chip area has realized that clamping protection circuit commonly used is more accurate, clamping protection effect faster.Particularly point out, the clamp level of clamping protection circuit of the present invention can be realized according to the number that the practice situation increases or reduce the triode of low pressure biasing module 21.

Fig. 7 is the theory diagram of first embodiment of PFC control circuit of the present invention.As shown in Figure 7; This PFC control circuit; Comprise boost module 10; Be used for detecting boost module 10 boost inductances current zero-crossing point zero passage detection module 700, PFC control chip 701 and be connected to the clamping protection circuit 200 on the pin ZCD of said PFC control chip 701, said clamping protection circuit 200 comprises: the high pressure isolation module 20 that is used to receive high voltage source Vcc power supply and output low voltage voltage; Be used to the low pressure clamp module 22 that receives the output low voltage voltage of said high pressure isolation module 20 and realize clamping protection; And be used to the low pressure biasing module 21 that said high pressure isolation module 20 and low pressure clamp module 22 provide the low pressure biasing.Each module of PFC control circuit of the present invention can make up referring to each module among Fig. 1-4, and those skilled in the art understand and can accomplish according to prior art the structure of above-mentioned module.

Though the present invention describes through specific embodiment, it will be appreciated by those skilled in the art that, without departing from the present invention, can also carry out various conversion and be equal to alternative the present invention.Therefore, the present invention is not limited to disclosed specific embodiment, and should comprise the whole execution modes that fall in the claim scope of the present invention.

Claims (7)

1. a clamping protection circuit is characterized in that, said clamping protection circuit comprises:
Be used to receive the high pressure isolation module (20) of high voltage source (Vcc) power supply and output low voltage voltage;
Be used to the low pressure clamp module (22) that receives the output low voltage voltage of said high pressure isolation module (20) and realize clamping protection;
And be used to the low pressure biasing module (21) that said high pressure isolation module (20) and low pressure clamp module (22) provide the low pressure biasing; Wherein
Said low pressure biasing module (21) comprising: being used to said high pressure isolation module (20) provides first biasing module (2011) of low pressure biasing and is used to second biasing module (2012) that said low pressure clamp module (22) provides the low pressure biasing;
Said high pressure isolation module (20) comprises high pressure isolated transistor (201), first diode (202); Input (Node C), drain electrode that first output (Node B), source electrode and the substrate that the grid of wherein said high pressure isolated transistor (201) is connected to said first biasing module (2011) is connected to said low pressure clamp module (22) are connected to high voltage source (Vcc), and plus earth, the negative electrode of said first diode (202) is connected to the input (Node C) of said low pressure clamp module (22);
Said low pressure clamp module (22) comprises first switching tube (221); The base stage of said first switching tube (221) be connected to said second biasing module (2012) second output (Node D), the very said low pressure clamp of current collection module (22) input (Node C) and be connected to the source electrode and the substrate of said high pressure isolated transistor (201), emitter is connected to clamped point.
2. clamping protection circuit according to claim 1 is characterized in that, said second biasing module (2012) comprises bias current sources (213), at least one switching tube, transistor seconds (214); Wherein, the output of said bias current sources (213) is said second output (Node D); The grounded emitter of said at least one switching tube; Collector electrode and base stage are connected to the output of said bias current sources (213), and input (Node C), drain electrode that the grid of said transistor seconds (214) is connected to said low pressure clamp module (22) are connected to first output (Node B) that said second output (Node D), source electrode and substrate are connected to said first biasing module (2011).
3. clamping protection circuit according to claim 2 is characterized in that, second biasing module (2012) further comprises a plurality of switching tubes.
4. clamping protection circuit according to claim 2; It is characterized in that; Said first biasing module (2011) comprising: first resistance (215) and second diode (216); The plus earth of said second diode (216), negative electrode are said first output (Node B), and said first resistance (215) is connected between said high voltage source (Vcc) and said first output (Node B).
5. according to the described clamping protection circuit of any claim among the claim 1-4, it is characterized in that said switching tube is a low pressure NPN triode, said diode is a Zener diode.
6. PFC control circuit; Comprise boost module (10); Be used for detecting boost module (10) boost inductance current zero-crossing point zero passage detection module (700), PFC control chip (701) and be connected to the clamping protection circuit (200) on the pin ZCD of said PFC control chip (701); It is characterized in that said clamping protection circuit (200) comprising:
Be used to receive the high pressure isolation module (20) of high voltage source (Vcc) power supply and output low voltage voltage;
Be used to the low pressure clamp module (22) that receives the output low voltage voltage of said high pressure isolation module (20) and realize clamping protection;
And be used to the low pressure biasing module (21) that said high pressure isolation module (20) and low pressure clamp module (22) provide the low pressure biasing; Wherein
Said low pressure biasing module (21) comprising: being used to said high pressure isolation module (20) provides first biasing module (2011) of low pressure biasing and is used to second biasing module (2012) that said low pressure clamp module (22) provides the low pressure biasing;
Said high pressure isolation module (20) comprises high pressure isolated transistor (201), first diode (202); Input (Node C), drain electrode that first output (Node B), source electrode and the substrate that the grid of wherein said high pressure isolated transistor (201) is connected to said first biasing module (2011) is connected to said low pressure clamp module (22) are connected to high voltage source (Vcc), and plus earth, the negative electrode of said first diode (202) is connected to the input (Node C) of said low pressure clamp module (22);
Said low pressure clamp module (22) comprises first switching tube (221); The base stage of said first switching tube (221) be connected to said second biasing module (2012) second output (Node D), the very said low pressure clamp of current collection module (22) input (Node C) and be connected to the source electrode and the substrate of said high pressure isolated transistor (201), emitter is connected to clamped point.
7. PFC control circuit according to claim 6 is characterized in that, said clamping protection circuit comprises a plurality of low-voltage devices.
CN2009101062061A 2009-03-20 2009-03-20 Clamping protection circuit and PFC control circuit utilizing same CN101841228B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2009101062061A CN101841228B (en) 2009-03-20 2009-03-20 Clamping protection circuit and PFC control circuit utilizing same

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Application Number Priority Date Filing Date Title
CN2009101062061A CN101841228B (en) 2009-03-20 2009-03-20 Clamping protection circuit and PFC control circuit utilizing same

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CN101841228B true CN101841228B (en) 2012-07-04

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102354246B (en) * 2011-10-28 2013-07-17 电子科技大学 Active clamping circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1481066A (en) * 2003-06-19 2004-03-10 艾默生网络能源有限公司 BUCK convertor containing synchronous rectitication drive circuit
CN101325411A (en) * 2008-04-16 2008-12-17 中兴通讯股份有限公司 Slow starting circuit for electrifying DC power supply

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1481066A (en) * 2003-06-19 2004-03-10 艾默生网络能源有限公司 BUCK convertor containing synchronous rectitication drive circuit
CN101325411A (en) * 2008-04-16 2008-12-17 中兴通讯股份有限公司 Slow starting circuit for electrifying DC power supply

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