CN102709302B - Image sensor and manufacturing method of transistor - Google Patents
Image sensor and manufacturing method of transistor Download PDFInfo
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- CN102709302B CN102709302B CN201210179855.6A CN201210179855A CN102709302B CN 102709302 B CN102709302 B CN 102709302B CN 201210179855 A CN201210179855 A CN 201210179855A CN 102709302 B CN102709302 B CN 102709302B
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
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Abstract
The invention discloses an image sensor and a manufacturing method of a transistor. The image sensor comprises a pixel array. One or a plurality of pixel units of the pixel array respectively comprise one source following transistor. Each source following transistor is a junction type field effect transistor and comprises a first conduction type substrate, a second conduction type well, a second conduction type deposition doped layer, a first conduction type source region, a first conduction type drain region and a first conduction type doped layer, wherein the second conduction type well is positioned in the first conduction type substrate; the second conduction type deposition doped layer is positioned outside the surface of the first conduction type substrate and at least part of the second conduction type deposition doped layer is positioned on the second conduction type well; the first conduction type source region is positioned in the second conduction type well; the first conduction type drain region is positioned in the first conduction type substrate and/or the second conduction type well; at least part of the first conduction type doped layer is positioned between the second conduction type well and the second conduction type deposition doped layer so as to ensure the first conduction type source region to be electrically connected with the first conduction type drain region; and PN nodes are respectively formed between the first conduction type doped layer and the second conduction type well and between the first conduction type doped layer and the second conduction type deposition doped layer.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to the manufacture method of a kind of imageing sensor and a kind of transistor.
Background technology
Traditional imageing sensor can be divided into two classes usually: charge coupled device (Charge Coupled Device, CCD) imageing sensor and complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor.Wherein, cmos image sensor has the advantages such as volume is little, low in energy consumption, production cost is low, therefore, cmos image sensor is easy to be integrated in the mancarried electronic aids such as such as mobile phone, notebook computer, panel computer, uses as providing the camera module of digital imagery function.
Cmos image sensor adopts the dot structure of 3T or 4T usually.Namely Fig. 1 shows a kind of 4T dot structure of conventional CMOS image sensor, comprises photodiode 11, transfering transistor 12, reset transistor 13, source follow transistor 14 and row selecting transistor 15.Wherein, photodiode 11 forms corresponding image charge signal for responding to light intensity change.Transfering transistor 12 is for receiving transfer control signal TX, under the control of transfer control signal TX, the corresponding conducting of transfering transistor 12 or shutoff, thus the image charge signal making photodiode 11 respond to is read out to the floating diffusion region (floating diffusion) coupled that to drain with this transfering transistor 12, and then by this floating diffusion region memory image charge signal.Reset transistor 13 for receiving reseting controling signal RST, under the control of this reseting controling signal RST, the corresponding conducting of reset transistor 13 or shutoff, thus the grid of following transistor 14 to source provides reset signal.Source is followed transistor 14 and is converted to voltage signal for the image charge signal obtained by transfering transistor 12, and this voltage signal can be outputted on bit line BL by row selecting transistor 15.
But often have larger flicker noise in the voltage signal that conventional CMOS image sensor exports, especially when light is more weak, this flicker noise is more obvious.Flicker noise in voltage signal can reduce picture quality significantly.
Summary of the invention
Therefore, need to provide a kind of imageing sensor had compared with low flash noise.
Inventor finds through research, and traditional cmos image sensor often adopts the surface channel transistor source of being used as to follow transistor.Follow in transistor in this provenance, conducting channel is positioned at substrate surface, and the gate oxide on substrate.But the interface of substrate and gate oxide easily forms interfacial state, this interfacial state can be captured randomly or discharge charge carrier, thus causes the change of channel current, so source follow transistor export voltage signal in introduce flicker noise.
In order to solve the problem, according to an aspect of the present invention, a kind of imageing sensor is provided.This imageing sensor comprises pel array, and the one or more pixel cells in this pel array comprise a source and follow transistor, and it is junction field effect transistor that transistor is followed in described source, and it comprises: the first conductivity type substrate; Second conductive type of trap, is arranged in described first conductivity type substrate; Second conduction type deposit doped layer, to be positioned at outside described first conductivity type substrate surface and to be positioned on described second conductive type of trap at least partly; First conduction type source region, is arranged in described second conductive type of trap; First conductivity type drain region, is arranged in described first conductivity type substrate and/or is arranged in described second conductive type of trap; First conduction type doped layer, at least partly between described second conductive type of trap and described second conduction type deposit doped layer, to make described first conduction type source region be electrically connected with described first conductivity type drain region, and form PN junction respectively between itself and described second conductive type of trap and between itself and described second conduction type deposit doped layer.
Compared to the imageing sensor of prior art, substitute surperficial channel MOS transistor and follow transistor owing to have employed junction field effect transistor as source, the charge carrier which avoid in conducting channel is captured at random because of the interfacial state of oxide layer-Semiconductor substrate interface or is discharged, thus the flicker noise effectively reduced in the voltage signal of output, and then improve the image quality of imageing sensor.In addition, in this junction field effect transistor, the PN junction of conducting channel side is formed by the second conduction type deposit doped layer be positioned at outside the first conductivity type substrate surface and the first conduction type doped layer contacted with it.Because the edge of the second conduction type deposit doped layer can be formed by such as dry etching, its profile is easy to control, and therefore adopts the imageing sensor reliability of this junction field effect transistor higher, and performance difference between different pixels unit is less.
In one embodiment, described second conduction type deposit doped layer comprises polysilicon layer or the amorphous silicon layer of doping.The polysilicon of this doping or amorphous silicon can be formed in outside the first conductivity type substrate surface by chemical vapor deposition mode or other deposit modes be applicable to, and without the need to being formed in the first conductivity type substrate by ion implantation mode.This can reduce primary ions and inject, thus reduces the cost of manufacture of imageing sensor.In addition, inject owing to decreasing primary ions, thus source is followed the profile of conducting channel in transistor and is easy to control, and too much can not cause darker junction depth and affect its performance due to annealing times.Therefore, transistor is followed without the need to making darker isolation channel to isolate adjacent area in the first conductivity type substrate outside its conducting channel in this source, and this can reduce manufacture craft difficulty, and reduces the area of imageing sensor.
In one embodiment, described second conductive type of trap and described second conduction type deposit doped layer are outer overlapped at least partly at described first conduction type doped layer, are electrically connected to each other to make described second conductive type of trap and described second conduction type deposit doped layer.
In one embodiment, described first conductivity type drain region and/or the first conduction type doped layer are positioned at outside described second conductive type of trap at least partly, are electrically connected with described first conductivity type substrate to make described first conductivity type drain region.
In one embodiment, the edge of described second conduction type deposit doped layer be arranged in the first conductivity type substrate surface dielectric layer on or be positioned on the isolated groove of the first conductivity type substrate.In the process of etching second conduction type doped layer, the etching stopping that dielectric layer between its edge and the first conductivity type substrate can make the second conduction type doped layer is on the dielectric layer or on isolated groove, thus the transistor damage avoided the damage of the first conductivity type substrate and bring thus.
According to a further aspect in the invention, additionally provide a kind of manufacture method of transistor, comprise the steps: to provide the first conductivity type substrate, in described first conductivity type substrate, doping is formed with the second conductive type of trap; Adulterate formation first conduction type doped layer in described first conductivity type substrate and/or described second conductive type of trap; Form the second conduction type deposit doped layer, it to be positioned at outside described first conductivity type substrate surface and to be positioned on described first conduction type doped layer at least partly, to make to form PN junction between described second conduction type deposit doped layer and described first conduction type doped layer; The first conduction type source region is formed in described second conductive type of trap, and the first conductivity type drain region is formed in described second conductive type of trap and/or in described first conductivity type substrate, be electrically connected with described first conductivity type drain region to make described first conduction type source region.
In one embodiment, the edge of described second conduction type deposit doped layer be arranged in the first conductivity type substrate surface dielectric layer on or be positioned on the isolated groove of the first conductivity type substrate.
In one embodiment, before the step forming described second conduction type deposit doped layer, also comprise: form described dielectric layer on described first conductivity type substrate surface and/or form isolated groove in described first conductivity type substrate; And the step of described formation second conduction type deposit doped layer comprises further: dielectric layer described in partial etching, exposes at least partly to make described first conduction type doped layer; The polysilicon of deposit doping on described the first conduction type doped layer exposed or amorphous silicon are to form described second conduction type deposit doped layer; And the second conduction type deposit doped layer described in partial etching the second conduction type deposit doped layer edge be etched is positioned on described dielectric layer and/or on described isolated groove.
In one embodiment, the step of described partial etching dielectric layer comprises further: dielectric layer described in partial etching, exposes at least partly to make described first conduction type doped layer and described second conductive type of trap.
In one embodiment, the described polysilicon of deposit doping or the step of amorphous silicon comprise further: adulterate to the polysilicon of institute's deposit or amorphous silicon while polysilicon described in deposit or amorphous silicon, or after polysilicon described in deposit or amorphous silicon, the polysilicon of institute's deposit or amorphous silicon are adulterated.
Embodiment part is hereinafter set forth by above characteristic of the present invention and other characteristics clearly.
Accompanying drawing explanation
Read the following detailed description to non-limiting example by referring to accompanying drawing, more easily can understand features, objects and advantages of the invention.Wherein, same or analogous Reference numeral represents same or analogous device.
Fig. 1 shows a kind of 4T dot structure of conventional CMOS image sensor;
Fig. 2 shows imageing sensor 200 according to an embodiment of the invention;
An example 300 of transistor is followed in the source that Fig. 3 a shows imageing sensor 200 in Fig. 2;
Another example of transistor is followed in the source that Fig. 3 b shows imageing sensor 200 in Fig. 2;
Another example 400 of transistor is followed in the source that Fig. 4 a shows imageing sensor 200 in Fig. 2;
The generalized section of transistor along AA ' direction is followed in the source that Fig. 4 b shows Fig. 4 a;
Fig. 5 a shows the manufacture method 500 of transistor according to an embodiment of the invention;
Fig. 5 b to Fig. 5 e shows the generalized section of the manufacture method 500 in Fig. 5 a.
Embodiment
Discuss enforcement and the use of embodiment below in detail.But, should be appreciated that discussed specific embodiment only exemplarily illustrates and implement and use ad hoc fashion of the present invention, but not limit the scope of the invention.
With reference to figure 2, show imageing sensor 200 according to an embodiment of the invention, this imageing sensor 200 comprises pel array, and each pixel cell in this pel array comprises: photodiode 201, generates corresponding image charge signal for responding to light intensity change; Transfering transistor 202, for transition diagram charge signal; And transistor 204 is followed in source, for based on shifted image charge signal formation voltage signal, wherein, it is junction field effect transistors that transistor 204 is followed in this source.
It should be noted that, in some instances, the multiple pixel cells in pel array can have a source and follow transistor 204, and such as adjacent 2,4 or more pixel cells can share a source and follow transistor 204 with output voltage signal.In addition, in the present embodiment, transistor 204 is followed in source is p type field effect transistors.It will be understood by those skilled in the art that in other examples, source is followed transistor 204 and also be can be n type field effect transistor.
Particularly, photodiode 201 is coupled to reference potential line VSS, such as or negative supply current potential, and between the source electrode of transfering transistor 202, forms corresponding image charge signal for responding to light intensity change.The grid that transistor 204 is followed in drain electrode and the source of transfering transistor 202 is connected, the grid of this transfering transistor 202 is for receiving transfer control signal TX, under the control of transfer control signal TX, the corresponding conducting of transfering transistor 202 or shutoff, thus the image charge signal making photodiode 201 respond to is read out to the floating diffusion region of the drain electrode being coupled in this transfering transistor 202, and by this floating diffusion region memory image charge signal.
Source is followed transistor 204 and is coupled between reference potential line VSS and bias current sources 205, its drain electrode is coupled to reference potential line VSS, its source electrode is coupled to this bias current sources 205 and for output voltage signal, its grid is coupled to the drain electrode of transfering transistor 202, namely floating diffusion region is couple to, to obtain the image charge signal that transfering transistor 202 shifts.Bias current sources 205 biased under, the voltage follow that transistor 204 source electrode is followed in source image charge signal change that its grid obtains and changes, and its voltage gain is close to 1.In one embodiment, the source electrode that transistor 204 is followed in source is couple to bit line (not shown) further by row selecting transistor (not shown), and this voltage signal is supplied to the signal processing circuit of imageing sensor.
In one embodiment, this imageing sensor also comprises reset transistor 203, and the drain electrode of this reset transistor 203 is for receiving reset signal RSG, and its source electrode is couple to the grid that transistor 204 is followed in the drain electrode of transfering transistor 202 and source.The grid of this reset transistor 203 for receiving reseting controling signal RST, under the control of this reseting controling signal RST, the corresponding conducting of reset transistor 203 or shutoff, thus the grid of following transistor 204 to source provides reset signal.In this embodiment, transfering transistor 202 and reset transistor 203 are nmos pass transistor, are appreciated that in other examples, transfering transistor 202 and reset transistor 203 also can adopt the transistor of other types, such as PMOS transistor or technotron.
Substitute surperficial channel MOS transistor and follow transistor 204 owing to have employed junction field effect transistor as source, the charge carrier which avoid in conducting channel is captured at random because of the interfacial state of oxide layer-Semiconductor substrate interface or is discharged, thus the flicker noise effectively reduced in the voltage signal of output, and then improve the image quality of imageing sensor 200.
After reset capacitance 213 and image electric capacity 211 store the electric charge corresponding to reset signal and image charge signal respectively, amplifying unit 215 amplifies the voltage difference on these two electric capacity, and the output voltage through amplifying is supplied to follow-up treatment circuit.
An example 300 of transistor is followed in the source that Fig. 3 a shows imageing sensor 200 in Fig. 2, and wherein transistor is followed in this source is p type field effect transistor.It should be understood by one skilled in the art that its operation principle is equally applicable to source and follows the situation that transistor is n type field effect transistor.
As shown in Figure 3 a, this source is followed transistor and is comprised:
P type substrate 301;
N-type trap 303, it is arranged in P type substrate 301;
N-type deposit doped layer 305, it is positioned at outside P type substrate 301 surface, and is positioned in N-type trap 303 at least partly;
P type source region 307, it is arranged in N-type trap 303;
P type drain region 309, it is arranged in P type substrate 301 and/or N-type trap 303;
P type doped layer 311, it is at least partly between N-type trap 303 and N-type deposit doped layer 305, be electrically connected with P type drain region 309 to make P type source region 307, and P type source region 307 is electrically connected with P type drain region 309, and between P type doped layer 311 and N-type trap 303, and form PN junction respectively between this P type doped layer 311 and N-type deposit doped layer 305.
Particularly, P type substrate 301 can be the semiconductor wafer of P type doping, or the silicon-on-insulator (SOI) of P type doping, or the P type trap zone in the semiconductor wafer of N-type doping, or other similar substrates or well region.
P type source region 307 is all arranged in N-type trap 303.This N-type trap 303 makes P type source region 307 and P type substrate 301 mutually isolated.Because source region 307 is for output voltage signal, it may have higher current potential, and P type substrate 301 is couple to reference potential line usually, such as.Therefore, substrate break-through can be avoided, to ensure that the normal work of transistor is followed in source with P type substrate 301 is mutually isolated in source region 307.
According to the difference of specific embodiment, this P type drain region 309 all can be arranged in the P type substrate 301 outside N-type trap 303; Or be all arranged in N-type trap 303; Or a part is positioned at N-type trap 303, and another part is arranged in the P type substrate 301 outside N-type trap 303.In the example 300 shown in Fig. 3 a, P type drain region 309 is all arranged in N-type trap 303, and thus itself and P type source region 307 are electrically connected to each other by the P type doped layer 311 in N-type trap 303.In actual applications, this P type source region 307 and P type drain region 309 partly overlap (overlap) to realize electrical connection therebetween mutually with P type doped layer 311 respectively.Corresponding with P type doped layer 311, N-type deposit doped layer 305 also can be positioned in N-type trap 303 whole or in part, and between source region 307 and drain region 309.In the example 300 of Fig. 3 a, the Butut (layout) of this N-type deposit doped layer 305 is all positioned at the Butut of N-type trap 303.
P type doped layer 311 between N-type trap 303 and N-type deposit doped layer 305, and is electrically connected P type source region 307 and P type drain region 309.Because P type doped layer 311 is arranged in N-type trap 303 at least partly, thus this P type doped layer 311 contacts with N-type trap 303, thus near its contact interface, define a PN junction of technotron.In addition, P type doped layer 311 also contacts with each other at least partly with the N-type deposit doped layer 305 be located thereon, thus near its contact interface, define another PN junction of technotron.This makes N-type trap 303 and N-type deposit doped layer 305 act as the grid that transistor is followed in this source, and the region between two PN junctions is the conducting channel district that transistor 300 is followed in source.When transistor is followed in source, N-type deposit doped layer 305 (and N-type trap 303) causes the change width of the knot space charge region of these two PN junctions from the different meetings of the voltage difference between source region 307 and drain region 309, namely change the conducting channel thickness of technotron, and then change the size of channel current.It should be noted that, because P type doped layer 311 adopts identical material with N-type deposit doped layer 305, be namely made up of silicon, thus the interface state defects of its contact-making surface position is far fewer than the interface state defects of oxide layer-substrate interface.Because channel current is in the P type doped layer 311 away from P type substrate 301 surface, it can not be subject to the interfacial state effect of P type substrate 301 surface oxide layers-substrate interface substantially, thus greatly reduce the probability that interface state defects captures at random or discharge charge carrier, and then the flicker noise in transistor output voltage signal is followed in the source that effectively reduces.
In certain embodiments, electrical contact between N-type deposit doped layer 305 and P type doped layer 311 can by removing the dielectric layer 304 on P type substrate 301 surface, such as oxide layer, realize, that is: P type substrate 301 surface is formed with layer of oxide layer usually, the oxide layer portion above P type doped layer 311 can be removed to be exposed from P type substrate 301 surface by this P type doped layer 311; Afterwards, then the polysilicon that deposit is such as adulterated in P type substrate 301 or amorphous silicon to form this N-type deposit doped layer 305.This dielectric layer 304 can be previously formed in P type substrate 301 surface.Due to the isolation of dielectric layer 304, N-type deposit doped layer 305 only contacts with P type doped layer 311 and forms PN junction, and can not with P type source region 307 and drain region 309 electrical contact of P type.In some instances, the polysilicon layer of doping or amorphous silicon layer can adulterate to this polysilicon or amorphous silicon in the lump when being deposited, in the reaction cavity of deposit, namely add the gas with Doped ions.This does not just need to adulterate in the mode of ion implantation to form N-type deposit doped layer 305 again, and this can reduce primary ions and inject, thus reduces the cost of manufacture of imageing sensor.To be appreciated that at some in other example, N-type deposit doped layer 305 also can be formed by following manner: first depositing polysilicon or amorphous silicon, then the polysilicon of institute's deposit or amorphous silicon are adulterated, such as, with ion implantation or diffusion way doping.
In addition, N-type deposit doped layer 305 can adopt such as dry etching to control, and its profile is easy to control, and therefore adopts imageing sensor 300 reliability of this technotron higher.Preferably, in the embodiment shown in Fig. 3 a, the edge of N-type deposit doped layer 305 is positioned on dielectric layer 304.This dielectric layer 304 makes N-type deposit doped layer 305 edge and P type substrate 301 isolate.In the process of etching N type deposit doped layer 305, dielectric layer 304 between its edge and P type substrate 301 can make the etching stopping of N-type deposit doped layer 305 on dielectric layer 304, thus the transistor damage avoided the damage of P type substrate 301 and bring thus.In some instances, the part that N-type deposit doped layer 305 contacts with P type substrate 301 is positioned at the window of dielectric layer 304, and its edge exceeds this dielectric layer 304 window edge certain length, such as 5 nanometers, 10 nanometers, 50 nanometers, etc.
In some instances, N-type trap 303 can be divided overlapped in P type doped layer 311 outside with N-type deposit doped layer 305, thus N-type trap 303 and N-type deposit doped layer 305 are electrically connected to each other.This does not just need to make extra through hole or other structures in N-type trap 303 to draw N-type trap 303, thus reduces cost of manufacture.Be appreciated that in other examples, N-type trap 303 also can not directly contact mutually with N-type deposit doped layer 305, but is electrically connected by the through hole in dielectric layer 304.
Another example of transistor is followed in the source that Fig. 3 b shows imageing sensor 200 in Fig. 2.In fig 3b, also show the photodiode of imageing sensor 200, it is made up of P type substrate 301 and the N-type doped region 321 be positioned at outside N-type trap 303.
As shown in Figure 3 b, also comprise isolated groove 323 in P type substrate 301, it is positioned at outside N-type trap 303, namely between N-type doped region 321 and N-type trap 303.Isolated groove 323 adopts insulating material, and such as silica, silicon nitride are formed, and thus have good electric isolation effect.Isolated groove 323 in P type substrate 301 makes N-type doped region 321 and N-type trap 303 mutually isolated, is short-circuited (i.e. break-through) and the operation of effect diagram image-position sensor between its grid can effectively avoiding the negative pole of photodiode and source to follow transistor.Can find out, inject owing to decreasing primary ions, the profile of conducting channel is easy to control, and too much can not cause darker junction depth due to annealing times.Therefore, this imageing sensor is without the need to making darker isolation channel to isolate adjacent area in the P type substrate 301 outside conducting channel, namely isolated groove 323 can adopt fleet plough groove isolation structure (Shallow Trench Isolation), its chip area taken is relatively little, thus effectively can reduce the area of imageing sensor.
In a preferred embodiment, isolated groove 323 can with P type source region 307 and/or N-type doped region 321 adjacent, this can reduce the area of imageing sensor further, thus improve chip integration.Especially, in the example shown in Fig. 3 b, isolated groove 323 and N-type trap 303 and P type source region 307 adjacent, this makes N-type trap 303 reduce with the contact area of P type substrate 301, thus effectively reduces the parasitic capacitance between N-type trap 303 and P type substrate 301.In the image sensor, N-type trap 303 can be coupled to the floating diffusion region of imageing sensor.Be appreciated that the parasitic capacitance between N-type trap 303 and P type substrate 301 is less, the sensitivity of imageing sensor is also higher.Therefore, the sensitivity of imageing sensor can be improved further with the adjacent isolated groove 323 of N-type trap 303 and P type source region 307.
In addition, in certain embodiments, the edge of N-type deposit doped layer 305 also can be positioned on isolated groove 323.This isolated groove 323 makes N-type deposit doped layer 305 edge and P type substrate 301 isolate.In the process of etching N type deposit doped layer 305, isolated groove 323 between its edge and P type substrate 301 can make the etching stopping of N-type deposit doped layer 305 on isolated groove 323, thus the transistor damage avoided the damage of P type substrate 301 and bring thus.
Another example 400 of transistor is followed in the source that Fig. 4 a and Fig. 4 b shows imageing sensor 200 in Fig. 2.Wherein, Fig. 4 b is that in Fig. 4 a, the generalized section of transistor along AA ' direction is followed in source.
As shown in Fig. 4 a and Fig. 4 b, this source is followed transistor and is had and follow structure like transistor-like with the source in Fig. 3 a.But the drain region 409 that transistor is followed in this source is arranged in the P type substrate 401 outside N-type trap 403, and this makes P type impure drain region 409 be electrically connected with P type substrate 401.In actual applications, this drain region 409 is all coupled to reference potential line with P type substrate 401, such as, does not therefore have voltage difference therebetween, thus can not form electric current between drain region 409 and P type substrate 401.
Correspondingly, P type doped layer 411 extends in P type substrate 401 by N-type trap 403 at least in part, is jointly electrically connected source region 407 and drain region 409 to make this P type substrate 401 and P type doped layer 411.Like this, when transistor turns is followed in this source, channel current can flow to source region 407 by drain region 409 through this P type substrate 401 and P type doped layer 411.
Especially, for imageing sensor 200, it has multiple pixel cell usually, and each pixel cell all has source follows transistor.These sources are followed to the drain region 409 of transistor, part or all of drain region 409 can be had to be arranged in P type substrate 401 outside N-type trap 403 all at least in part.Like this, these drain regions 409 be positioned at outside N-type trap 403 can have the current potential equal with P type substrate 401, thus it has equal current potential each other.Thus, this can make the effect that improve ground connection when not increasing chip area, such as, can carry out shared ground connection by P type substrate 401, and this is just avoided different pixels unit earthing potential inconsistent, thus further increases the performance of imageing sensor.
With reference to figure 4a, N-type trap 403 is outer overlapped at least partly at P type doped layer 411 with N-type deposit doped layer 405, thus N-type trap 403 and N-type deposit doped layer 405 are electrically connected to each other.This just does not need in N-type trap 403, to make extra through hole to draw N-type trap 403, thus reduces cost of manufacture.
Fig. 5 a shows the manufacture method 500 of transistor according to an embodiment of the invention.
As shown in Figure 5 a, this manufacture method 500 comprises:
Perform step S501, provide the first conductivity type substrate, in this first conductivity type substrate, doping is formed with the second conductive type of trap;
Perform step S503, adulterate formation first conduction type doped layer in the first conductivity type substrate and/or the second conductive type of trap;
Perform step S505, form the second conduction type deposit doped layer, it to be positioned at outside the first conductivity type substrate surface and to be positioned on the first conduction type doped layer at least partly, to make to form PN junction between the second conduction type deposit doped layer and the first conduction type doped layer;
Perform step S507, the first conduction type source region is formed in the second conductive type of trap, and the first conductivity type drain region is formed in the second conductive type of trap and/or in the first conductivity type substrate, be electrically connected with the first conductivity type drain region to make the first conduction type source region.
Be appreciated that transistor is followed in the source that the manufacture method 500 of this transistor may be used in making image transducer.In actual applications, the technique of making image transducer also comprises and forms photodiode in image sensor pixel cells and other transistors, and such as the step of transfering transistor, reset transistor, row selecting transistor, does not repeat them here.
In some instances, the edge of the second conduction type deposit doped layer is positioned on the dielectric layer on the first conductivity type substrate surface, or is arranged on the isolated groove of the first conductivity type substrate.In the process of etching second conduction type deposit doped layer, dielectric layer between its edge and the first conductivity type substrate or isolated groove can make the etching self-stopping technology of the second conduction type deposit doped layer on dielectric layer or isolated groove, thus the transistor damage avoided the etching injury of the first conductivity type substrate and bring thus.
In some instances, before step S505, also comprise: form dielectric layer on the first conductivity type substrate surface and/or form isolated groove in the first conductivity type substrate; And the step forming the second conduction type deposit doped layer comprises further: partial etching dielectric layer, expose at least partly to make the first conduction type doped layer; The polysilicon of deposit doping on the first conduction type doped layer exposed or amorphous silicon are to form the second conduction type deposit doped layer; And partial etching second conduction type deposit doped layer the second conduction type deposit doped layer edge be etched is positioned on dielectric layer and/or on isolated groove.
In one embodiment, the step of partial etching dielectric layer comprises further: partial etching dielectric layer exposes at least partly to make the first conduction type doped layer and the second conductive type of trap.Thus, need deposit is adulterated on the first conduction type doped layer exposed and the second conductive type of trap polysilicon or amorphous silicon to form the second conduction type deposit doped layer.The the second conduction type electrode layer be formed directly on the second conductive type of trap can with the second conductive type of trap electrical contact under it, thus this second conductive type of trap electricity can be drawn, and without the need to making through hole or other electric connection structures to draw this second conductive type of trap.
Fig. 5 b to Fig. 5 e shows the generalized section of the manufacture method 500 of Fig. 5 a.Wherein, the transistor that this manufacture method 500 is formed is p type field effect transistor.It should be understood by one skilled in the art that its operation principle is equally applicable to the situation that transistor is n type field effect transistor.Next, with reference to figure 5a to Fig. 5 e, an embodiment of the manufacture method 500 of this transistor for making image transducer is described in detail.
As shown in Figure 5 b, provide P type substrate 501, in this P type substrate 501, be formed with photodiode region 502 and N-type trap 503.This N-type trap 503 is separated from each other by P type substrate 501 therebetween with photodiode region 502.
Afterwards, as shown in Figure 5 c, form P type doped layer 511, it is arranged in N-type trap 503 at least partly.In fig. 5 c, P type doped layer 511 is all arranged in N-type trap 503.In addition, N-type trap 503 and constitute a PN junction of transistor between P type doped layer 511 wherein.At some in other embodiment, P type doped layer 511 also can be positioned partially in P type substrate 501, and is positioned partially in N-type trap 503.It should be noted that, the step forming P type doped layer 511 and N-type trap 503 adopts ion implantation to realize usually, after each ion implantation, also needs to carry out annealing in process to this P type substrate 501, such as short annealing process, also reduces the lattice defect injecting and cause with active ions.
Then, dielectric layer 504 is formed on P type substrate 501 surface.This dielectric layer 504 is such as silica or other dielectric materials, can form this dielectric layer 504 by such as oxidation technology or depositing technics.Alternatively, in some instances, can also form isolated groove (not shown) in P type substrate 501, this isolated groove is usually located at outside N-type trap 511.
Then, as fig 5d, form N-type deposit doped layer 505, it is outer and be positioned in N-type trap 503 at least partly, to make to form PN junction between the P type doped layer 511 in N-type deposit doped layer 505 and N-type trap 503 that it is positioned at P type substrate 501 surface.
Particularly, this N-type deposit doped layer 505 can be formed by following step: first, partial etching dielectric layer 504, and to form window in P type substrate 501, this window makes P type doped layer 511 expose at least partly; Then, the polysilicon that deposit is adulterated on the P type doped layer 511 exposed or amorphous silicon are to form N-type deposit doped layer 505; Afterwards, partial etching N-type deposit doped layer 505 also makes N-type deposit doped layer 505 edge be positioned on dielectric layer 504, or make the edge of N-type deposit doped layer 505 be positioned on isolated groove, namely make the edge of this N-type deposit doped layer 505 not be located immediately in P type substrate 501.In some instances, can chemical vapor deposition method depositing polysilicon or amorphous silicon be passed through, and while this polysilicon of deposit or amorphous silicon doped p-type ion, such as phosphorus or arsenic ion, to form polysilicon or the amorphous silicon of doping.In other examples, can pass through chemical vapor deposition method depositing polysilicon or amorphous silicon, afterwards, doped p-type ion in the polysilicon or amorphous silicon of institute's deposit, such as, adulterated by the mode of diffusion or ion implantation.Also having in some examples, first can pass through chemical vapor deposition method depositing polysilicon or amorphous silicon, then the polysilicon of partial etching institute deposit or amorphous silicon, carried out ion implantation to the polysilicon be etched or amorphous silicon more afterwards and carrys out impurity ion before or after formation source region and drain region.
In a preferred embodiment, N-type deposit doped layer 505 is also formed directly in N-type trap 503.Correspondingly, dielectric layer 504 is etched to and P type doped layer 511 and N-type trap 503 is exposed at least partly, and the polysilicon that deposit is adulterated on the P type doped layer 511 exposed and N-type trap 503 or amorphous silicon are to form N-type deposit doped layer.
Can find out, by this dielectric layer window, the polysilicon of institute's deposit directly can contact with the P type doped layer 511 under it, thus forms the PN junction of junction field effect transistor conducting channel opposite side.This PN junction limits the conducting channel of this junction field effect transistor jointly together with the PN junction between P type doped layer 511 and N-type trap 503, and N-type trap 503 and N-type deposit doped layer 505 are then jointly as two grids of junction field effect transistor.
Then, as depicted in fig. 5e, in N-type trap 503, form P type source region 507 and P type drain region 509, and this P type source region 507 and P type drain region 509 are electrically connected to each other.In the example of Fig. 5 e, P type source region 507 is electrically connected by P type doped layer 511 therebetween with P type drain region 509.Be appreciated that, in certain embodiments, P type drain region 509 also can be formed in the P type substrate 501 outside N-type trap 503, this P type drain region 509 can be electrically connected to N-type trap 503 by the P type substrate 501 between itself and N-type trap 503, and is further advanced by P type doped layer 511 and is electrically connected to P type source region 507.
Can find out, because this N-type deposit doped layer 505 can be formed by depositing technics, and without the need to being formed in P type substrate 501 by ion implantation mode.This can reduce primary ions and inject and annealing in process, thus reduces the cost of manufacture of transistor.In addition, inject owing to decreasing primary ions, the profile of conducting channel is easy to control, and too much can not cause darker junction depth due to annealing times.Therefore, this junction field effect transistor is without the need to making darker isolation channel to isolate adjacent area in the P type substrate 501 outside conducting channel, such as between N-type trap 503 and photodiode region 502, this can reduce manufacture craft difficulty, and reduces the area of transistor.
Although illustrate in detail in accompanying drawing and aforesaid description and describe the present invention, it is illustrative and exemplary for should thinking that this is illustrated and describes, instead of restrictive; The invention is not restricted to above-mentioned execution mode.
The those skilled in the art of those the art can pass through research specification, disclosed content and accompanying drawing and appending claims, understand and implement other changes to the execution mode disclosed.In the claims, word " comprises " element and step of not getting rid of other, and wording " one " does not get rid of plural number.In the practical application of invention, the function of the multiple technical characteristics quoted during a part possibility enforcement of rights requires.Any Reference numeral in claim should not be construed as the restriction to scope.
Claims (10)
1. an imageing sensor, is characterized in that, comprises pel array, and the one or more pixel cells in described pel array comprise a source and follow transistor, and it is junction field effect transistor that transistor is followed in described source, and it comprises:
First conductivity type substrate;
Second conductive type of trap, is arranged in described first conductivity type substrate;
Second conduction type deposit doped layer, to be positioned at outside described first conductivity type substrate surface and to be positioned on described second conductive type of trap at least partly;
First conduction type source region, is arranged in described second conductive type of trap;
First conductivity type drain region, is arranged in described first conductivity type substrate and/or is arranged in described second conductive type of trap;
First conduction type doped layer, at least partly between described second conductive type of trap and described second conduction type deposit doped layer, to make described first conduction type source region be electrically connected with described first conductivity type drain region, and form PN junction respectively between itself and described second conductive type of trap and between itself and described second conduction type deposit doped layer.
2. imageing sensor according to claim 1, is characterized in that, described second conduction type deposit doped layer comprises polysilicon layer or the amorphous silicon layer of doping.
3. imageing sensor according to claim 1, it is characterized in that, described second conductive type of trap and described second conduction type deposit doped layer are outer overlapped at least partly at described first conduction type doped layer, are electrically connected to each other to make described second conductive type of trap and described second conduction type deposit doped layer.
4. imageing sensor according to claim 1, it is characterized in that, described first conductivity type drain region and/or described first conduction type doped layer are positioned at outside described second conductive type of trap at least partly, are electrically connected with the first conductivity type substrate to make described first conductivity type drain region.
5. imageing sensor according to claim 1, is characterized in that, on the dielectric layer that the edge of described second conduction type deposit doped layer is arranged in the first conductivity type substrate surface or be positioned on the isolated groove of the first conductivity type substrate.
6. a manufacture method for transistor, is characterized in that, comprises the steps:
There is provided the first conductivity type substrate, in described first conductivity type substrate, doping is formed with the second conductive type of trap;
Adulterate formation first conduction type doped layer in described first conductivity type substrate and/or described second conductive type of trap;
Form the second conduction type deposit doped layer, it to be positioned at outside described first conductivity type substrate surface and to be positioned on described first conduction type doped layer at least partly, to make to form PN junction between described second conduction type deposit doped layer and described first conduction type doped layer;
The first conduction type source region is formed in described second conductive type of trap, and the first conductivity type drain region is formed in described second conductive type of trap and/or in described first conductivity type substrate, be electrically connected with described first conductivity type drain region to make described first conduction type source region.
7. manufacture method according to claim 6, is characterized in that, on the dielectric layer that the edge of described second conduction type deposit doped layer is arranged in the first conductivity type substrate surface or be positioned on the isolated groove of the first conductivity type substrate.
8. manufacture method according to claim 7, is characterized in that,
Before the step forming described second conduction type deposit doped layer, also comprise: form described dielectric layer on described first conductivity type substrate surface and/or form isolated groove in described first conductivity type substrate;
And the step of described formation second conduction type deposit doped layer comprises further:
Dielectric layer described in partial etching, exposes at least partly to make described first conduction type doped layer;
The polysilicon of deposit doping on described the first conduction type doped layer exposed or amorphous silicon are to form described second conduction type deposit doped layer; And
Second conduction type deposit doped layer described in partial etching also makes the second conduction type deposit doped layer edge be etched be positioned on described dielectric layer and/or on described isolated groove.
9. manufacture method according to claim 8, is characterized in that, the step of described partial etching dielectric layer comprises further: dielectric layer described in partial etching, exposes at least partly to make described first conduction type doped layer and described second conductive type of trap.
10. manufacture method according to claim 8, it is characterized in that, the described polysilicon of deposit doping or the step of amorphous silicon comprise further: adulterate to the polysilicon of institute's deposit or amorphous silicon while polysilicon described in deposit or amorphous silicon, or after polysilicon described in deposit or amorphous silicon, the polysilicon of institute's deposit or amorphous silicon are adulterated.
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| CN103928485B (en) * | 2014-05-08 | 2016-05-11 | 重庆大学 | A kind of radioscopic image sensor of high output amplitude |
| CN105304665A (en) * | 2015-10-29 | 2016-02-03 | 上海华力微电子有限公司 | CMOS image sensor for improving full-well capacity of pixel unit |
| CN111403428A (en) * | 2020-03-23 | 2020-07-10 | 中山大学 | Photoelectric sensor, random-readable active pixel circuit, image sensor, and camera device |
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| US6271550B1 (en) * | 1998-08-17 | 2001-08-07 | Elmos Semiconductor Ag | Junction field effect transistor or JFET with a well which has graded doping directly beneath the gate electrode |
| CN101986431A (en) * | 2010-10-25 | 2011-03-16 | 上海宏力半导体制造有限公司 | Quad transistor CMOS image sensor and design method thereof |
| CN102054863A (en) * | 2009-11-09 | 2011-05-11 | 格科微电子（上海）有限公司 | Source follower transistor, pixel structure and circuit |
| WO2011155105A1 (en) * | 2010-06-07 | 2011-12-15 | パナソニック株式会社 | Semiconductor device and method for manufacturing same |
| CN202678315U (en) * | 2012-06-01 | 2013-01-16 | 格科微电子（上海）有限公司 | Image sensor |
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| US7411231B2 (en) * | 2005-12-22 | 2008-08-12 | Analog Devices, Inc. | JFET with drain and/or source modification implant |
| CN102709302B (en) * | 2012-06-01 | 2015-02-11 | 格科微电子（上海）有限公司 | Image sensor and manufacturing method of transistor |
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| US6271550B1 (en) * | 1998-08-17 | 2001-08-07 | Elmos Semiconductor Ag | Junction field effect transistor or JFET with a well which has graded doping directly beneath the gate electrode |
| CN102054863A (en) * | 2009-11-09 | 2011-05-11 | 格科微电子（上海）有限公司 | Source follower transistor, pixel structure and circuit |
| WO2011155105A1 (en) * | 2010-06-07 | 2011-12-15 | パナソニック株式会社 | Semiconductor device and method for manufacturing same |
| CN101986431A (en) * | 2010-10-25 | 2011-03-16 | 上海宏力半导体制造有限公司 | Quad transistor CMOS image sensor and design method thereof |
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