CN102709302A - Image sensor and manufacturing method of transistor - Google Patents
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
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Abstract
The invention discloses an image sensor and a manufacturing method of a transistor. The image sensor comprises a pixel array. One or a plurality of pixel units of the pixel array respectively comprise one source following transistor. Each source following transistor is a junction type field effect transistor and comprises a first conduction type substrate, a second conduction type well, a second conduction type deposition doped layer, a first conduction type source region, a first conduction type drain region and a first conduction type doped layer, wherein the second conduction type well is positioned in the first conduction type substrate; the second conduction type deposition doped layer is positioned outside the surface of the first conduction type substrate and at least part of the second conduction type deposition doped layer is positioned on the second conduction type well; the first conduction type source region is positioned in the second conduction type well; the first conduction type drain region is positioned in the first conduction type substrate and/or the second conduction type well; at least part of the first conduction type doped layer is positioned between the second conduction type well and the second conduction type deposition doped layer so as to ensure the first conduction type source region to be electrically connected with the first conduction type drain region; and PN nodes are respectively formed between the first conduction type doped layer and the second conduction type well and between the first conduction type doped layer and the second conduction type deposition doped layer.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to a kind of imageing sensor and a kind of transistorized manufacture method.
Background technology
The traditional image transducer can be divided into two types usually: charge coupled device (Charge Coupled Device, CCD) imageing sensor and complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor.Wherein, Cmos image sensor has advantages such as volume is little, low in energy consumption, production cost is low; Therefore, cmos image sensor for example is easy to be integrated in the mancarried electronic aids such as mobile phone, notebook computer, panel computer, uses as the shooting module that the digital imagery function is provided.
Cmos image sensor adopts the dot structure of 3T or 4T usually.Fig. 1 promptly shows a kind of 4T dot structure of traditional cmos imageing sensor, comprises that photodiode 11, transfering transistor 12, reset transistor 13, source follow transistor 14 and row selecting transistor 15.Wherein, photodiode 11 is used to respond to the light intensity variation and forms corresponding image charge signal.Transfering transistor 12 is used for receiving transfer control signal TX; Under the control of shifting control signal TX; Transfering transistor 12 corresponding conducting or shutoffs; Thereby the image charge signal that makes photodiode 11 responded to is read into the floating diffusion region (floating diffusion) that couples with 12 drain electrodes of this transfering transistor, and then by this floating diffusion region memory image charge signal.Reset transistor 13 is used to receive reseting controling signal RST, under the control of this reseting controling signal RST, and reset transistor 13 corresponding conducting or shutoffs, thus to the grid that transistor 14 is followed in the source reset signal is provided.It is voltage signal that the image charge conversion of signals that transistor 14 is used for transfering transistor 12 is obtained is followed in the source, and this voltage signal can output on the bit line BL through row selecting transistor 15.
Yet, often have bigger flicker noise in the voltage signal of traditional cmos imageing sensor output, when light was more weak, this flicker noise was more obvious especially.Flicker noise in the voltage signal can reduce picture quality significantly.
Summary of the invention
Therefore, a kind of imageing sensor that has than low flash noise need be provided.
The inventor is through discovering that traditional cmos image sensor often adopts the surface channel transistor source of being used as to follow transistor.Follow in the transistor in this provenance, conducting channel is positioned at substrate surface, and near the gate oxide on the substrate.Yet the interface of substrate and gate oxide forms interfacial state easily, and this interfacial state can be captured randomly or discharged charge carrier, thereby causes the variation of channel current, and then in the voltage signal of transistor output is followed in the source, introduces flicker noise.
In order to address the above problem, according to an aspect of the present invention, a kind of imageing sensor is provided.This imageing sensor comprises pel array, and the one or more pixel cells in this pel array comprise that a source follows transistor, and it is junction field effect transistor that transistor is followed in said source, and it comprises: first conductivity type substrate; Second conductive type of trap is arranged in said first conductivity type substrate; The second conduction type deposit doped layer, be positioned at outside the said first conductivity type substrate surface and at least part be positioned on said second conductive type of trap; The first conduction type source region is arranged in said second conductive type of trap; The first conduction type drain region is arranged in said first conductivity type substrate and/or is arranged in said second conductive type of trap; The first conduction type doped layer; At least part is between said second conductive type of trap and the said second conduction type deposit doped layer; So that the said first conduction type source region is electrically connected with the said first conduction type drain region, and between itself and said second conductive type of trap with and and the said second conduction type deposit doped layer between form PN junction respectively.
Imageing sensor than prior art; Follow transistor owing to adopted junction field effect transistor to substitute surperficial channel MOS transistor as the source; This has been avoided the charge carrier in the conducting channel to be captured at random because of oxide layer-Semiconductor substrate interfacial state at the interface or discharge; Thereby effectively reduced the flicker noise in the voltage signal of exporting, and then improved the image quality of imageing sensor.In addition, in this junction field effect transistor, the PN junction of conducting channel one side is to form through the second conduction type deposit doped layer and the first conduction type doped layer contacted with it that is positioned at outside the first conductivity type substrate surface.Because the edge of the second conduction type deposit doped layer can form through for example dry etching, its profile is easy to control, therefore adopt the imageing sensor reliability of this junction field effect transistor higher, and the performance difference between the different pixels unit is less.
In one embodiment, the said second conduction type deposit doped layer comprises doped polycrystalline silicon layer or amorphous silicon layer.The polysilicon of this doping or amorphous silicon can be formed on outside the first conductivity type substrate surface through chemical vapor deposition mode or other deposit modes that is fit to, and need not to be formed in first conductivity type substrate through the ion injection mode.This can reduce the primary ions injection, thereby has reduced the cost of manufacture of imageing sensor.In addition, owing to reduced the primary ions injection, thereby the source follows that the profile of conducting channel is easy to control in the transistor, and can be owing to the annealing number of times too much causes darker junction depth to influence its performance.Therefore, this source is followed transistor and need not in first conductivity type substrate outside its conducting channel to make darker isolation channel and isolate adjacent area, and this can reduce the manufacture craft difficulty, and reduces the area of imageing sensor.
In one embodiment; Part is overlapped at least outside the said first conduction type doped layer for said second conductive type of trap and the said second conduction type deposit doped layer, so that said second conductive type of trap is electrically connected with the said second conduction type deposit doped layer each other.
In one embodiment, the said first conduction type drain region and/or the first conduction type doped layer part at least are positioned at outside said second conductive type of trap, so that the said first conduction type drain region is electrically connected with said first conductivity type substrate.
In one embodiment, the edge of the said second conduction type deposit doped layer is arranged on the surperficial dielectric layer of first conductivity type substrate or is positioned on the isolated groove of first conductivity type substrate.In the process of the etching second conduction type doped layer; Dielectric layer between its edge and first conductivity type substrate can so that the etching stopping of the second conduction type doped layer on the dielectric layer or on the isolated groove, thereby avoid the damage of first conductivity type substrate and the damage of the transistor that brings thus.
According to a further aspect in the invention, a kind of transistorized manufacture method is provided also, has comprised the steps: to provide first conductivity type substrate, mixing in said first conductivity type substrate is formed with second conductive type of trap; In said first conductivity type substrate and/or said second conductive type of trap, mix and form the first conduction type doped layer; Form the second conduction type deposit doped layer; It is positioned at outside the said first conductivity type substrate surface and at least partly is positioned on the said first conduction type doped layer, so that form PN junction between said second conduction type deposit doped layer and the said first conduction type doped layer; In said second conductive type of trap, form the first conduction type source region; And form the first conduction type drain region in said second conductive type of trap and/or in said first conductivity type substrate, so that the said first conduction type source region is electrically connected with the said first conduction type drain region.
In one embodiment, the edge of the said second conduction type deposit doped layer is arranged on the surperficial dielectric layer of first conductivity type substrate or is positioned on the isolated groove of first conductivity type substrate.
In one embodiment, before the step that forms the said second conduction type deposit doped layer, also comprise: form said dielectric layer and/or in said first conductivity type substrate, form isolated groove on said first conductivity type substrate surface; And the step of the said formation second conduction type deposit doped layer further comprises: the said dielectric layer of partial etching, so that the said first conduction type doped layer at least partly exposes; Polysilicon that deposit is mixed on the said first conduction type doped layer that exposes or amorphous silicon are to form the said second conduction type deposit doped layer; And the said second conduction type deposit doped layer of partial etching and make the second conduction type deposit doped layer edge be etched be positioned on the said dielectric layer and/or on the said isolated groove.
In one embodiment, the step of said partial etching dielectric layer further comprises: the said dielectric layer of partial etching, so that said first conduction type doped layer and said second conductive type of trap at least partly expose.
In one embodiment; The polysilicon that said deposit is mixed or the step of amorphous silicon further comprise: polysilicon or amorphous silicon to institute's deposit in said polysilicon of deposit or amorphous silicon mix; Perhaps after said polysilicon of deposit or amorphous silicon, the polysilicon or the amorphous silicon of institute's deposit mixed.
Above characteristic of the present invention and other characteristics are partly set forth embodiment hereinafter clearly.
Description of drawings
Through with reference to the detailed description of being done below the advantages, can more easily understand characteristic of the present invention, purpose and advantage to non-limiting example.Wherein, same or analogous Reference numeral is represented same or analogous device.
Fig. 1 shows a kind of 4T dot structure of traditional cmos imageing sensor;
Fig. 2 shows imageing sensor 200 according to an embodiment of the invention;
Fig. 3 a shows the source of imageing sensor 200 among Fig. 2 and follows a transistorized example 300;
Fig. 3 b shows the source of imageing sensor 200 among Fig. 2 and follows transistorized another example;
Fig. 4 a shows the source of imageing sensor 200 among Fig. 2 and follows transistorized another example 400;
Fig. 4 b shows the source of Fig. 4 a and follows the generalized section of transistor along AA ' direction;
Fig. 5 a shows transistorized according to an embodiment of the invention manufacture method 500;
Fig. 5 b to Fig. 5 e shows the generalized section of the manufacture method 500 among Fig. 5 a.
Embodiment
Go through enforcement and the use of embodiment below.Yet, should be appreciated that the specific embodiment discussed only exemplarily explanation implement and use ad hoc fashion of the present invention, and unrestricted scope of the present invention.
With reference to figure 2; Show imageing sensor 200 according to an embodiment of the invention; This imageing sensor 200 comprises pel array, and each pixel cell in this pel array comprises: photodiode 201 is used to respond to light intensity and changes and generate corresponding image charge signal; Transfering transistor 202 is used for transition diagram image charge signal; And the source follows transistor 204, is used for based on the image charge signal formation voltage signal that is shifted, and wherein, it is junction field effect transistors that transistor 204 is followed in this source.
Need to prove that in some instances, a plurality of pixel cells in the pel array can have a source and follow transistor 204, for example adjacent 2,4 or more a plurality of pixel cell can be followed transistor 204 with output voltage signal in a shared source.In addition, in the present embodiment, it is p type field effect transistors that transistor 204 is followed in the source.It will be understood by those skilled in the art that in other embodiment, the source is followed transistor 204 and also can be n type field effect transistor.
Particularly, photodiode 201 is coupled to reference potential line VSS, for example or the negative supply current potential, and between the source electrode of transfering transistor 202, is used to respond to light intensity and changes and form corresponding image charge signal.The drain electrode of transfering transistor 202 links to each other with the grid that transistor 204 is followed in the source; The grid of this transfering transistor 202 is used for receiving transfer control signal TX; Under the control of shifting control signal TX; Transfering transistor 202 corresponding conducting or shutoffs, thus the image charge signal that makes photodiode 201 responded to is read into the floating diffusion region of the drain electrode that is coupled in this transfering transistor 202, and by this floating diffusion region memory image charge signal.
The source is followed transistor 204 and is coupled between reference potential line VSS and the bias current sources 205; Its drain electrode is coupled to reference potential line VSS; Its source electrode is coupled to this bias current sources 205 and is used for output voltage signal; Its grid is coupled to the drain electrode of transfering transistor 202, promptly is couple to floating diffusion region, to obtain the image charge signal that transfering transistor 202 is shifted.Under the biasing of bias current sources 205, the voltage follow that transistor 204 source electrodes are followed in the source the image charge signal that its grid obtains and is changed and change, and its voltage gain approaches 1.In one embodiment, the source electrode that transistor 204 is followed in the source further is couple to the bit line (not shown) through the row selecting transistor (not shown), and this voltage signal is offered the signal processing circuit of imageing sensor.
In one embodiment, this imageing sensor also comprises reset transistor 203, and the drain electrode of this reset transistor 203 is used to receive reset signal RSG, and its source electrode is couple to the drain electrode of transfering transistor 202 and the grid that transistor 204 is followed in the source.The grid of this reset transistor 203 is used to receive reseting controling signal RST, under the control of this reseting controling signal RST, and reset transistor 203 corresponding conducting or shutoffs, thus to the grid that transistor 204 is followed in the source reset signal is provided.In this embodiment; Transfering transistor 202 is nmos pass transistor with reset transistor 203, is appreciated that in other embodiment; Transfering transistor 202 and reset transistor 203 also can adopt the transistor of other types, for example PMOS transistor or technotron.
Follow transistor 204 owing to adopted junction field effect transistor to substitute surperficial channel MOS transistor as the source; This has been avoided the charge carrier in the conducting channel to be captured at random because of oxide layer-Semiconductor substrate interfacial state at the interface or discharge; Thereby effectively reduced the flicker noise in the voltage signal of exporting, and then improved the image quality of imageing sensor 200.
After reset capacitance 213 and image electric capacity 211 were stored the electric charge corresponding to reset signal and image charge signal respectively, amplifying unit 215 amplified the voltage difference on these two electric capacity, and the output voltage that will pass through amplification offers follow-up treatment circuit.
Fig. 3 a shows the source of imageing sensor 200 among Fig. 2 and follows a transistorized example 300, and wherein to follow transistor be p type field effect transistor in this source.It should be understood by one skilled in the art that its operation principle is equally applicable to the source and follows the situation that transistor is a n type field effect transistor.
Shown in Fig. 3 a, this source is followed transistor and is comprised:
N type deposit doped layer 305, it is positioned at outside P type substrate 301 surfaces, and part is positioned on the N type trap 303 at least;
P type source region 307, it is arranged in N type trap 303;
P type drain region 309, it is arranged in P type substrate 301 and/or N type trap 303;
P type doped layer 311; It is at least partly between N type trap 303 and N type deposit doped layer 305; So that P type source region 307 is electrically connected with P type drain region 309; And make P type source region 307 be electrically connected with P type drain region 309, and between P type doped layer 311 and N type trap 303, and between this P type doped layer 311 and N type deposit doped layer 305, form PN junction respectively.
Particularly, P type substrate 301 can be the semiconductor wafer that the P type mixes, or the silicon-on-insulator (SOI) of P type doping, or the P type well region in the semiconductor wafer of N type doping, perhaps other similar substrate or well regions.
P type source region 307 all is arranged in N type trap 303.This N type trap 303 makes P type source region 307 and P type substrate 301 isolate each other.Because source region 307 is used for output voltage signal, it possibly have higher current potential, and P type substrate 301 is couple to reference potential line usually, for example.Therefore, the substrate break-through can be avoided with the 301 mutual isolation of P type substrate in source region 307, follows transistorized operate as normal to guarantee the source.
According to the difference of specific embodiment, this P type drain region 309 can all be arranged in the P type substrate 301 outside the N type trap 303; Perhaps all be arranged in N type trap 303; Perhaps a part is positioned at N type trap 303, and another part is arranged in the P type substrate 301 outside the N type trap 303.In the example shown in Fig. 3 a 300, P type drain region 309 all is arranged in N type trap 303, thereby it is electrically connected through the P type doped layer 311 in the N type trap 303 with P type source region 307 each other.In practical application, (overlap) overlapped to realize being electrically connected therebetween with P type doped layer 311 respectively each other in this P type source region 307 and P type drain region 309.Corresponding with P type doped layer 311, N type deposit doped layer 305 also can be positioned on the N type trap 303 whole or in part, and between source region 307 and drain region 309.In the example 300 of Fig. 3 a, the Butut (layout) of this N type deposit doped layer 305 all is positioned at the Butut of N type trap 303.
P type doped layer 311 is between N type trap 303 and N type deposit doped layer 305, and electrical connection P type source region 307 and P type drain region 309.Because P type doped layer 311 part at least is arranged in N type trap 303, thereby this P type doped layer 311 contacts with N type trap 303, thereby near its contact interface, formed a PN junction of technotron.In addition, P type doped layer 311 also at least partly is in contact with one another with position N type deposit doped layer 305 on it, thereby near its contact interface, has formed another PN junction of technotron.This makes N type trap 303 and N type deposit doped layer 305 act as this source and follows transistorized grid, and the conducting channel district of transistor 300 is followed in the source of being, zone between two PN junctions.When transistor work is followed in the source; The different meetings of the voltage difference between N type deposit doped layer 305 (and N type trap 303) and source region 307 and the drain region 309 cause the change width of the knot space charge region of these two PN junctions; Promptly change the conducting channel thickness of technotron, and then changed the size of channel current.Need to prove,, promptly constitute, thereby the interfacial state defective of its contact-making surface position is far fewer than the interfacial state defective of oxide layer-substrate interface by silicon because P type doped layer 311 adopts identical materials with N type deposit doped layer 305.Because channel current is in the P type doped layer 311 away from P type substrate 301 surfaces; It can not receive the interfacial state effect of P type substrate 301 surface oxide layers-substrate interface basically; Thereby greatly reduce the probability that charge carrier was captured or discharged to the interfacial state defective at random, and then effectively reduced the source and followed the flicker noise in the transistor output voltage signal.
In certain embodiments; Electrically contacting between N type deposit doped layer 305 and the P type doped layer 311 can be through removing the dielectric layer 304 on P type substrate 301 surfaces; Oxide layer for example; Realize that is: P type substrate 301 surfaces are formed with layer of oxide layer usually, can the oxide layer of P type doped layer 311 tops partly be removed so that this P type doped layer 311 is exposed from P type substrate 301 surfaces; Afterwards, polysilicon that deposit is for example mixed on P type substrate 301 again or amorphous silicon are to form this N type deposit doped layer 305.This dielectric layer 304 can be pre-formed on P type substrate 301 surfaces.Because the isolation of dielectric layer 304, N type deposit doped layer 305 only contacts with P type doped layer 311 and constitutes PN junction, and can not electrically contact with P type source region 307 and P type drain region 309.In some instances, doped polycrystalline silicon layer or amorphous silicon layer can mix to this polysilicon or amorphous silicon when being deposited in the lump, promptly in the reaction cavity of deposit, add the gas with dopant ion.This does not just need to mix with the mode of ion injection to form N type deposit doped layer 305 again, and this can reduce the primary ions injection, thereby reduces the cost of manufacture of imageing sensor.Be appreciated that at some in other the example that N type deposit doped layer 305 also can form through following manner: first deposit polysilicon or amorphous silicon, polysilicon or the amorphous silicon to institute's deposit mixes again, for example injects with ion or diffusion way mixes.
In addition, N type deposit doped layer 305 for example can adopt dry etching to control, and its profile is easy to control, therefore adopts imageing sensor 300 reliabilities of this technotron higher.Preferably, in the embodiment shown in Fig. 3 a, the edge of N type deposit doped layer 305 is positioned on the dielectric layer 304.This dielectric layer 304 makes N type deposit doped layer 305 edges and P type substrate 301 isolate.In the process of etching N type deposit doped layer 305; Dielectric layer 304 between its edge and the P type substrate 301 can so that the etching stopping of N type deposit doped layer 305 on dielectric layer 304, thereby avoid the damage of P type substrate 301 and the damage of the transistor that brings thus.In some instances, the part that N type deposit doped layer 305 contacts with P type substrate 301 is positioned at the window of dielectric layer 304, and its edge exceeds this dielectric layer 304 window edge certain-lengths, for example 5 nanometers, 10 nanometers, 50 nanometers, or the like.
In some instances, N type trap 303 can be overlapped in P type doped layer 311 exterior portions with N type deposit doped layer 305, thereby make N type trap 303 be electrically connected each other with N type deposit doped layer 305.This just need in N type trap 303, not make extra through hole or other structures are drawn N type trap 303, thereby has reduced cost of manufacture.Be appreciated that in other examples N type trap 303 can directly not contact with N type deposit doped layer 305 each other yet, but is electrically connected through the through hole in the dielectric layer 304.
Fig. 3 b shows the source of imageing sensor 200 among Fig. 2 and follows transistorized another example.In Fig. 3 b, also show the photodiode of imageing sensor 200, it is by P type substrate 301 and be positioned at the outer N type doped regions 321 of N type trap 303 and constitute.
Shown in Fig. 3 b, also comprise isolated groove 323 in the P type substrate 301, it is positioned at outside the N type trap 303, promptly between N type doped region 321 and N type trap 303.Isolated groove 323 adopts insulating material, and for example silica, silicon nitride form, thereby have electric isolation effect preferably.Isolated groove 323 in the P type substrate 301 makes N type doped region 321 and N type trap 303 isolate each other, and it can effectively be avoided negative pole and the source of photodiode to follow between the transistorized grid being short-circuited (being break-through) and influence the operation of imageing sensor.Can find out that owing to reduced the primary ions injection, the profile of conducting channel is easy to control, and can be owing to the annealing number of times too much causes darker junction depth.Therefore; This imageing sensor need not to make in the P type substrate 301 outside conducting channel darker isolation channel and isolates adjacent area; Be that isolated groove 323 can adopt fleet plough groove isolation structure (Shallow Trench Isolation); Its chip area that takies is less relatively, thereby can effectively reduce the area of imageing sensor.
In a preferred embodiment, isolated groove 323 can be adjacent with P type source region 307 and/or N type doped region 321, and this can further reduce the area of imageing sensor, thereby improve chip integration.Especially, in the example shown in Fig. 3 b, isolated groove 323 is adjacent with N type trap 303 and P type source region 307, and this makes the N type trap 303 and the contact area of P type substrate 301 reduce, thereby has effectively reduced the parasitic capacitance between N type trap 303 and the P type substrate 301.In imageing sensor, N type trap 303 can be coupled to the floating diffusion region of imageing sensor.Be appreciated that the parasitic capacitance between N type trap 303 and the P type substrate 301 is more little, the sensitivity of imageing sensor is also high more.The sensitivity that therefore, can further improve imageing sensor with N type trap 303 and P type source region 307 adjacent isolated grooves 323.
In addition, in certain embodiments, the edge of N type deposit doped layer 305 also can be positioned on the isolated groove 323.This isolated groove 323 makes N type deposit doped layer 305 edges and P type substrate 301 isolate.In the process of etching N type deposit doped layer 305; Isolated groove 323 between its edge and the P type substrate 301 can so that the etching stopping of N type deposit doped layer 305 on isolated groove 323, thereby avoid the damage of P type substrate 301 and the damage of the transistor that brings thus.
Fig. 4 a and Fig. 4 b show the source of imageing sensor 200 among Fig. 2 and follow transistorized another example 400.Wherein, Fig. 4 b is that the generalized section of transistor along AA ' direction followed in the source among Fig. 4 a.
Shown in Fig. 4 a and Fig. 4 b, this source follow transistor have with Fig. 3 a in the source follow structure like the transistor-like.But this source is followed transistorized drain region 409 and is arranged in the P type substrate 401 outside the N type trap 403, and this makes P type impure drain region 409 be electrically connected with P type substrate 401.In practical application, this drain region 409 all is coupled to reference potential line with P type substrate 401, for example, does not therefore have voltage difference therebetween, thereby can between drain region 409 and P type substrate 401, not form electric current.
Correspondingly, P type doped layer 411 is extended in the P type substrate 401 by N type trap 403 at least in part, so that this P type substrate 401 is electrically connected source region 407 and drain region 409 jointly with P type doped layer 411.Like this, when transistor turns was followed in this source, channel current can flow to source region 407 through these P type substrates 401 and P type doped layer 411 by drain region 409.
Especially, for imageing sensor 200, it has a plurality of pixel cells usually, follows transistor and each pixel cell all has the source.Follow transistorized drain region 409 for these sources, can have part or all of drain region 409 all to be arranged in the P type substrate 401 outside the N type trap 403 at least in part.Like this, these are positioned at N type trap 403 outer drain regions 409 can have the current potential that equates with P type substrate 401, thereby it has equal current potential each other.Thereby this can for example can share ground connection through P type substrate 401 so that under the situation that does not increase chip area, improved the effect of ground connection, and this is just avoided different pixels unit earthing potential inconsistent, thereby has further improved the performance of imageing sensor.
With reference to figure 4a, part is overlapped at least outside P type doped layer 411 with N type deposit doped layer 405 for N type trap 403, thereby makes N type trap 403 be electrically connected each other with N type deposit doped layer 405.Just need in N type trap 403, not make extra through hole draws N type trap 403 for this, thereby has reduced cost of manufacture.
Fig. 5 a shows transistorized according to an embodiment of the invention manufacture method 500.
Shown in Fig. 5 a, this manufacture method 500 comprises:
Execution in step S501 provides first conductivity type substrate, and mixing in this first conductivity type substrate is formed with second conductive type of trap;
Execution in step S503, in first conductivity type substrate and/or second conductive type of trap, mixing forms the first conduction type doped layer;
Execution in step S505; Form the second conduction type deposit doped layer; It is positioned at outside the first conductivity type substrate surface and at least partly is positioned on the first conduction type doped layer, so that form PN junction between the second conduction type deposit doped layer and the first conduction type doped layer;
Execution in step S507; In second conductive type of trap, form the first conduction type source region; And form the first conduction type drain region in second conductive type of trap and/or in first conductivity type substrate, so that the first conduction type source region is electrically connected with the first conduction type drain region.
Be appreciated that the source that this transistorized manufacture method 500 can be used for the construction drawing image-position sensor follows transistor.In practical application, the technology of construction drawing image-position sensor also comprises photodiode and other transistors that forms in the image sensor pixel cells, and for example the step of transfering transistor, reset transistor, row selecting transistor repeats no more at this.
In some instances, the edge of the second conduction type deposit doped layer is positioned on the dielectric layer on first conductivity type substrate surface, perhaps is arranged on the isolated groove of first conductivity type substrate.In the process of the etching second conduction type deposit doped layer; Dielectric layer between its edge and first conductivity type substrate or isolated groove can be so that the etching of the second conduction type deposit doped layer be from stopping on dielectric layer or the isolated groove, thus the transistor damage of avoiding the etching injury of first conductivity type substrate and bringing thus.
In some instances, before step S505, also comprise: form dielectric layer and/or in first conductivity type substrate, form isolated groove on first conductivity type substrate surface; And the step that forms the second conduction type deposit doped layer further comprises: the partial etching dielectric layer, so that the first conduction type doped layer at least partly exposes; Polysilicon that deposit is mixed on the first conduction type doped layer that exposes or amorphous silicon are to form the second conduction type deposit doped layer; And the partial etching second conduction type deposit doped layer and make the second conduction type deposit doped layer edge be etched be positioned on the dielectric layer and/or on the isolated groove.
In one embodiment, the step of partial etching dielectric layer further comprises: the partial etching dielectric layer is so that the first conduction type doped layer and second conductive type of trap at least partly expose.Thereby, need be on the first conduction type doped layer that exposes and second conductive type of trap polysilicon that mixes of deposit or amorphous silicon to form the second conduction type deposit doped layer.The second conduction type electrode doped layer that is formed directly on second conductive type of trap can electrically contact with second conductive type of trap under it; Thereby can this second conductive type of trap electricity be drawn, and need not to make through hole or other electric connection structures are drawn this second conductive type of trap.
Fig. 5 b to Fig. 5 e shows the generalized section of the manufacture method 500 of Fig. 5 a.Wherein, the transistor of these manufacture method 500 formation is a p type field effect transistor.It should be understood by one skilled in the art that its operation principle is equally applicable to the situation that transistor is a n type field effect transistor.Next, with reference to figure 5a to Fig. 5 e, an embodiment of this transistorized manufacture method 500 of being used for the construction drawing image-position sensor is detailed.
Shown in Fig. 5 b, P type substrate 501 is provided, be formed with photodiode region 502 and N type trap 503 in this P type substrate 501.This N type trap 503 and photodiode region 502 are separated from each other through P type substrate 501 therebetween.
Afterwards, shown in Fig. 5 c, form P type doped layer 511, it at least partly is arranged in N type trap 503.In Fig. 5 c, P type doped layer 511 all is arranged in N type trap 503.In addition, N type trap 503 and between P type doped layer 511 wherein, constituted a transistorized PN junction.In certain other embodiments, P type doped layer 511 also can be positioned partially in the P type substrate 501, and is positioned partially in the N type trap 503.Need to prove; The step that forms P type doped layer 511 and N type trap 503 adopts ion to inject usually and realizes, after each ion injects, also need carry out annealing in process to this P type substrate 501; For example short annealing is handled, and injects the lattice defect that causes with active ions and minimizing.
Then, form dielectric layer 504 on P type substrate 501 surfaces.This dielectric layer 504 for example is silica or other dielectric materials, can form this dielectric layer 504 through for example oxidation technology or depositing technics.Alternatively, in some instances, can also in P type substrate 501, form the isolated groove (not shown), this isolated groove is usually located at outside the N type trap 511.
Then, shown in Fig. 5 d, form N type deposit doped layer 505, it is positioned at, and P type substrate 501 surfaces are outer also at least partly to be positioned on the N type trap 503, so that form PN junction between the P type doped layer 511 in N type deposit doped layer 505 and the N type trap 503.
Particularly, this N type deposit doped layer 505 can form through following step: at first, partial etching dielectric layer 504, on P type substrate 501, to form window, this window makes P type doped layer 511 at least partly expose; Then, polysilicon that deposit is mixed on the P type doped layer 511 that exposes or amorphous silicon are to form N type deposit doped layer 505; Afterwards; Partial etching N type deposit doped layer 505 also makes N type deposit doped layer 505 edges be positioned on the dielectric layer 504; Perhaps make the edge of N type deposit doped layer 505 be positioned on the isolated groove, promptly make the edge of this N type deposit doped layer 505 not be located immediately on the P type substrate 501.In some instances, can pass through chemical vapor deposition method deposit polysilicon or amorphous silicon, and in this polysilicon of deposit or amorphous silicon doping P type ion, for example phosphorus or arsenic ion are to form polysilicon or the amorphous silicon that mixes.In other examples, can pass through chemical vapor deposition method deposit polysilicon or amorphous silicon, afterwards, and doping P type ion in the polysilicon of institute's deposit or amorphous silicon, the mode of for example injecting through diffusion or ion is mixed.In also having some examples; Can pass through chemical vapor deposition method deposit polysilicon or amorphous silicon earlier; The then polysilicon or the amorphous silicon of the deposit of partial etching institute carried out ion to the polysilicon that is etched or amorphous silicon more afterwards and inject the impurity ion before or after forming source region and drain region.
In a preferred embodiment, N type deposit doped layer 505 also is formed directly on the N type trap 503.Correspondingly, dielectric layer 504 is etched to and makes P type doped layer 511 and N type trap 503 at least partly expose, and deposit is mixed on P type doped layer that exposes 511 and N type trap 503 polysilicon or amorphous silicon form N type deposit doped layer.
Can find out that through this dielectric layer window, the polysilicon of institute's deposit can directly contact with the P type doped layer 511 under it, thereby form the PN junction of junction field effect transistor conducting channel opposite side.This PN junction limits the conducting channel of this junction field effect transistor jointly together with the PN junction between P type doped layer 511 and the N type trap 503, and N type trap 503 and N type deposit doped layer 505 are then jointly as two grids of junction field effect transistor.
Then, shown in Fig. 5 e, in N type trap 503, form P type source region 507 and P type drain region 509, and make this P type source region 507 and P type drain region 509 be electrically connected each other.In the example of Fig. 5 e, P type source region 507 and P type drain region 509 are electrically connected through P type doped layer 511 therebetween.Be appreciated that; In certain embodiments; P type drain region 509 also can be formed on the P type substrate 501 outside the N type trap 503; This P type drain region 509 can be electrically connected to N type trap 503 through the P type substrate 501 between itself and the N type trap 503, and is electrically connected to P type source region 507 through P type doped layer 511 further.
Can find out, form because this N type deposit doped layer 505 can pass through depositing technics, and need not to be formed in the P type substrate 501 through the ion injection mode.This can reduce primary ions injection and annealing in process, thereby has reduced transistorized cost of manufacture.In addition, owing to reduced the primary ions injection, the profile of conducting channel is easy to control, and can be owing to the annealing number of times too much causes darker junction depth.Therefore; This junction field effect transistor need not to make in the P type substrate 501 outside conducting channel darker isolation channel and isolates adjacent area; For example between N type trap 503 and the photodiode region 502, this can reduce the manufacture craft difficulty, and reduces transistorized area.
Although in accompanying drawing and aforesaid description sets forth in detail with the present invention has been described, should think that this is illustrated and describes is illustrative and exemplary, rather than restrictive; The invention is not restricted to above-mentioned execution mode.
The those skilled in the art in those present technique fields can be through research specification, disclosed content and accompanying drawing and appending claims, and understanding and enforcement are to other changes of the execution mode of disclosure.In claim, word " comprises " element and the step of not getting rid of other, and wording " one " is not got rid of plural number.In the practical application of invention, the function of a plurality of technical characterictics of being quoted during a part possibility enforcement of rights requires.Any Reference numeral in the claim should not be construed as the restriction to scope.
Claims (10)
1. an imageing sensor is characterized in that, comprises pel array, and the one or more pixel cells in the said pel array comprise that a source follows transistor, and it is junction field effect transistor that transistor is followed in said source, and it comprises:
First conductivity type substrate;
Second conductive type of trap is arranged in said first conductivity type substrate;
The second conduction type deposit doped layer, be positioned at outside the said first conductivity type substrate surface and at least part be positioned on said second conductive type of trap;
The first conduction type source region is arranged in said second conductive type of trap;
The first conduction type drain region is arranged in said first conductivity type substrate and/or is arranged in said second conductive type of trap;
The first conduction type doped layer; At least part is between said second conductive type of trap and the said second conduction type deposit doped layer; So that the said first conduction type source region is electrically connected with the said first conduction type drain region, and between itself and said second conductive type of trap with and and the said second conduction type deposit doped layer between form PN junction respectively.
2. imageing sensor according to claim 1 is characterized in that, the said second conduction type deposit doped layer comprises doped polycrystalline silicon layer or amorphous silicon layer.
3. imageing sensor according to claim 1; It is characterized in that; Part is overlapped at least outside the said first conduction type doped layer for said second conductive type of trap and the said second conduction type deposit doped layer, so that said second conductive type of trap is electrically connected with the said second conduction type deposit doped layer each other.
4. imageing sensor according to claim 1; It is characterized in that; Said first conduction type drain region and/or the said first conduction type doped layer part at least are positioned at outside said second conductive type of trap, so that the said first conduction type drain region is electrically connected with first conductivity type substrate.
5. imageing sensor according to claim 1 is characterized in that, the edge of the said second conduction type deposit doped layer is arranged on the surperficial dielectric layer of first conductivity type substrate or is positioned on the isolated groove of first conductivity type substrate.
6. a transistorized manufacture method is characterized in that, comprises the steps:
First conductivity type substrate is provided, and mixing in said first conductivity type substrate is formed with second conductive type of trap;
In said first conductivity type substrate and/or said second conductive type of trap, mix and form the first conduction type doped layer;
Form the second conduction type deposit doped layer; It is positioned at outside the said first conductivity type substrate surface and at least partly is positioned on the said first conduction type doped layer, so that form PN junction between said second conduction type deposit doped layer and the said first conduction type doped layer;
In said second conductive type of trap, form the first conduction type source region; And form the first conduction type drain region in said second conductive type of trap and/or in said first conductivity type substrate, so that the said first conduction type source region is electrically connected with the said first conduction type drain region.
7. manufacture method according to claim 6 is characterized in that, the edge of the said second conduction type deposit doped layer is arranged on the surperficial dielectric layer of first conductivity type substrate or is positioned on the isolated groove of first conductivity type substrate.
8. manufacture method according to claim 7 is characterized in that,
Before the step that forms the said second conduction type deposit doped layer, also comprise: form said dielectric layer and/or in said first conductivity type substrate, form isolated groove on said first conductivity type substrate surface;
And the step of the said formation second conduction type deposit doped layer further comprises:
The said dielectric layer of partial etching is so that the said first conduction type doped layer at least partly exposes;
Polysilicon that deposit is mixed on the said first conduction type doped layer that exposes or amorphous silicon are to form the said second conduction type deposit doped layer; And
The said second conduction type deposit doped layer of partial etching also makes the second conduction type deposit doped layer edge be etched be positioned on the said dielectric layer and/or on the said isolated groove.
9. manufacture method according to claim 8 is characterized in that, the step of said partial etching dielectric layer further comprises: the said dielectric layer of partial etching, so that said first conduction type doped layer and said second conductive type of trap at least partly expose.
10. manufacture method according to claim 8; It is characterized in that; The polysilicon that said deposit is mixed or the step of amorphous silicon further comprise: polysilicon or amorphous silicon to institute's deposit in said polysilicon of deposit or amorphous silicon mix; Perhaps after said polysilicon of deposit or amorphous silicon, the polysilicon or the amorphous silicon of institute's deposit mixed.
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| WO2013178078A1 (en) * | 2012-06-01 | 2013-12-05 | 格科微电子（上海）有限公司 | Image sensor and transistor manufacturing method |
| CN103928485A (en) * | 2014-05-08 | 2014-07-16 | 重庆大学 | X-ray image sensor with high output amplitude |
| CN105304665A (en) * | 2015-10-29 | 2016-02-03 | 上海华力微电子有限公司 | CMOS image sensor for improving full-well capacity of pixel unit |
| WO2021189619A1 (en) * | 2020-03-23 | 2021-09-30 | 中山大学 | Photoelectric sensor, random-readable active pixel circuit, image sensor and camera device |
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