CN202633312U - Image sensor and source follower - Google Patents
Image sensor and source follower Download PDFInfo
- Publication number
- CN202633312U CN202633312U CN 201220044374 CN201220044374U CN202633312U CN 202633312 U CN202633312 U CN 202633312U CN 201220044374 CN201220044374 CN 201220044374 CN 201220044374 U CN201220044374 U CN 201220044374U CN 202633312 U CN202633312 U CN 202633312U
- Authority
- CN
- China
- Prior art keywords
- trap
- type
- source
- transistor
- conductive type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The utility model discloses an image sensor and a source follower. The image sensor comprises a photodiode used for sensing the light intensity change to generate corresponding image charge signals, a transfer transistor used for transferring image charge signals, and a source following transistor for generating voltage signals based on the transferred image charge signals, wherein the source following transistor is a junction field-effect transistor. Compared with the conventional image sensor that employs the prior art, the image sensor of the utility model adopts the junction field-effect transistor to replace the surface channel MOS transistor as the source following transistor, thereby preventing the carriers in the conductive channel from being randomly captured or released due to the interface state of one semiconductor substrate interface of the oxide layer, effectively reducing the flicker noise in the output voltage signals, and accordingly improving the imaging quality of the image sensor.
Description
Technical field
The utility model relates to technical field of semiconductors, and more specifically, the utility model relates to a kind of imageing sensor and source follower.
Background technology
The traditional image transducer can be divided into two types usually: charge coupled device (Charge Coupled Device, CCD) imageing sensor and complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor.Wherein, Cmos image sensor has advantages such as volume is little, low in energy consumption, production cost is low; Therefore, cmos image sensor for example is easy to be integrated in the mancarried electronic aids such as mobile phone, notebook computer, panel computer, uses as the shooting module that the digital imagery function is provided.
Cmos image sensor adopts the dot structure of 3T or 4T usually.Fig. 1 promptly shows a kind of 4T dot structure of traditional cmos imageing sensor, comprises that photodiode 11, transfering transistor 12, reset transistor 13, source follow transistor 14 and row selecting transistor 15.Wherein, photodiode 11 is used to respond to the light intensity variation and forms corresponding image charge signal.Transfering transistor 12 is used for receiving transfer control signal TX; Under the control of shifting control signal TX; Transfering transistor 12 corresponding conducting or shutoffs; Thereby the image charge signal that makes photodiode 11 responded to is read into the floating diffusion region (floating diffusion) that couples with 12 drain electrodes of this transfering transistor, and then by this floating diffusion region memory image charge signal.Reset transistor 13 is used to receive reseting controling signal RST, under the control of this reseting controling signal RST, and reset transistor 13 corresponding conducting or shutoffs, thus to the grid that transistor 14 is followed in the source reset signal is provided.It is voltage signal that the image charge conversion of signals that transistor 14 is used for transfering transistor 12 is obtained is followed in the source, and this voltage signal can output on the bit line BL through row selecting transistor 15.
Yet, often have bigger flicker noise in the voltage signal of traditional cmos imageing sensor output, when light was more weak, this flicker noise was more obvious especially.Flicker noise in the voltage signal can reduce picture quality significantly.
The utility model content
Therefore, a kind of imageing sensor that has than low flash noise need be provided.
The inventor is through discovering that traditional cmos image sensor often adopts the surface channel transistor source of being used as to follow transistor.Follow in the transistor in this provenance, conducting channel is positioned at substrate surface, and near the gate oxide on the substrate.Yet substrate forms easily interfacial state near the zone of gate oxide, and this interfacial state can be captured randomly or discharged charge carrier, thereby causes the variation of channel current, and then in the voltage signal of transistor output is followed in the source, introduces flicker noise.
In order to address the above problem, an aspect according to the utility model provides a kind of imageing sensor, comprising: photodiode is used to respond to light intensity and changes and generate corresponding image charge signal; Transfering transistor is used for transition diagram image charge signal; Transistor is followed in the source, is used for based on the image charge signal formation voltage signal that is shifted, and wherein, it is junction field effect transistor that transistor is followed in this source.
Imageing sensor than prior art; Follow transistor owing to adopted junction field effect transistor to substitute surperficial channel MOS transistor as the source; This has been avoided the charge carrier in the conducting channel to be captured at random because of oxide layer-Semiconductor substrate interfacial state at the interface or discharge; Thereby effectively reduced the flicker noise in the voltage signal of exporting, and then improved the image quality of imageing sensor.
In one embodiment, this source is followed transistor and is comprised: first conductivity type substrate; Second conductive type of trap is arranged in said first conductivity type substrate; The second conduction type doped layer, part is arranged in said second conductive type of trap at least; The first conduction type source region is arranged in said second conductive type of trap; The first conduction type drain region is arranged in said first conductivity type substrate and/or is arranged in said second conductive type of trap; First conductive type of trap, part is between said second conductive type of trap and the said second conduction type doped layer, so that the said first conduction type source region is electrically connected with the said first conduction type drain region at least.
In one embodiment, part is overlapped at least outside said first conductive type of trap for said second conductive type of trap and the said second conduction type doped layer, so that said second conductive type of trap is electrically connected with the said second conduction type doped layer each other.
In one embodiment; At least the part source of a plurality of pixel cells is followed the transistorized first conduction type drain region and is positioned at least in part outside said second conductive type of trap, has equal current potential so that the transistorized first conduction type drain region is followed in said part at least source.This makes the ground connection of each pixel cell of imageing sensor directly to connect through first conductivity type substrate, under the situation that does not increase chip area, has improved the effect of ground connection, avoids different pixels unit earthing potential inconsistent.
In one embodiment, the drain electrode that the transistorized second conduction type doped layer is coupled to said transfering transistor is followed in said source, and the first conduction type drain region is coupled to reference potential line, and the said first conduction type source region is used to export said voltage signal.
In one embodiment, also comprise dielectric isolation region in said first conductivity type substrate, it is positioned at outside said second conductive type of trap, is used to isolate said second conductive type of trap and said photodiode.
According to the utility model on the other hand, a kind of source follower is provided also, has comprised that the source follows the transistor AND gate bias current sources, wherein, it is junction field effect transistor that transistor is followed in said source, and its grid is used for receiving inputted signal; Its drain region is coupled to reference potential line; Its source region is coupled to said bias current sources obtaining bias current, and is used for output voltage signal.
Source follower than prior art; Follow transistor owing to adopted junction field effect transistor to substitute surperficial channel MOS transistor as the source; This has been avoided the charge carrier in the conducting channel to be captured at random because of oxide layer-Semiconductor substrate interfacial state at the interface or discharge, thereby has effectively reduced the flicker noise in the voltage signal of output.
The above characteristic of the utility model and other characteristics are partly set forth embodiment hereinafter clearly.
Description of drawings
Through with reference to the detailed description of being done below the advantages, can more easily understand characteristic, purpose and the advantage of the utility model to non-limiting example.Wherein, same or analogous Reference numeral is represented same or analogous device.
Fig. 1 shows a kind of 4T dot structure of traditional cmos imageing sensor;
Fig. 2 a shows the imageing sensor 200 according to an embodiment of the utility model;
Fig. 2 b shows imageing sensor 200 and the signal processing circuit 210 thereof of Fig. 2 a;
Fig. 2 c shows the sequential chart of the control signal of the imageing sensor 200 that is used for Fig. 2 b and signal processing circuit 210 thereof;
Fig. 3 a shows the source of imageing sensor 200 among Fig. 2 a and follows a transistorized example 300;
Fig. 3 b shows the source of imageing sensor 200 among Fig. 2 a and follows transistorized another example;
Fig. 4 a shows the source of imageing sensor 200 among Fig. 2 a and follows transistorized another example 400;
Fig. 4 b shows the source of Fig. 4 a and follows the generalized section of transistor along AA ' direction;
Fig. 5 shows the source follower 500 according to an embodiment of the utility model;
Fig. 6 shows the source follower 600 according to an embodiment of the utility model.
Embodiment
Go through enforcement and the use of embodiment below.Yet, should be appreciated that the specific embodiment discussed only exemplarily explanation implement and use the ad hoc fashion of the utility model, and the scope of unrestricted the utility model.
With reference to figure 2a, show imageing sensor 200 according to an embodiment of the utility model, comprising:
Photodiode 201 is used to respond to light intensity and changes and generate corresponding image charge signal;
Transfering transistor 202 is used for transition diagram image charge signal;
In the present embodiment, to follow transistor 204 are p type field effect transistors in the source.It will be understood by those skilled in the art that in other embodiment, the source is followed transistor 204 and also can be n type field effect transistor.
Particularly, photodiode 201 is coupled to reference potential line VSS, for example or the negative supply current potential, and between the source electrode of transfering transistor 202, is used to respond to light intensity and changes and form corresponding image charge signal.The drain electrode of transfering transistor 202 links to each other with the grid that transistor 204 is followed in the source; The grid of this transfering transistor 202 is used for receiving transfer control signal TX; Under the control of shifting control signal TX; Transfering transistor 202 corresponding conducting or shutoffs, thus the image charge signal that makes photodiode 201 responded to is read into the floating diffusion region of the drain electrode that is coupled in this transfering transistor 202, and by this floating diffusion region memory image charge signal.
The source is followed transistor 204 and is coupled between reference potential line VSS and the bias current sources 205; Its drain electrode is coupled to reference potential line VSS; Its source electrode is coupled to this bias current sources 205 and is used for output voltage signal; Its grid is coupled to the drain electrode of transfering transistor 202, promptly is couple to floating diffusion region, to obtain the image charge signal that transfering transistor 202 is shifted.Under the biasing of bias current sources 205, the voltage follow that transistor 204 source electrodes are followed in the source the image charge signal that its grid obtains and is changed and change, and its voltage gain approaches 1.In one embodiment, the source electrode that transistor 204 is followed in the source further is couple to the bit line (not shown) through the row selecting transistor (not shown), and this voltage signal is offered the signal processing circuit of imageing sensor.
In one embodiment, this imageing sensor also comprises reset transistor 203, and the drain electrode of this reset transistor 203 is used to receive reset signal RSG, and its source electrode is couple to the drain electrode of transfering transistor 202 and the grid that transistor 204 is followed in the source.The grid of this reset transistor 203 is used to receive reseting controling signal RST, under the control of this reseting controling signal RST, and reset transistor 203 corresponding conducting or shutoffs, thus to the grid that transistor 204 is followed in the source reset signal is provided.In this embodiment; Transfering transistor 202 is nmos pass transistor with reset transistor 203, is appreciated that in other embodiment; Transfering transistor 202 and reset transistor 203 also can adopt the transistor of other types, for example PMOS transistor or technotron.
Follow transistor 204 owing to adopted junction field effect transistor to substitute surperficial channel MOS transistor as the source; This has been avoided the charge carrier in the conducting channel to be captured at random because of oxide layer-Semiconductor substrate interfacial state at the interface or discharge; Thereby effectively reduced the flicker noise in the voltage signal of exporting, and then improved the image quality of imageing sensor 200.
Fig. 2 b shows imageing sensor 200 and the signal processing circuit 210 thereof of Fig. 2 a.
Shown in Fig. 2 b, this imageing sensor 200 is couple to bit line BL through row selecting transistor 206, and wherein the grid of this row selecting transistor 206 is used to receive row selection signal RS.This signal processing circuit 210 comprises:
Image electric capacity 211, it is coupled to bit line BL, is configured under the control of first switch 212, obtain the picture signal that imageing sensor 200 provides, and is promptly followed the image voltage signal of transistor 204 outputs by the source; Wherein, the control end of this first switch 212 is used to receive the first control signal SHS;
Amplifying unit 215 is used for the poor of enlarged image signal and reset signal.The output voltage of amplifying unit 215 can be further through offering subsequent process circuit after the conversion of analog-to-digital conversion module (not shown).
Fig. 2 c shows the sequential chart of the control signal of the imageing sensor 200 that is used for Fig. 2 b and signal processing circuit 210 thereof.Next, in conjunction with Fig. 2 b and Fig. 2 c, the operation principle of this imageing sensor is described.
Shown in Fig. 2 c, between the T6, this pixel cell is selected at moment T1, and row selection signal RS is in high level, row selecting transistor 206 conductings.The source electrode that transistor 204 is followed in the source is couple to bit line BL.
Between moment T1 to T2; Reseting controling signal RST is in high level; And between moment T1 to T6; The reset signal that loads in the drain electrode of reset transistor 203 is in high level all the time, so reset transistor 203 conducting between moment T1 to T2, and the reset signal of high level is provided to the drain electrode that the source is followed the grid of transistor 204 and is temporarily stored in transfering transistor 202.Then, at moment T3, the second control signal SHR is a high level by low transition, and this makes second switch 214 conductings, and reset capacitance 213 is coupled to bit line BL.Because the source is followed transistor 204 source potential and is higher than grid potential; Transistor 204 conductings are followed in the source; This makes that reset signal is followed by the source, and transistor 204 offers reset capacitance 213 so that reset capacitance 213 is recharged; Thereby in reset capacitance 213, correspondingly store reset charge, wherein the charge value of this reset charge is corresponding to the magnitude of voltage of reset signal.Afterwards, the second control signal SHR replys low level, and reset capacitance 213 is broken off with bit line BL.
At moment T4, shifting control signal TX is high level by low transition, transfering transistor 202 conductings.Electric charge by photodiode 201 inductions is transferred transistor 202 transfers, and is stored in floating diffusion region.Then, at moment T5, the first control signal SHS is a high level by low transition, and this makes switch 212 conductings of winning, and image electric capacity 211 is coupled to bit line BL.Because the source is followed transistor 204 source potential and is higher than grid potential; This makes that the image charge signal is followed by the source, and transistor 204 offers image electric capacity 211 so that image electric capacity 211 is recharged; Thereby memory image electric charge correspondingly in image electric capacity 211, wherein the charge value of this reset charge is corresponding to image charge voltage of signals value.Afterwards, the first control signal SHS replys low level, and image electric capacity 211 breaks off with bit line BL.
After reset capacitance 213 and image electric capacity 211 were stored the electric charge corresponding to reset signal and image charge signal respectively, amplifying unit 215 amplified the voltage difference on these two electric capacity, and the output voltage that will pass through amplification offers follow-up treatment circuit.
Fig. 3 a shows the source of imageing sensor 200 among Fig. 2 a and follows a transistorized example 300, and wherein to follow transistor be p type field effect transistor in this source.It should be understood by one skilled in the art that its operation principle is equally applicable to the source and follows the situation that transistor is a n type field effect transistor.
Shown in Fig. 3 a, this source is followed transistor and is comprised:
N type doped layer 305, it at least partly is arranged in N type trap 303;
P type source region 307, it is arranged in N type trap 303;
P type drain region 309, it is arranged in P type substrate 301 and/or N type trap 303;
Particularly, P type substrate 301 can be the semiconductor wafer that the P type mixes, or the silicon-on-insulator (SOI) of P type doping, or the P type trap in the semiconductor wafer of N type doping, perhaps other similar substrate or well regions.
P type source region 307 all is arranged in N type trap 303.This N type trap 303 makes P type source region 307 and P type substrate 301 isolate each other.Because source region 307 is used for output voltage signal, it possibly have higher current potential, and P type substrate 301 is couple to reference potential line usually, for example.Therefore, the substrate break-through can be avoided with the 301 mutual isolation of P type substrate in source region 307, follows transistorized operate as normal to guarantee the source.
According to the difference of specific embodiment, this P type drain region 309 can all be arranged in the P type substrate 301 outside the N type trap 303; Perhaps all be arranged in N type trap 303; Perhaps a part is positioned at N type trap 303, and another part is arranged in the P type substrate 301 outside the N type trap 303.In the example shown in Fig. 3 a 300, P type drain region 309 all is arranged in N type trap 303, thereby it is electrically connected through the P type trap 311 in the N type trap 303 with P type source region 307 each other.In practical application, (overlap) overlapped to realize being electrically connected therebetween with P type trap 311 respectively each other in this P type source region 307 and P type drain region 309.Adapt with P type trap 311, N type doped layer 305 also can be positioned among the N type trap 303 whole or in part, and between source region 307 and drain region 309.In the example 300 of Fig. 3 a, this N type doped layer 305 all is positioned at N type trap 303.
Fig. 3 b shows the source of imageing sensor 200 among Fig. 2 a and follows transistorized another example.In Fig. 3 b, also show the photodiode of imageing sensor 200, it is by P type substrate 301 and be positioned at the outer N type doped regions 321 of N type trap 303 and constitute.
Shown in Fig. 3 b, also comprise dielectric isolation region 323 in the P type substrate 301, it is positioned at outside the N type trap 303, promptly between N type doped region 321 and N type trap 303.Dielectric isolation region 323 adopts insulating material, and for example silica, silicon nitride form, thereby have electric isolation effect preferably.Dielectric isolation region 323 in the P type substrate 301 makes N type doped region 321 and N type trap 303 isolate each other, and it can effectively be avoided negative pole and the source of photodiode to follow between the transistorized grid being short-circuited (being break-through) and influence the operation of imageing sensor.Dielectric isolation region 323 can adopt fleet plough groove isolation structure (Shallow Trench Isolation), and its chip area that takies is less relatively, thereby can effectively reduce the area of imageing sensor.
In a preferred embodiment, dielectric isolation region 323 can be adjacent with P type source region 307 and/or N type doped region 321, and this can further reduce the area of imageing sensor, thereby improve chip integration.Especially, in the example shown in Fig. 3 b, dielectric isolation region 323 is adjacent with N type trap 303 and P type source region 307, and this makes the N type trap 303 and the contact area of P type substrate 301 reduce, thereby has effectively reduced the parasitic capacitance between N type trap 303 and the P type substrate 301.In imageing sensor, N type trap 303 can be coupled to the floating diffusion region of imageing sensor.Be appreciated that the parasitic capacitance between N type trap 303 and the P type substrate 301 is more little, the sensitivity of imageing sensor is also high more.The sensitivity that therefore, can further improve imageing sensor with N type trap 303 and P type source region 307 adjacent dielectric isolation region 323.
Fig. 4 a and Fig. 4 b show the source of imageing sensor 200 among Fig. 2 a and follow transistorized another example 400.Wherein, Fig. 4 b is that the generalized section of transistor along AA ' direction followed in the source among Fig. 4 a.
Shown in Fig. 4 a and Fig. 4 b, this source follow transistor have with Fig. 3 a in the source follow structure like the transistor-like.But the P type substrate 401 outside the N type trap 403 that is arranged in transistorized drain region 409 is followed in this source, and this makes P type impure drain region 409 be electrically connected with P type substrate 401.In practical application, this drain region 409 all is coupled to reference potential line with P type substrate 401, for example, does not therefore have voltage difference therebetween, thereby can between drain region 409 and P type substrate 401, not form electric current.
Correspondingly, P type trap 411 is extended in the P type substrate 401 by N type trap 403 at least in part, so that this P type substrate 401 is electrically connected source region 407 and drain region 409 jointly with P type trap 411.Like this, when transistor turns was followed in this source, channel current can flow to source region 407 through these P type substrates 401 and P type trap 411 by drain region 409.
Especially, for imageing sensor 200, it has a plurality of pixel cells usually, follows transistor and each pixel cell all has the source.Follow transistorized drain region 409 for these sources, can have part or all of drain region 409 all to be arranged in the P type substrate 401 outside the N type trap 403 at least in part.Like this, these are positioned at N type trap 403 outer drain regions 409 can have the current potential that equates with P type substrate 401, thereby it has equal current potential each other.Thereby; This can be so that have improved the effect of ground connection under the situation that does not increase chip area; For example can share ground connection through P type substrate 401, this is just avoided different pixels unit earthing potential inconsistent, thereby has further improved the performance of imageing sensor 200.
With reference to figure 4a, part is overlapped at least outside P type trap 411 with N type doped layer 405 for N type trap 403, thereby makes N type trap 403 be electrically connected each other with N type doped layer 405.Just need in N type trap 403, not make extra electrode draws N type trap 403 for this, thereby has reduced cost of manufacture.
Fig. 5 shows the source follower 500 according to an embodiment of the utility model.
As shown in Figure 5, this source follower 500 comprises that the source follows transistor 501 and bias current sources 503, and wherein, it is P type junction field effect transistors that transistor 501 is followed in this source, and its grid 505 is used to receive input voltage signal V
InIts drain region 507 is coupled to reference potential line VSS, for example or the negative sense power supply potential; Its source region 509 is coupled to bias current sources 503 obtaining bias current, and is used for output voltage signal V
Out
In certain embodiments, transistor 501 is followed in this source can adopt the jfet structure shown in Fig. 3 a, Fig. 3 b or Fig. 4 b, repeats no more at this.In practical application, this source follower 500 can be used for imageing sensor or other need provide the circuit of voltage follow.
Fig. 6 shows the source follower 600 according to an embodiment of the utility model.
As shown in Figure 6, this source follower 600 comprises that the source follows transistor 601 and bias current sources 603, and wherein, it is N type junction field effect transistors that transistor 601 is followed in this source, and its grid 605 is used to receive input voltage signal V
InIts drain region 607 is coupled to reference potential line VDD, for example the forward power supply potential; Its source region 609 is coupled to bias current sources 603 obtaining bias current, and is used for output voltage signal V
Out
Source follower than prior art; Adopted junction field effect transistor to substitute surperficial channel MOS transistor and followed transistor as the source; This has been avoided the charge carrier in the conducting channel to be captured at random because of oxide layer-Semiconductor substrate interfacial state at the interface or discharge, thereby has effectively reduced the flicker noise in the voltage signal of output.
Although in accompanying drawing and aforesaid description sets forth in detail with the utility model has been described, should think that this is illustrated and describes is illustrative and exemplary, rather than restrictive; The utility model is not limited to above-mentioned execution mode.
Claims (11)
1. an imageing sensor is characterized in that, comprises one or more pixel cells, and wherein each pixel cell comprises:
Photodiode is used to respond to light intensity and changes and generate corresponding image charge signal;
Transfering transistor is used to shift said image charge signal;
Transistor is followed in the source, is used for based on the image charge signal formation voltage signal that is shifted, and wherein, it is junction field effect transistor that transistor is followed in said source.
2. imageing sensor according to claim 1 is characterized in that, said source is followed transistor and comprised:
First conductivity type substrate;
Second conductive type of trap is arranged in said first conductivity type substrate;
The second conduction type doped layer, part is arranged in said second conductive type of trap at least;
The first conduction type source region is arranged in said second conductive type of trap;
The first conduction type drain region is arranged in said first conductivity type substrate and/or is arranged in said second conductive type of trap;
First conductive type of trap, part is between said second conductive type of trap and the said second conduction type doped layer, so that the said first conduction type source region is electrically connected with the said first conduction type drain region at least.
3. imageing sensor according to claim 2; It is characterized in that; Part is overlapped at least outside said first conductive type of trap for said second conductive type of trap and the said second conduction type doped layer, so that said second conductive type of trap is electrically connected with the said second conduction type doped layer each other.
4. imageing sensor according to claim 2 is characterized in that, said first conduction type drain region part at least is positioned at outside said second conductive type of trap.
5. imageing sensor according to claim 4; It is characterized in that; At least the part source of a plurality of pixel cells is followed the transistorized first conduction type drain region and is positioned at least in part outside said second conductive type of trap, has equal current potential so that the transistorized first conduction type drain region is followed in said part at least source.
6. imageing sensor according to claim 2; It is characterized in that; The said second conduction type doped layer is coupled to the drain electrode of said transfering transistor, and the said first conduction type drain region is coupled to reference potential line, and the said first conduction type source region is used to export said voltage signal.
7. imageing sensor according to claim 2 is characterized in that, also comprises dielectric isolation region in said first conductivity type substrate, and it is positioned at outside said second conductive type of trap, is used to isolate said second conductive type of trap and said photodiode.
8. a source follower is characterized in that, comprises that the source follows the transistor AND gate bias current sources, and wherein, it is junction field effect transistor that transistor is followed in said source, and its grid is used for receiving inputted signal; Its drain region is coupled to reference potential line; Its source region is coupled to said bias current sources obtaining bias current, and is used for output voltage signal.
9. source follower according to claim 8 is characterized in that, said source is followed transistor and comprised:
First conductivity type substrate;
Second conductive type of trap is arranged in said first conductivity type substrate;
The second conduction type doped layer, part is arranged in said second conductive type of trap at least;
The first conduction type source region is arranged in said second conductive type of trap;
The first conduction type drain region is arranged in said first conductivity type substrate and/or is arranged in said second conductive type of trap;
First conductive type of trap, part is between said second conductive type of trap and the said second conduction type doped layer, so that the said first conduction type source region is electrically connected with the said first conduction type drain region at least.
10. source follower according to claim 9; It is characterized in that; Part is overlapped at least outside said first conductive type of trap for said second conductive type of trap and the said second conduction type doped layer, so that said second conductive type of trap is electrically connected with the said second conduction type doped layer each other.
11. source follower according to claim 9 is characterized in that, said first conduction type drain region part at least is positioned at outside said second conductive type of trap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220044374 CN202633312U (en) | 2012-01-11 | 2012-02-10 | Image sensor and source follower |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210008006.4 | 2012-01-11 | ||
| CN201210008006 | 2012-01-11 | ||
| CN 201220044374 CN202633312U (en) | 2012-01-11 | 2012-02-10 | Image sensor and source follower |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202633312U true CN202633312U (en) | 2012-12-26 |
Family
ID=46527890
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210030647XA Pending CN102610623A (en) | 2012-01-11 | 2012-02-10 | Image sensor and source follower |
| CN 201220044374 Expired - Lifetime CN202633312U (en) | 2012-01-11 | 2012-02-10 | Image sensor and source follower |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210030647XA Pending CN102610623A (en) | 2012-01-11 | 2012-02-10 | Image sensor and source follower |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN102610623A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610623A (en) * | 2012-01-11 | 2012-07-25 | 格科微电子（上海）有限公司 | Image sensor and source follower |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9319613B2 (en) * | 2013-12-05 | 2016-04-19 | Omnivision Technologies, Inc. | Image sensor having NMOS source follower with P-type doping in polysilicon gate |
| CN105830219B (en) * | 2013-12-25 | 2019-01-01 | 佳能株式会社 | Imaging device, imaging system and the method for manufacturing imaging device |
| CN107301393B (en) * | 2017-06-20 | 2018-03-23 | 安徽泓森物联网有限公司 | Self-adaptive switch big data management platform |
| IT201800010671A1 (en) * | 2018-11-29 | 2020-05-29 | Milano Politecnico | CHARGING PRE-AMPLIFIER DEVICE AND RADIATION DETECTION DEVICE INCLUDING THE DEVICE |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2666928B2 (en) * | 1987-07-13 | 1997-10-22 | 株式会社東芝 | Output detector for charge transfer device |
| EP0981166A3 (en) * | 1998-08-17 | 2000-04-19 | ELMOS Semiconductor AG | JFET transistor |
| US6245607B1 (en) * | 1998-12-28 | 2001-06-12 | Industrial Technology Research Institute | Buried channel quasi-unipolar transistor |
| JP4513497B2 (en) * | 2004-10-19 | 2010-07-28 | ソニー株式会社 | Solid-state imaging device |
| JP5709404B2 (en) * | 2010-05-10 | 2015-04-30 | キヤノン株式会社 | Solid-state imaging device and driving method thereof |
| CN102610623A (en) * | 2012-01-11 | 2012-07-25 | 格科微电子（上海）有限公司 | Image sensor and source follower |
-
2012
- 2012-02-10 CN CN201210030647XA patent/CN102610623A/en active Pending
- 2012-02-10 CN CN 201220044374 patent/CN202633312U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610623A (en) * | 2012-01-11 | 2012-07-25 | 格科微电子（上海）有限公司 | Image sensor and source follower |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102610623A (en) | 2012-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100851495B1 (en) | Small pixel for image sensors with jfet and vertically integrated reset diodes | |
| US9673258B2 (en) | Organic pixels including organic photodiode, manufacturing methods thereof, and apparatuses including the same | |
| KR100922931B1 (en) | CMOS image sensor and method for fabricating the same | |
| KR100851494B1 (en) | Small pixel for cmos image sensors with vertically integrated set and reset diodes | |
| KR20100064699A (en) | Back-side illuminated image sensor | |
| CN202633312U (en) | Image sensor and source follower | |
| US20040206991A1 (en) | Solid-state imaging device | |
| CN105304660A (en) | Imaging device and method for driving the same | |
| TWI470777B (en) | Image sensor including a pixel cell having an epitaxial layer, system having the same, and method of forming a pixel cell | |
| KR20030008481A (en) | Cmos image sensor | |
| KR100462164B1 (en) | Cmos image sensor with enhanced fill factor | |
| JP2004253670A (en) | Solid state imaging device | |
| CN102709302B (en) | Image sensor and manufacturing method of transistor | |
| KR100298199B1 (en) | A unit pixel of a CMOS image sensor having a PIN diode | |
| CN102522417B (en) | Image sensor and source follower | |
| CN202549844U (en) | Image sensor and source follower | |
| US9602746B2 (en) | Image pickup device and electronic apparatus | |
| KR100303773B1 (en) | A unit pixel of a CMOS image sensor having a p < th > | |
| CN202678315U (en) | Image sensor | |
| KR100298198B1 (en) | A unit pixel of a CMOS image sensor having a Schottky diode | |
| KR100460760B1 (en) | Unit Pixel with improved fill factor and dark signal property in cmos image sensor | |
| KR20040093295A (en) | Fabricating method for photo diode in cmos image sensor | |
| KR20040092737A (en) | Cmos image sensor with improved dead zone characteristics and dark current characteristics and the method for fabricating thereof | |
| KR20040058756A (en) | Unit Pixel in CMOS image sensor and method for fabricating thereof | |
| KR20030052634A (en) | CMOS Image sensor and method for fabricaing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20121226 |