CN102522417B - Image sensor and source follower - Google Patents
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Abstract
The invention discloses an image sensor and a source follower. The image sensor comprises a photoelectric diode for sensing a change of light intensity to generate a corresponding image charge signal, a transfer transistor for transferring the image charge signal, and a source follower transistor for generating a voltage signal based on the transferred image charge signal, wherein the source follower transistor is a buried channel PMOS (P-channel Metal Oxide Semiconductor) transistor. Compared with the image sensor in the prior art, as the buried channel PMOS transistor is adopted as the source follower transistor, a conducting channel of the source follower transistor can be far away from an interface between a gate oxidation layer and a substrate, and the probability of randomly capturing or releasing carriers by an interface state at the interface position is greatly reduced, so that the flicker noise in the output voltage signal is effectively reduced, and therefore the imaging quality of the image sensor is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to a kind of imageing sensor and source follower.
Background technology
Traditional imageing sensor can be divided into two classes conventionally: charge coupled device (Charge Coupled Device, CCD) imageing sensor and complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor.Wherein, cmos image sensor has the advantages such as volume is little, low in energy consumption, production cost is low, therefore, cmos image sensor is easy to be integrated in mancarried electronic aids such as mobile phone, notebook computer, panel computer, as providing the camera module of digital imagery function to use.
Cmos image sensor adopts the dot structure of 3T or 4T conventionally.Fig. 1 shows a kind of 4T dot structure of traditional cmos imageing sensor, comprises that photodiode 11, transfering transistor 12, reset transistor 13, source follow transistor 14 and row selecting transistor 15.Wherein, photodiode 11 forms corresponding image charge signal for responding to light intensity variation.Transfering transistor 12 shifts control signal TX for receiving, shifting under the control of control signal TX, the corresponding conducting of transfering transistor 12 or shutoff, thereby make image charge signal that photodiode 11 is responded to be read out to the floating diffusion region (floating diffusion) that the drain electrode with this transfering transistor 12 couples, and then by this floating diffusion region memory image charge signal.Reset transistor 13 is for receiving reseting controling signal RST, under the control of this reseting controling signal RST, and the corresponding conducting of reset transistor 13 or shutoff, thus the grid of following transistor 14 to source provides reset signal.Source is followed transistor 14 and is converted to voltage signal for the image charge signal that transfering transistor 12 is obtained, and this voltage signal can output on bit line BL by row selecting transistor 15.
Yet, in the voltage signal of traditional cmos imageing sensor output, often there is larger flicker noise, when light is weak, this flicker noise is more obvious especially.Flicker noise in voltage signal can reduce picture quality significantly.
Summary of the invention
Therefore, need to provide a kind of imageing sensor having compared with low flash noise.
Inventor is through research discovery, and traditional cmos image sensor often adopts the surface channel transistor source of being used as to follow transistor.In this provenance, follow in transistor, conducting channel is positioned at substrate surface, and near the gate oxide on substrate.Yet substrate easily forms interfacial state near the region of gate oxide, this interfacial state can be captured randomly or be discharged charge carrier, thereby causes the variation of channel current, and then introduces flicker noise in the voltage signal of transistor output is followed in source.
In order to address the above problem, according to an aspect of the present invention, provide a kind of imageing sensor, comprising: photodiode, generates corresponding image charge signal for responding to light intensity variation; Transfering transistor, for transition diagram as charge signal; Transistor is followed in source, and for the image charge signal formation voltage signal based on shifted, wherein, it is buried channel (Buried Channel) PMOS transistor that transistor is followed in this source.
Imageing sensor than prior art, owing to having adopted PMOS with buried channel transistor, as source, follow transistor, this makes source follow transistorized conducting channel can be away from the interface of gate oxide-substrate, the interfacial state of this interface location is captured at random or the probability that discharges charge carrier reduces greatly, thereby effectively reduced the flicker noise in the voltage signal of exporting, and then improved the image quality of imageing sensor.
In one embodiment, this source is followed transistor and is comprised: P type substrate; N-type trap, it is arranged in P type substrate; Grid, it is positioned on N-type trap; Source region and drain region, it lays respectively at grid both sides, and wherein source region is arranged in N-type trap, and drain region is arranged in N-type trap at least in part; P type doped layer and N-type doped layer, it is from top to bottom successively in the N-type trap below the grid between source region and drain region.
In one embodiment, this source is followed transistorized drain region and is positioned at least in part outside N-type trap.This can directly connect by P type substrate the ground connection of each pixel cell of imageing sensor, has improved the effect of ground connection in the situation that not increasing chip area, avoids different pixels unit earthing potential inconsistent.
In one embodiment, source is followed transistor and is also comprised N-type heavily doped region, and it is arranged in N-type trap so that N-type trap is drawn from P type substrate electricity.Preferably, N-type heavily doped region is electrically connected to source region.The source being mutually electrically connected to is followed transistorized source region and is had with tagma the current potential equating, this can be avoided serving as a contrast inclined to one side mudulation effect, makes source follow transistor and has higher input and output gain, and voltage follow characteristic is also better.
In one embodiment, N-type heavily doped region and source region are adjacent.Preferably, source is followed transistor and is also comprised metal silicide layer, its be positioned at N-type heavily doped region with on source region to be electrically connected to N-type heavily doped region and source region.This metal silicide layer is suitable for being electrically connected to adjacent source region and tagma, and does not need to connect by metal interconnect structure, thereby has simplified the structure of imageing sensor, has reduced cost of manufacture.
In one embodiment, the drain electrode that transistorized grid is coupled to transfering transistor is followed in source, i.e. floating diffusion region, and source is followed transistorized drain region and is coupled to reference potential line, and transistorized source region is followed for output voltage signal in source.
According to a further aspect in the invention, also provide a kind of source follower, having comprised: transistor and bias current sources are followed in source, wherein, it is PMOS with buried channel transistor that transistor is followed in this source, and its grid is used for receiving input signal; Its drain region is coupled to reference potential line; Its source region is coupled to bias current sources to obtain bias current, and for output voltage signal.
Source follower than prior art, owing to having adopted PMOS with buried channel transistor, as source, follow transistor, this makes source follow transistorized conducting channel can be away from the interface of gate oxide-substrate, the interfacial state of this interface location is captured at random or the probability that discharges charge carrier reduces greatly, thereby has effectively reduced the flicker noise in the voltage signal of output.
Above characteristic of the present invention and other characteristics are partly set forth embodiment hereinafter clearly.
Accompanying drawing explanation
By reading the following detailed description to non-limiting example with reference to accompanying drawing, can more easily understand features, objects and advantages of the invention.Wherein, same or analogous Reference numeral represents same or analogous device.
Fig. 1 shows a kind of 4T dot structure of traditional cmos imageing sensor;
Fig. 2 a shows imageing sensor 200 according to an embodiment of the invention;
Fig. 2 b shows imageing sensor 200 and the signal processing circuit 210 thereof of Fig. 2 a;
Fig. 2 c shows the sequential chart for the imageing sensor 200 of Fig. 2 b and the control signal of signal processing circuit 210 thereof;
Fig. 3 shows the source of imageing sensor 200 in Fig. 2 a and follows a transistorized example;
Fig. 4 shows the source of imageing sensor 200 in Fig. 2 a and follows transistorized another example;
Fig. 5 shows source follower 500 according to an embodiment of the invention.
Embodiment
Discuss enforcement and the use of embodiment below in detail.Yet, should be appreciated that discussed specific embodiment only exemplarily illustrates and implements and use ad hoc fashion of the present invention, but not limit the scope of the invention.
With reference to figure 2a, show imageing sensor 200 according to an embodiment of the invention, comprising:
Photodiode 201, generates corresponding image charge signal for responding to light intensity variation;
Transfering transistor 202, for transition diagram as charge signal;
Transistor 204 is followed in source, and for the image charge signal formation voltage signal based on shifted, wherein, it is PMOS with buried channel transistors that transistor 204 is followed in this source.
Particularly, photodiode 201 is coupled to reference potential line VSS, for example or negative supply current potential, and between the source electrode of transfering transistor 202, for responding to light intensity, changes and forms corresponding image charge signal.The drain electrode of transfering transistor 202 is connected with the grid that transistor 204 is followed in source, the grid of this transfering transistor 202 is used for receiving transfer control signal TX, shifting under the control of control signal TX, the corresponding conducting of transfering transistor 202 or shutoff, thereby make image charge signal that photodiode 201 is responded to be read out to the floating diffusion region of the drain electrode that is coupled in this transfering transistor 202, and by this floating diffusion region memory image charge signal.
Source is followed transistor 204 and is coupled between reference potential line VSS and bias current sources 205, its drain electrode is coupled to reference potential line VSS, its source electrode is coupled to this bias current sources 205 and for output voltage signal, its grid is coupled to the drain electrode of transfering transistor 202, be couple to floating diffusion region, the image charge signal being shifted to obtain transfering transistor 202.Under the biasing of bias current sources 205, the voltage follow that transistor 204 source electrodes are followed in source the image charge signal intensity that its grid obtains and is changed, and its voltage gain is close to 1.In one embodiment, the source electrode that transistor 204 is followed in source is further couple to bit line (not shown) by row selecting transistor (not shown), and this voltage signal is offered to the signal processing circuit of imageing sensor.
In one embodiment, this imageing sensor also comprises reset transistor 203, and the drain electrode of this reset transistor 203 is used for receiving reset signal RSG, and its source electrode is couple to the drain electrode of transfering transistor 202 and the grid that transistor 204 is followed in source.The grid of this reset transistor 203 is used for receiving reseting controling signal RST, under the control of this reseting controling signal RST, and the corresponding conducting of reset transistor 203 or shutoff, thus the grid of following transistor 204 to source provides reset signal.In this embodiment, transfering transistor 202 is nmos pass transistor with reset transistor 203, is appreciated that in other embodiment, transfering transistor 202 also can adopt the transistor of other types with reset transistor 203, for example PMOS transistor or technotron.
Owing to having adopted PMOS with buried channel transistor, as source, follow transistor 204, this makes source follow the conducting channel of transistor 204 can be away from the interface of its gate oxide-substrate, should thus this source follow that interfacial state in transistor 204 is captured at random or the probability that discharges charge carrier reduces greatly, thereby effectively reduced the flicker noise in the voltage signal of exporting, and then improved the image quality of imageing sensor 200.
Fig. 2 b shows imageing sensor 200 and the signal processing circuit 210 thereof of Fig. 2 a.
As shown in Figure 2 b, this imageing sensor 200 is couple to bit line BL by row selecting transistor 206, and wherein the grid of this row selecting transistor 206 is used for receiving row selection signal RS.This signal processing circuit 210 comprises:
Image electric capacity 211, it is coupled to bit line BL, is configured to obtain under the control of the first switch 212 picture signal that imageing sensor 200 provides, and by source, is followed the image voltage signal of transistor 204 outputs; Wherein, the control end of this first switch 212 is used for receiving the first control signal SHS;
Reset capacitance 213, it is coupled to bit line BL, is configured to obtain under the control of second switch 214 reset signal that imageing sensor 200 provides, and this reset signal is also followed transistor 204 outputs by source; Wherein, the control end of this second switch 214 is used for receiving the second control signal SHR; And
Amplifying unit 215, poor for enlarged image signal and reset signal.The output voltage of amplifying unit 215 can be further by offering subsequent process circuit after the conversion of analog-to-digital conversion module (not shown).
Fig. 2 c shows the sequential chart for the imageing sensor 200 of Fig. 2 b and the control signal of signal processing circuit 210 thereof.Next, in conjunction with Fig. 2 b and Fig. 2 c, the operation principle of this imageing sensor is described.
As shown in Figure 2 c, at moment T1, between T6, this pixel cell is selected, and row selection signal RS is in high level, row selecting transistor 206 conductings.The source electrode that transistor 204 is followed in source is couple to bit line BL.
Between moment T1 to T2, reseting controling signal RST is in high level, and between moment T1 to T6, the reset signal loading in the drain electrode of reset transistor 203 is all the time in high level, therefore reset transistor 203 conducting between moment T1 to T2, the reset signal of high level is provided to the drain electrode that source is followed the grid of transistor 204 and is temporarily stored in transfering transistor 202.Then, at moment T3, the second control signal SHR is high level by low transition, and this makes second switch 214 conductings, and reset capacitance 213 is coupled to bit line BL.Because transistor 204 source potential are followed higher than grid potential in source, transistor 204 conductings are followed in source, this makes reset signal by source, be followed that transistor 204 offers reset capacitance 213 so that reset capacitance 213 is recharged, thereby in reset capacitance 213, correspondingly store reset charge, wherein the charge value of this reset charge is corresponding to the magnitude of voltage of reset signal.Afterwards, the second control signal SHR replys low level, and reset capacitance 213 disconnects with bit line BL.
At moment T4, shifting control signal TX is high level by low transition, transfering transistor 202 conductings.The electric charge of being responded to by photodiode 201 is transferred transistor 202 and shifts, and is stored in unsteady active area.Then, at moment T5, the first control signal SHS is high level by low transition, and this makes the first switch 212 conductings, and image electric capacity 211 is coupled to bit line BL.Because transistor 204 source potential are followed higher than grid potential in source, this makes image charge signal by source, be followed that transistor 204 offers image electric capacity 211 so that image electric capacity 211 is recharged, thereby memory image electric charge correspondingly in image electric capacity 211, wherein the charge value of this reset charge is corresponding to the magnitude of voltage of image charge signal.Afterwards, the first control signal SHS replys low level, and image electric capacity 211 disconnects with bit line BL.
After reset capacitance 213 and image electric capacity 211 are stored respectively the electric charge corresponding to reset signal and image charge signal, amplifying unit 215 amplifies the voltage difference on these two electric capacity, and the output voltage through amplifying is offered to follow-up treatment circuit.
Fig. 3 shows the source of imageing sensor 200 in Fig. 2 a and follows a transistorized example.As shown in Figure 3, it is PMOS with buried channel transistor that transistor is followed in this source, and it comprises:
P type substrate 301;
N-type trap 303, it is arranged in P type substrate 301;
Grid 305, it is positioned on N-type trap 303;
311Yu drain region, source region 309, it lays respectively at grid 305 both sides, and wherein source region 311 is arranged in N-type trap 303, and drain region 309 is arranged in N-type trap 303 at least in part;
P type doped layer 315 and N-type doped layer 313, it is from top to bottom successively in the N-type trap 303 below the grid 305 between 311Yu drain region, source region 309.
Particularly, P type substrate 301 can be the semiconductor wafer of P type doping, or the silicon-on-insulator (SOI) of P type doping, or the P type trap in the semiconductor wafer of N-type doping, or other similar substrates or well region.
The source region 311 of P type doping is fully arranged in N-type trap 303, and this N-type trap 303 makes this source region 311 mutually isolate with P type substrate 301.Because source region 311 is for output voltage signal, it may have higher current potential, and P type substrate 301 is couple to reference potential line conventionally, for example.Therefore, substrate break-through can be avoided with the mutual isolation of P type substrate 301 in source region 311.
According to the difference of specific embodiment, P type impure drain region 309 can fully be arranged in N-type trap 303, or its part is arranged in N-type trap 303 and another part is arranged in P type substrate 301.In the example described in Fig. 3, this drain region 309 is arranged in N-type trap 303 completely, and this makes this drain region 309 mutually isolate with P type substrate 301.
P type doped layer 315 is positioned at the surface of N-type trap 303, and it contacts with the gate oxide 317 under grid 305.P type doped layer 315 is by gate oxide 317 and 313 isolation of N-type doped layer.When transistor turns is followed in this source, conducting channel is formed in N-type doped layer 313, thereby away from gate oxide 317.This makes this conducting channel away from the interfacial state between P type doped layer 315 and gate oxide 317, thereby greatly reduces the probability that charge carrier was captured or discharged to interfacial state randomly, and then has effectively reduced source and followed the flicker noise in transistor output voltage signal.
In one embodiment, source is followed transistor and is also comprised N-type heavily doped region 319, and it is arranged in N-type trap 303 so that N-type trap 303 is drawn from described P type substrate 301 electricity.Because N-type trap 303 is that transistorized tagma is followed in source, this N-type heavily doped region 319 is convenient to this tagma and is drawn.Preferably, this N-type heavily doped region 319 can be electrically connected to source region 311 by the metal interconnect structure on P type substrate 301, or other applicable conduction connecting structures are electrically connected to source region 311.The source being mutually electrically connected to is followed transistorized source region and is had with tagma the current potential equating, this can be avoided serving as a contrast inclined to one side mudulation effect, makes source follow transistor and has higher input and output gain, and voltage follow characteristic is also better.
Fig. 4 shows the source of imageing sensor 200 in Fig. 2 a and follows transistorized another example.
As shown in Figure 4, this source follow transistor have with Fig. 3 in source follow structure like transistor-like, be also PMOS with buried channel transistor.But this source is followed the part in transistorized drain region 409 and is positioned at outside N-type trap 403, and another part is arranged in P type substrate 401, and this makes P type impure drain region 409 be electrically connected to P type substrate 401.In actual applications, this drain region 409 is all coupled to reference potential line with P type substrate 401, for example, does not therefore have voltage difference therebetween, thereby can between drain region 409 and P type substrate 401, not form electric current.
Especially, for imageing sensor 200, it has a plurality of pixel cells conventionally, and each pixel cell all has source, follows transistor.Because the ground connection of each pixel cell can directly connect by P type substrate 401, in the situation that not increasing chip area, improved the effect of ground connection, avoid different pixels unit earthing potential inconsistent, thereby further improved the performance of imageing sensor 200.
In addition, it is adjacent that 411YuNXing heavily doped region 419, transistorized source region is followed in this source, and this 419Yu source region, N-type heavily doped region 411 is arranged in the P type substrate 401 of grid 405 the same sides.On this P type substrate 401, be also formed with metal silicide layer 421, it is positioned on 419Yu source region, N-type heavily doped region 411 at least in part, to be electrically connected to 419Yu source region, N-type heavily doped region 411.Meanwhile, this metal silicide layer 421 can also form Metal Contact on P type substrate 401 surfaces, thereby reduces the contact resistance in source region 411.Because N-type trap 403 electricity are drawn in N-type heavily doped region 419, therefore this source is followed transistorized tagma (being N-type trap 403) and is electrically connected to source region 411, the source being mutually electrically connected to is followed transistorized source region and is had with tagma the current potential equating, this can be avoided serving as a contrast inclined to one side mudulation effect, make source follow transistor and have higher input and output gain, voltage follow characteristic is also better.And owing to not needing the metal interconnect structure by extra to connect, thereby simplified the structure of imageing sensor, reduced cost of manufacture.
Fig. 5 shows source follower 500 according to an embodiment of the invention.
As shown in Figure 5, this source follower 500 comprises that source follows transistor 501 and bias current sources 503, and wherein, it is PMOS with buried channel transistors that transistor 501 is followed in this source, and its grid 505 is for receiving input voltage signal V
in; Its drain region 507 is coupled to reference potential line VSS, for example; Its source region 509 is coupled to bias current sources 503 to obtain bias current, and for output voltage signal V
out.
In actual applications, transistor 501 is followed in this source can adopt the PMOS with buried channel transistor arrangement shown in Fig. 3 or Fig. 4, does not repeat them here.
Source follower than prior art, owing to having adopted PMOS with buried channel transistor, as source, follow transistor, this makes source follow transistorized conducting channel can be away from the interface of gate oxide-substrate, the interfacial state of this interface location is captured at random or the probability that discharges charge carrier reduces greatly, thereby has effectively reduced the flicker noise in the voltage signal of output.
Although illustrate in detail and described the present invention in accompanying drawing and aforesaid description, should think that this is illustrated and describes is illustrative and exemplary, rather than restrictive; The invention is not restricted to above-mentioned execution mode.
The those skilled in the art of those the art can, by research specification, disclosed content and accompanying drawing and appending claims, understand and implement other changes of the execution mode to disclosing.In the claims, word " comprises " element and the step of not getting rid of other, and wording " one " is not got rid of plural number.In the practical application of invention, a part may execute claims the function of middle quoted a plurality of technical characterictics.Any Reference numeral in claim should not be construed as the restriction to scope.
Claims (11)
1. an imageing sensor, comprising:
Photodiode, generates corresponding image charge signal for responding to light intensity variation;
Transfering transistor, for shifting described image charge signal;
Transistor is followed in source, and for the image charge signal formation voltage signal based on shifted, wherein, it is PMOS with buried channel transistor that transistor is followed in described source; And described source is followed transistor and is comprised
P type substrate;
N-type trap, it is arranged in described P type substrate;
Grid, it is positioned on described N-type trap;
Source region and drain region, it lays respectively at described grid both sides; And
The N-type heavily doped region being electrically connected to described source region, is arranged in described N-type trap so that described N-type trap is drawn from described P type substrate electricity.
2. imageing sensor according to claim 1, is characterized in that, described source region is arranged in described N-type trap, and described drain region is arranged in described N-type trap at least in part;
P type doped layer and N-type doped layer, it is from top to bottom successively in the described N-type trap below the described grid between described source region and described drain region.
3. imageing sensor according to claim 2, is characterized in that, described source is followed transistorized described drain region and is positioned at least in part outside described N-type trap.
4. imageing sensor according to claim 2, is characterized in that, described N-type heavily doped region is adjacent with described source region.
5. imageing sensor according to claim 4, is characterized in that, described source is followed transistor and also comprised metal silicide layer, its be positioned at described N-type heavily doped region with on described source region to be electrically connected to described N-type heavily doped region and described source region.
6. imageing sensor according to claim 2, it is characterized in that, the drain electrode that transistorized grid is coupled to described transfering transistor is followed in described source, and described source is followed transistorized drain region and is coupled to reference potential line, and transistorized source region is followed for exporting described voltage signal in described source.
7. a source follower, is characterized in that, comprises that source follows transistor AND gate bias current sources, wherein: it is PMOS with buried channel transistor that transistor is followed in described source, and its grid is used for receiving input signal; Its drain region is coupled to reference potential line; Its source region is coupled to bias current sources to obtain bias current, and for output voltage signal;
Wherein said source is followed transistor and is comprised:
P type substrate;
N-type trap, it is arranged in described P type substrate;
Grid, it is positioned on described N-type trap;
Source region and drain region, it lays respectively at described grid both sides;
The N-type heavily doped region being electrically connected to described source region, is arranged in described N-type trap so that described N-type trap is drawn from described P type substrate electricity.
8. source follower according to claim 7, is characterized in that, described source region is arranged in described N-type trap, and described drain region is arranged in described N-type trap at least in part;
P type doped layer and N-type doped layer, it is from top to bottom successively in the described N-type trap below the described grid between described source region and described drain region.
9. source follower according to claim 8, is characterized in that, described source is followed transistorized described drain region and is positioned at least in part outside described N-type trap.
10. source follower according to claim 8, is characterized in that, described N-type heavily doped region is adjacent with described source region.
11. source followers according to claim 10, is characterized in that, described source is followed transistor and also comprised metal silicide layer, its be positioned at described N-type heavily doped region with on described source region to be electrically connected to described N-type heavily doped region and described source region.
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| US9319613B2 (en) * | 2013-12-05 | 2016-04-19 | Omnivision Technologies, Inc. | Image sensor having NMOS source follower with P-type doping in polysilicon gate |
| CN105100651B (en) * | 2015-06-03 | 2019-04-23 | 格科微电子（上海）有限公司 | Imaging sensor and the method for reducing image sensor noise |
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