CN102709166A - 降低n型掺杂和非掺杂多晶硅栅极刻蚀后形貌差异的方法 - Google Patents
降低n型掺杂和非掺杂多晶硅栅极刻蚀后形貌差异的方法 Download PDFInfo
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Abstract
本发明提供降低N型掺杂和非掺杂多晶硅栅极刻蚀后形貌差异的方法,包括以下顺序步骤:在具有N型掺杂多晶硅和非掺杂多晶硅的衬底板上沉积一层硬掩膜层,分别形成N型掺杂多晶硅硬掩膜层和非掺杂多晶硅硬掩膜层,对非掺杂多晶硅硬掩膜层进行刻蚀使得其厚度小于N型掺杂多晶硅硬掩膜层。在不同厚度的N型掺杂多晶硅硬掩膜层和非掺杂多晶硅硬掩膜层上沉积一防反射层,对整个器件进行预设定图案进行刻蚀,刻蚀至露出N型掺杂多晶硅为止。去除刻蚀过程留下在器件表面的残留物,后对器件进行刻蚀分别形成N型掺杂多晶硅栅极和非掺杂多晶硅栅极。
Description
技术领域
本发明涉及微电子技术领域,尤其涉及一种改进N型掺杂与非掺杂多晶硅栅极刻蚀后形貌差异的方法。
背景技术
在65nm及以下的工艺技术中,一般要求器件中多晶硅栅极由N型掺杂和非掺杂两种多晶硅组成。由于受N型离子掺杂的影响,N型掺杂多晶硅的刻蚀速率大于非掺杂的多晶硅刻蚀速率。
自动终点检测系统确认多晶硅栅极刻蚀结束的依据是N型掺杂与非掺杂多晶硅栅极全部刻蚀的完成,当N型掺杂多晶硅由于较快的刻蚀速率提前完成刻蚀时,为进行非掺杂多晶硅的刻蚀,等离子体并未停止轰击,会造成N型掺杂多晶硅栅极底部的损伤,形成缺陷(under-cut)。在这样的工艺条件下,就会造成N型半导体与P型半导体器件之间的差异,影响产品的整体性能。
65nm和55nm级多晶硅栅极普遍的刻蚀过程包括:步骤一:多晶硅栅极生长之后,硅片表面再生长一层用作刻蚀阻挡层的硬掩膜层。步骤二:经过光刻,涂上运用于多晶硅栅极刻蚀的光刻胶。步骤三:开始进入刻蚀步骤,首先是刻蚀防反射层。步骤四:刻蚀硬掩模层。步骤五:在刻蚀机台中,去光刻胶。步骤六:刻蚀多晶硅形成多晶硅栅极。在形成多晶硅栅极的刻蚀过程中,由于N型掺杂的多晶硅刻蚀速率大于非掺杂的多晶硅刻蚀,在刻蚀的过程中,两者的刻蚀形貌会形成差异。
发明内容
本发明提供一种改进N型掺杂与非掺杂多晶硅栅极刻蚀后形貌差异的方法,利用形成N型掺杂多晶硅栅极上较厚的硬掩膜层,来弥补由于N型掺杂多晶硅刻蚀速率大于非掺杂多晶硅刻蚀速率而造成N型与非掺杂多晶硅栅极刻蚀后形貌差异的方法。
为了实现上述目的,本发明提供降低N型掺杂和非掺杂多晶硅栅极刻蚀后形貌差异的方法,其特征在于,包括以下顺序步骤:
步骤1:在具有N型掺杂多晶硅和非掺杂多晶硅的衬底板上沉积一层硬掩膜层,分别形成N型掺杂多晶硅硬掩膜层和非掺杂多晶硅硬掩膜层,对非掺杂多晶硅硬掩膜层进行刻蚀使得其厚度小于N型掺杂多晶硅硬掩膜层。
步骤2:在不同厚度的N型掺杂多晶硅硬掩膜层和非掺杂多晶硅硬掩膜层上沉积一防反射层,对整个器件进行预设定图案进行刻蚀,刻蚀至露出N型掺杂多晶硅为止。
步骤3:去除刻蚀过程留下在器件表面的残留物,后对器件进行刻蚀分别形成N型掺杂多晶硅栅极和非掺杂多晶硅栅极。
本发明提供的一优选实施例中,其中所述非掺杂多晶硅硬掩膜层和N型掺杂多晶硅硬掩膜层之间的厚度差值通过以下公式计算:
其中:THM_Ppoly为厚度差;ERHM_HM为硬掩膜层刻蚀速度;ERPpoly_HM为非掺杂多晶硅刻蚀速度;TPpoly_etch为需要被刻蚀的非掺杂多晶硅的厚度,TPpoly_etch通过以下公式计算:
TPpoly_etch=TPpoly_remain
其中:TPpoly_remain为常规技术中非掺杂多晶硅刻蚀剩余量,TPpoly_remain通过以下公式计算:
其中:Tpoly为多晶硅总厚度,ERPpoly_poly为非掺杂多晶硅刻蚀速率,ERNpoly_poly为N型掺杂多晶硅刻蚀速率。
本发明提供的一优选实施例中,其中所述非掺杂多晶硅硬掩膜层刻蚀时间通过以下公式计算:
其中:TimeHM_etch为非掺杂多晶硅硬掩膜层刻蚀时间,ERHM_HM为硬掩膜层刻蚀速率,THM_Ppoly为需要被刻蚀除去非掺杂多晶硅硬掩膜层的厚度,THM_Ppoly通过以下公式计算:
其中:THM_Ppoly为厚度差;ERHM_HM为硬掩膜层刻蚀速度;ERPpoly_HM为非掺杂多晶硅刻蚀速度;TPpoly_etch为需要被刻蚀的非掺杂多晶硅的厚度,TPpoly_etch通过以下公式计算:
TPpoly_etch=TPpoly_remain
其中:TPpoly_remain为常规技术中非掺杂多晶硅刻蚀剩余,TPpoly_remain通过以下公式计算:
其中:Tpoly为多晶硅总厚度,ERPpoly_poly为非掺杂多晶硅刻蚀速率,ERNpoly_poly为N型掺杂多晶硅刻蚀速率。
本发明提供的方法能有效改善N型掺杂与非掺杂多晶硅栅极刻蚀后形貌差异。
附图说明
图1是本发明实施例中对非掺杂多晶硅硬掩膜层进行刻蚀的结构示意图。
图2是本发明实施例中形成不同厚度硅硬掩膜层后的结构示意图。
图3是本发明实施例中沉积防反射层后的结构示意图。
图4是本发明实施例中完成刻蚀硬掩膜层后的结构示意图。
图5是本发明实施例中形成N型掺杂多晶硅栅极和非掺杂多晶硅栅极后的结构示意图。
具体实施方式
本发明提供一种改进N型掺杂与非掺杂多晶硅栅极刻蚀后形貌差异的方法,利用形成N型掺杂多晶硅栅极上较厚的硬掩膜层,来弥补由于N型掺杂多晶硅刻蚀速率大于非掺杂多晶硅刻蚀速率而造成N型与非掺杂多晶硅栅极刻蚀后形貌差异。
以下通过实施例对本发明提供的方法做进一步详细说明,以便更好理解本发明创造,但实施例的内容并不限制本发明创造的保护范围。
如图1所示,在具有N型掺杂多晶硅31和非掺杂多晶硅32的衬底板1上沉积一层硬掩膜层41、42,分别形成N型掺杂多晶硅硬掩膜层41和非掺杂多晶硅硬掩膜层42,对非掺杂多晶硅硬掩膜层42进行刻蚀使得其厚度小于N型掺杂多晶硅硬掩膜层41,所形成的结构如图2所示。
如图3所示,在不同厚度的N型掺杂多晶硅硬掩膜层41和非掺杂多晶硅硬掩膜层42上沉积一防反射层5。对整个器件进行预设定图案进行刻蚀,刻蚀至露出N型掺杂多晶硅31为止,形成的结构如图4所示。
去除刻蚀过程留下在器件表面的残留物,后对器件进行刻蚀分别形成N型掺杂掺杂多晶硅栅极41和非掺杂多晶硅栅极42,形成的结构如图5所示。
在多晶硅栅极刻蚀步骤中,由于N型掺杂掺杂多晶硅31与非掺杂多晶硅32之间存在刻蚀速率差。需要确定当N型掺杂掺杂多晶硅栅极刻蚀结束时,非掺杂多晶硅栅极还剩余的量,该剩余量通过以下公式计算得出:
其中,TPpoly_remain为常规技术中非掺杂多晶硅刻蚀剩余,Tpoly为多晶硅总厚度,ERPpoly_poly为非掺杂多晶硅刻蚀速率,ERNpoly_poly为N型掺杂多晶硅刻蚀速率。
由于非掺杂多晶硅剩余量就等于硬掩膜层刻蚀中需要被刻蚀非掺杂多晶硅的厚度TPpoly_etch,所以
TPpoly_etch=TPpoly_remain (2)
在硬掩膜层刻蚀步骤中,通过硬掩膜层刻蚀速率与非掺杂多晶硅刻蚀速率差,确定非掺杂多晶硅栅极上局部硬掩膜层被刻蚀的量,即非掺杂多晶硅硬掩膜层和N型掺杂多晶硅硬掩膜层之间的厚度差值THM_Ppoly,该厚度差值通过以下公式计算得出:
其中:ERHM_HM为硬掩膜层刻蚀速度;ERPpoly_HM为非掺杂多晶硅刻蚀速度。
通过计算得出的厚度差值THM_Ppoly和硬掩膜层的刻蚀速率,可以计算出非掺杂多晶硅栅极上局部硬掩膜层刻蚀时间TimeHM_etch,刻蚀时间TimeHM_etch通过以下公式计算得出:
以上对本发明的具体实施例进行了详细描述,但其只是作为范例,本发明并不限制于以上描述的具体实施例。对于本领域技术人员而言,任何对本发明进行的等同修改和替代也都在本发明的范畴之中。因此,在不脱离本发明的精神和范围下所作的均等变换和修改,都应涵盖在本发明的范围内。
Claims (3)
1.降低N型掺杂和非掺杂多晶硅栅极刻蚀后形貌差异的方法,其特征在于,包括以下顺序步骤:
步骤1:在具有N型掺杂多晶硅和非掺杂多晶硅的衬底板上沉积一层硬掩膜层,分别形成N型掺杂多晶硅硬掩膜层和非掺杂多晶硅硬掩膜层,对非掺杂多晶硅硬掩膜层进行刻蚀使得其厚度小于N型掺杂多晶硅硬掩膜层;
步骤2:在不同厚度的N型掺杂多晶硅硬掩膜层和非掺杂多晶硅硬掩膜层上沉积一防反射层,对整个器件进行预设定图案进行刻蚀,刻蚀至露出N型掺杂多晶硅为止;
步骤3:去除刻蚀过程留下在器件表面的残留物,后对器件进行刻蚀分别形成N型掺杂多晶硅栅极和非掺杂多晶硅栅极。
2.根据权利要求1所述方法,其特征在于,所述非掺杂多晶硅硬掩膜层和N型掺杂多晶硅硬掩膜层之间的厚度差值通过以下公式计算:
其中:THM_Ppoly为厚度差,
ERHM_HM为硬掩膜层刻蚀速度,
ERPpoly_HM为非掺杂多晶硅刻蚀速度,
TPpoly_etch为需要被刻蚀的非掺杂多晶硅的厚度,TPpoly_etch通过以下公式计算:
TPpoly_etch=TPpoly_remain
其中:TPpoly_remain为常规技术中非掺杂多晶硅刻蚀剩余量,TPpoly_remain通过以下公式计算:
其中:Tpoly为多晶硅总厚度,
ERPpoly_poly为非掺杂多晶硅刻蚀速率,
ERNpoly_poly为N型掺杂多晶硅刻蚀速率。
3.根据权利要求1所述方法,其特征在于,所述非掺杂多晶硅硬掩膜层刻蚀时间通过以下公式计算:
其中:TimeHM_etch为非掺杂多晶硅硬掩膜层刻蚀时间,
ERHM_HM为硬掩膜层刻蚀速率,
THM_Ppoly为需要被刻蚀除去非掺杂多晶硅硬掩膜层的厚度,THM_Ppoly通过以下公式计算:
其中:THM_Ppoly为厚度差,
ERHM_HM为硬掩膜层刻蚀速度,
ERPpoly_HM为非掺杂多晶硅刻蚀速度,
TPpoly_etch为需要被刻蚀的非掺杂多晶硅的厚度,TPpoly_etch通过以下公式计算:
TPpoly_etch=TPpoly_remain
其中:TPpoly_remain为常规技术中非掺杂多晶硅刻蚀剩余,TPpoly_remain通过以下公式计算:
其中:Tpoly为多晶硅总厚度,
ERPpoly_poly为非掺杂多晶硅刻蚀速率,
ERNpoly_poly为N型掺杂多晶硅刻蚀速率。
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CN102867743A (zh) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | 改善掺杂与非掺杂多晶硅栅极刻蚀形貌差异的方法 |
CN109887842A (zh) * | 2019-01-08 | 2019-06-14 | 上海华虹宏力半导体制造有限公司 | 多晶硅的刻蚀方法 |
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US20130316539A1 (en) | 2013-11-28 |
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