CN102683377A - Double-drain type CMOS magnetic field induction transistor and fabricating method thereof - Google Patents

Abstract

The invention discloses a double-drain type CMOS (Complementary Metal-Oxide-Semiconductor) magnetic field induction transistor and a fabricating method thereof. The double-drain type CMOS magnetic field induction transistor comprises a P type substrate, two n+ drain doped region, an n+ source doped region, a p+ substrate contact doped region, a polycrystalline silicon gate and a silicon dioxide oxide layer. The method comprises the following steps of: firstly, growing the silicon dioxide oxide layer and the polycrystalline silicon gate on the P type substrate; and secondly, generating a source n+ heavily doped region and a drain n+ heavily doped region and the p+ substrate contact doped region on the two sides of the polycrystalline silicon gate, wherein the drain n+ heavily doped region is divided into two same regions having a certain distance therebetween. The double-drain structure is capable of realizing induction to a magnetic field under the action of the magnetic field to current carriers in an inversion layer formed under the transistor and is completely compatible with standard CMOS process; and simultaneously, compared with a magnetic sensor of a hall disc structure, the double-drain type CMOS magnetic field induction transistor is lower in power consumption.

Description

A kind of pair of drain type CMOS magnetic field induction transistor and preparation method thereof

Technical field

The present invention relates to a kind of CMOS magnetic field sensor transistor, particularly CMOS magnetic field sensor transistor of a kind of pair of drain type magnetic field induction transistor arrangement and preparation method thereof.

Background technology

Hall effect has been widely used in the design of magnetic field sensor, particularly integrated with standard CMOS process.Common a kind of way is to use CMOS Hall disc structure at present; Promptly let bias current pass through a square semi-conducting material (like N trap resistance); When magnetic field vertically was added in semiconductor surface, the semiconductor both sides can produce voltage difference, thereby had realized the induction to magnetic field.But be generally the bigger magnetic field induction sensitivity of acquisition, the CMOS Hall disc need provide bigger bias current, so power consumption is bigger.In addition, the Hall disc structure is comparatively complicated, is unfavorable for the realization of extensive magnetic field induction array system.

Summary of the invention

In order to solve the problems of the technologies described above, the present invention provides a kind of two drain type magnetic field induction transistors that can be used for extensive CMOS technology and preparation method thereof.

The technical scheme that the present invention solves the problems of the technologies described above is: the two drain type magnetic field induction transistors of a kind of CMOS comprise P type substrate, two n+ drain doping region; The n+ source doping region, polysilicon gate, silicon dioxide oxide layer; On P type substrate, generate silicon dioxide oxide layer and polysilicon gate earlier; Generate source electrode n+ heavily doped region and drain electrode n+ heavily doped region then respectively in the polysilicon gate both sides, the n+ heavily doped region that wherein drains is divided into two same area, and midfeather is apart from d.

A kind of pair of transistorized manufacture method of drain type CMOS magnetic field induction may further comprise the steps:

1) growth layer of silicon dioxide layer on P type substrate;

2) utilize polycrystalline lithography mask version manufacturing polycrystalline silicon grid;

3) make source electrode and drain electrode in the polysilicon gate both sides, and remove the silicon dioxide on source electrode and the drain diffusion window with photoetching technique;

4) utilize the n+ doped region to flood the film version and make source electrode and drain electrode n+ doped region;

5) on polysilicon gate and source electrode and drain electrode n+ doped region, generate contact hole, and plate layer of metal film;

6) on metal film, carve the electrode of grid, source electrode and drain electrode.

Owing to adopt technique scheme; The invention has the beneficial effects as follows: (1) this CMOS magnetic field induction transistor AND gate standard CMOS transistor is almost completely identical; Two kinds difference only is that CMOS magnetic field induction transistor drain is divided into two separate zones; Therefore this kind CMOS magnetic field induction transistor can manufacture and design on standard CMOS process, and integrated magneto-dependent sensor system provides a kind of simple and feasible scheme for high density.(2) in magnetic field, the transistorized source electrode of two drain electrode magnetic field inductions is applied bias current; Because Hall effect; Two separate drain electrodes can receive the electric current that differs in size, and this difference between current is proportional to magnetic flux density, thereby have realized the induction to magnetic field easily.

Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed description.

Description of drawings

Fig. 1 is that the axle that waits of the present invention is surveyed view.

Fig. 2 is a structural representation of the present invention.

Magnetic field induction principle schematic of the present invention when Fig. 3 is applied on the transistor for there not being magnetic field.

Magnetic field induction principle schematic of the present invention when Fig. 4 is applied on the transistor for magnetic field.

Embodiment

Like Fig. 1, shown in 2, the two drain type magnetic field induction transistors of CMOS of the present invention comprise 105, two n+ drain doping region of P type substrate 103,104, n+ source doping region 102, polysilicon gate 101, silicon dioxide oxide layer 106, metal contact hole 107.On P type substrate, generate silicon dioxide oxide layer and polysilicon gate earlier, generate source electrode n+ heavily doped region and drain electrode n+ heavily doped region then in the polysilicon gate both sides respectively, the n+ heavily doped region that wherein drains is divided into two same area, midfeather certain distance.

The two transistorized concrete manufacturing process of drain type magnetic field induction of CMOS, narrate as follows:

(1) growth layer of silicon dioxide layer 106 on P type substrate 105;

(2) remove the silicon dioxide on source electrode n+ doped region 102 and drain electrode n+ doped region 103 and the 104 diffusion windows with photoetching technique;

(3) utilize polycrystalline lithography mask version manufacturing polycrystalline silicon grid 101;

(4) utilize the n+ doped region to flood the film version and make source electrode n+ doped region 102 and drain electrode n+ doped region 103 and 104;

(5) on polysilicon gate 101 and source electrode n+ doped region 102 and drain electrode n+ doped region 103,104, generate contact hole, and plate layer of metal film;

(6) on metal film, carve the electrode of grid, source electrode and drain electrode.

Like Fig. 3, shown in 4, a kind of pair of drain type CMOS magnetic field induction transistor comprises polysilicon gate 201, source electrode n+ doped region 202,203, the second drain electrodes of first drain electrode n+ doped region n+ doped region 204.Bias current flows into from source electrode n+ doped region 202, and constant bias voltage is applied on the polysilicon gate 201.When not having magnetic field to be applied on the transistor, as shown in Figure 3, electric current will flow out from two drain electrode n+ doped regions 203 and 204 respectively uniformly, and therefore the magnetic field induction difference between current of equivalence is zero.

When magnetic field is applied on the transistor; As shown in Figure 4, under the effect of long-range navigation thatch power, below polysilicon gate 201 in the formed conducting channel; The direction of motion of charge carrier squints; Therefore can when two drain electrode n+ doped regions 203 and 204 flow out, change from the electric current that source electrode n+ doped region 202 flows into this moment, the electric current that flows out from drain electrode n+ doped region 204 can increase gradually, and the electric current that flows out from drain electrode n+ doped region 203 can reduce gradually; The formed difference between current of the electric current that this two-way changes is directly proportional with the magnetic field intensity that is applied, thereby has effectively realized the induction to magnetic field.The length L of polysilicon gate 201 wherein; The width W of source electrode n+ doped region 202; And the spacing d of two drain electrode n+ doped regions 203 and 204 plays key influence to transistorized magnetic field induction sensitivity, for obtaining maximized magnetic field induction sensitivity, W; The value magnitude of L and d is respectively 100um, 100um and 10um.

Claims (3)

1. a two drain type CMOS magnetic field induction transistor is characterized in that: comprise P type substrate, two n+ drain doping region; The n+ source doping region, polysilicon gate, silicon dioxide oxide layer; On P type substrate, generate silicon dioxide oxide layer and polysilicon gate earlier, generate source electrode n+ heavily doped region and drain electrode n+ heavily doped region then in the polysilicon gate both sides respectively, and p+ substrate contact doping district; The length of polysilicon gate is L; The width of source electrode n+ heavily doped region is W, and the n+ heavily doped region that wherein drains is divided into two same area, and midfeather is d.

2. according to claim 1 pair of drain type CMOS magnetic field induction transistor, it is characterized in that: the value of W, L and d is respectively 100um, 100um and 10um.

3. two transistorized manufacture method of drain type CMOS magnetic field induction may further comprise the steps:

1) growth layer of silicon dioxide layer on P type substrate;

2) utilize polycrystalline lithography mask version manufacturing polycrystalline silicon grid;

3) make source electrode and drain electrode in the polysilicon gate both sides, and remove the silicon dioxide on source electrode and the drain diffusion window with photoetching technique;

4) utilize n+ doped region and p+ doped region to flood the film version respectively and make source electrode and drain electrode n+ doped region and p+ substrate contact doping district;

5), generate contact hole in source electrode and drain electrode n+ doped region and the p+ substrate contact doping district, and plate layer of metal film at polysilicon gate;

6) on metal film, carve the electrode of grid, source electrode and drain electrode.

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